Adc Control Register 2 (Adcr2); Zero Crossing Control Register (Adzcc1 And Adzcc2) - Freescale Semiconductor 56F800 User Manual

9.8.2 ADC Control Register 2 (ADCR2)

15 14
BASE+$1
Read 0 0
Write
Reset 0 0
9.8.2.1 Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
9.8.2.2 Clock Divisor Select (DIV)—Bits 4–0
ADC_CLK can be run at a slower rate than the IPBus clock. The divider circuit provides a clock
of period 2N of the IPBus clock where N = DIV[4:0]+1. A divisor must be chosen allowing the
ADC clock to remain within specified limits. For a IPBus Clock frequency of 40MHz and a
desired ADC_CLK frequency of 2.5MHz, a DIV[4:0] value of 7d is required.
Note: The maximum frequency ADC can operate is 2.5MHz. DIV[4:0]. ADC should not be
programmed for ADC_CLK frequency more than 2.5MHz. At higher frequencies, the
accuracy of the ADC will be less than its specified value.

9.8.3 Zero Crossing Control Register (ADZCC1 and ADZCC2)

The Zero Crossing Control (ADZCC) register provides the ability to monitor the selected channels
and select the direction of zero crossing that triggers the optional interrupt. Zero crossing logic
monitors only the sign change between current and previous sample. ZCE0 monitors the sample
stored in ADRSLT0 and ZCE9 monitors ADRSLT9. When the zero crossing is disabled for a
selected result register, sign changes are not monitored and updated in the ADZSTAT but are
properly stored in the respective result register.
15 14
BASE+$2
Read
ZCE7
Write
Reset 0 0
Figure 9-3. ADC Zero Crossing Control Register (ADZCC1)
Freescale Semiconductor
13 12 11 10
0 0 0 0
0 0 0 0
Figure 9-2. ADC Control Registers 2 (ADCR2)
13 12 11 10
ZCE6 ZCE5
0 0 0 0
See Programmer's Sheets on Appendix page B- 53
Analog-to-Digital Converter (ADC), Rev. 3
9 8 7 6 5
0 0 0 0 0
0 0 0 0 0
9 8 7 6 5
ZCE4 ZCE3 ZCE2
0 0 0 0 0
Register Definitions
4 3 2 1 0
DIV
0 0 0 0 0
4 3 2 1 0
ZCE1 ZCE0
0 0 0 0 0
17