Adc Sample Disable Register (Adsdis); Adc Core - Freescale Semiconductor 56F800 User Manual

• SAMPLE7: AN4 single-ended
• SAMPLE8: AN8+ and AN3- differential
• SAMPLE9: AN2+ and AN7- differential.
AN0 —
AN1 —
AN2 —
AN3 —
AN4 —
AN5 —
AN6 —
AN7 —
AN8 —
AN9 —

9.8.5 ADC Sample Disable Register (ADSDIS)

This register is an extension to the ADLST1, 2, 3,4, and 5 providing the ability to enable only the
desired samples programmed in the SAMPLE0–SAMPLE9. A sample sequence is terminated
when the first disabled sample is encountered. The power on default is all samples enabled. For
example: if in sequential mode, DS5 is set to 1 and rest all set to 0, only SAMPLE0 through
SAMPLE4 are sampled.
15 14
BASE+$9
Read 0 0
Write
Reset 0 0
Figure 9-10. ADC Sample Disable Register (ADSDIS)
9.8.5.1 Reserved—Bits 15–10
This bit field is reserved or not implemented. It cannot be read or modified.
Freescale Semiconductor
Analog Core
ADC_Plus
A / D
Analog
Core
MUX
ADC_Minus
Figure 9-8. ADC Core
13 12 11 10
0 0 0 0
0 0 0 0
See Programmer's Sheets on Appendix page B- 56
Analog-to-Digital Converter (ADC), Rev. 3
12-Bits
12-Bits
Output
Latch
Data_Rdy
9 8 7 6 5
DS9 DS8 DS7 DS6 DS5
0 0 0 0 0
Register Definitions
Digital
Core
4 3 2 1 0
DS4 DS3 DS2 DS1 DS0
0 0 0 0 0
21