Port A Operation With Drv Bit = 0 - Freescale Semiconductor 56F800 User Manual

16-bit digital signal controllers

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3.3.1.1 Reserved—Bits 15–10

This bit field is reserved or not implemented. It is read/written as 0.

3.3.1.2 Drive (DRV)—Bit 9

The Drive Control bit is used to specify what occurs on the external memory port pins when no

external access is performed—whether the pins remain driven or are tri-stated. The Drive (DRV)

bit is cleared on hardware reset. Please see

Normal Mode, External Access

Normal Mode, Internal Access

Normal Mode, External Access

Normal Mode, Internal Access

3.3.1.3 Reserved—Bit 8

This bit field is reserved or not implemented. It is read/written as 0.

Freescale Semiconductor

Table 3-4. Port A Operation with DRV Bit = 0

Table 3-5. Port A Operation with DRV = 1

Memory and Operating Modes, Rev. 3

PS, DS, RD, WR

Pulled High Internally

PS, DS, RD, WR

Pulled high internally

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