Once Control Register (Ocr); Cop Timer Disable (Copdis)-Bit 15; Ocr Programming Model - Freescale Semiconductor 56F800 User Manual

Command, Status, and Control Registers

16.7.4 OnCE Control Register (OCR)

The 16-bit OnCE Control Register (OCR) contains bit fields determining how breakpoints are
triggered, what action occurs when a OnCE event occurs, as well as controlling other
miscellaneous OnCE features.
OCR—$02 15
Read
COP
DIS
Write
Reset 0
16.7.5 COP Timer Disable (COPDIS)—Bit 15
The COP Disable (COPDIS) timer bit is used to prevent the COP timer from resetting the chip
when it times out. When COPDIS is cleared, the COP timer is enabled. When COPDIS is set, the
COP timer is disabled.
Note: When the COP Enable (CPE) bit in the COP/RTI Control (COPCTL) register is
cleared, the COP timer is not enabled. In this case, the COPDIS bit has no effect on the
deactivated COP timer. That is, COP reset can not be generated. However, the
COPDIS bit overrides the CPE bit when both are set.
16.7.5.1 Reserved—Bit 14
This bit is reserved or not implemented. It must always remain 0.
16.7.5.2 Breakpoint Configuration (BK)—Bits 13–9
The Breakpoint (BK) configuration bits are used to configure the operation of the OnCE module
when it enters the debug processing state. In addition, these bits can also be used to setup a
breakpoint on one address and an interrupt on another address.
breakpoint configurations.
16
Figure 16-9 illustrates the OCR and its fields.
14 13 12 11 10
0
BK4 BK3 BK2 BK1
0 0 0 0 0
Figure 16-9. OCR Programming Model
56F826/827 User Manual, Rev. 3
9 8 7 6 5
0
BK0 FH EM1 EM0 PWD BS1
0 0 0 0 0
Table 16-10
4 3 2 1 0
BS0 BE1 BE0
0 0 0 0 0
lists the different
Freescale Semiconductor