Download Print this page

Freescale Semiconductor 56F800 User Manual

16-bit digital signal controllers

Hide thumbs Also See for 56F800:

User manual (56 pages)

,

User manual (56 pages)

Table Of Contents

page of 630

/ 630
Contents
Table of Contents
Bookmarks

Table of Contents

Advertisement

Quick Links

Download this manual

DSP56F826/827

User Manual

56F800

16-bit Digital Signal Controllers

DSP56F826-827UM

Rev. 3.0

09/2005

freescale.com

Table of Contents

Advertisement

Table of Contents

Need help?

Need help?

Do you have a question about the 56F800 and is the answer not in the manual?

Questions and answers

Summary of Contents for Freescale Semiconductor 56F800

Page 1 DSP56F826/827 User Manual 56F800 16-bit Digital Signal Controllers DSP56F826-827UM Rev. 3.0 09/2005 freescale.com...
Page 2 This manual is one of a set of three documents. You need the following manuals to have complete product information: Family Manual, User’s Manual, and Technical Data Sheet. Order this document by DSP56F826-827UM - Rev. 5.0 March, 2005 Summary of Changes and Updates: Clarified SPI Chapter Section 12.9.1.7 Clarified statement in GPIO Chapter immediately aboveTable 8-2 Converted to Freescale look and feel...
Page 3: Table Of Contents
Serial Peripheral Interface (SPI) ........1-23 1.10.5 COP/Watchdog Timer and Modes of Operation Module....1-23 Freescale Semiconductor Table of Contents - i...
Page 4 External Mode (Mode 3) ..........3-29 56F826/827 User Manual, Rev. 3 Table of Contents - ii Freescale Semiconductor...
Page 5 Serial Communications Interface (SCI0)....... . . 5-7 Freescale Semiconductor Table of Contents - iii...
Page 6 Flash Erase Enable Register (FIU_EE) ....... . 6-20 56F826/827 User Manual, Rev. 3 Table of Contents - iv Freescale Semiconductor...
Page 7 Register Summary ........... . 8-9 Freescale Semiconductor...
Page 8 ADC Offset Registers (ADOFS0–9) ........9-30 56F826/827 User Manual, Rev. 3 Table of Contents - vi Freescale Semiconductor...
Page 9 Transmission Formats ..........11-9 Freescale Semiconductor...
Page 10 Normal Mode........... . 12-37 56F826/827 User Manual, Rev. 3 Table of Contents - viii Freescale Semiconductor...
Page 11 TMR Comparator Load Register 2 (CMPLD2)–56F827 Only ....13-21 12.7.11 TMR Comparator Status and Control Register (COMSCR)– 56F827 Only ..13-21 Freescale Semiconductor Table of Contents - ix...
Page 12 Register Definitions ..........15-8 56F826/827 User Manual, Rev. 3 Table of Contents - x Freescale Semiconductor...
Page 13 OnCE Trace Logic Operation ........16-40 Freescale Semiconductor...
Page 14 Programmer’s Sheets..........C-13 56F826/827 User Manual, Rev. 3 Table of Contents - xii Freescale Semiconductor...
Page 15 ........8-14 Freescale Semiconductor...
Page 16 SSI Receive Data Register (SRX)........12-12 56F826/827 User Manual, Rev. 3 List of Figures - xiv Freescale Semiconductor...
Page 17 OnCE PDB Register (OPDBR) ........16-30 Freescale Semiconductor...
Page 18 TAP Controller State Diagram........17-25 56F826/827 User Manual, Rev. 3 List of Figures - xvi Freescale Semiconductor...
Page 19 F56827 Data Memory Peripheral Address Map ......3-15 3-13 System Control Registers Address Map (SYS_BASE = $1000)....3-15 Freescale Semiconductor List of Tables - xvii...
Page 20 ITCN Memory Map ..........5-11 56F826/827 User Manual, Rev. 3 List of Tables - xviii Freescale Semiconductor...
Page 21 Loop Functions ..........10-16 Freescale Semiconductor...
Page 22 GO Bit Definition ..........16-15 56F826/827 User Manual, Rev. 3 List of Tables - xx Freescale Semiconductor...
Page 23 List of Programmer’s Sheets......... C-13 Freescale Semiconductor...
Page 24 56F826/827 User Manual, Rev. 3 List of Tables - xxii Freescale Semiconductor...
Page 25 Port A. Chapter Flash Memory Interface (FLASH) describes the Program Flash, Data Flash, and Boot Flash features and registers. Chapter External Memory Interface (EMI) provides the External Memory Interface available on the 56F826/827. Preface, Rev. 3 Freescale Semiconductor xxiii...
Page 26 56F826/827 registers. Additional information • See http//:www.freescale.com/ for the most current BSDL listings. • See device Techical Data Sheet for package and pin-out information. 56F826/827 User Manual, Rev. 3 xxiv Freescale Semiconductor...
Page 27 • When a bit is described as set, its value is set to one. When a bit is described as cleared, its value is set to zero. • Pins, or signals asserted low, made active when pulled to ground, have an overbar above their name. For example, the SS0 pin is asserted low. Preface, Rev. 3 Freescale Semiconductor...
Page 28: Pin Conventions
PWM generator is currently using. Table 0-1. Pin Conventions Signal/Symbol Logic State Signal State Voltage True Asserted False Deasserted True Asserted False Deasserted 1.Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 56F826/827 User Manual, Rev. 3 xxvi Freescale Semiconductor...
Page 29: 56F826/827 Overview
Chapter 1 56F826/827 Overview 56F826/827 Overview, Rev. 3 Freescale Semiconductor...
Page 30 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 31: Introduction
• Uninterruptable power supplies • Telephony system implementation • Noise cancellation applications • Home security • Steppers and encoders • Temperature regulation • HVAC applications • Remote monitoring and control • Digital telephone answering machine 56F826/827 Overview, Rev. 3 Freescale Semiconductor...
Page 32: 56800 Family Description
(TMR). Any of these interfaces can be used as a General-Purpose In/Out (GPIO) if those functions are not required. An internal Interrupt Controller and dedicated GPIO, are also included on some of the parts. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 33: 56800 Core Description
• Address Generation Unit (AGU) • Program controller and hardware looping unit • Bit Manipulation Unit • On-Chip Emulation (OnCE) port • Interrupt Controller • External Bus Bridge • Address buses • Data buses 56F826/827 Overview, Rev. 3 Freescale Semiconductor...
Page 34: Core Block Diagram
Likewise, each functional unit interfaces with other units, with memory, and with memory-mapped peripherals over the core’s internal address and data buses, illustrated in Figure 1-2. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 35: Bus Block Diagram
Data ALU. The architecture is pipelined to take advantage of the parallel units and significantly decrease the execution time of each instruction. 56F826/827 Overview, Rev. 3 Freescale Semiconductor...
Page 36: Architectural Overview
Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 37: 56F826 Features
• Simple port interface with other asynchronous serial communication devices • Simple port interface with other asynchronous serial peripheral communication devices and off-chip EE memory • Sophisticated debugging using OnCE to view core, peripheral, and memory contents 56F826/827 Overview, Rev. 3 Freescale Semiconductor...
Page 38: 56F827 Description
The 56F827 is well-suited for many applications such as: • Noise suppression • Identification tag readers • Sonic/subsonic detectors • Security access devices • Remote metering 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 39: 56F827 Features
• Up to 64K × 16-bit words external memory expansion for program and Data Memory • JTAG/OnCE for debugging • MCU-friendly instruction set supports controller functions: MAC, Bit Manipulation Unit (BMU), 14 addressing modes • 8-channel programmable chip select • 10-channel, 12-bit Analog-to-Digital Converter (ADC) 56F826/827 Overview, Rev. 3 Freescale Semiconductor...
Page 40: 56F827 Benefits
• Capable of Analog-to-Digital Converter (ADC) functionality utilizing Quad Timer to provide independence to each channel timer • Sophisticated debugging using OnCE to view the core, peripheral, and memory contents • Power-saving analog shut-down mode 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 41: 56F827 Block Diagram
Data Bus GPIOG16[00:16] Switch Memory & PCS [2:7} ADDRESS Programmable BUS [8:0] Chip Select Peripherals PS or PCS DS or PCS Dedicated DATA Control GPIO BUS [15:0] Timer Figure 1-4. 56F827 Block Diagram 56F826/827 Overview, Rev. 3 Freescale Semiconductor...
Page 42: 56F826/827 Features
• Two 32-bit accumulator registers • Two 4-bit accumulator extension registers • One parallel, single cycle, non-pipelined MAC unit • An accumulator shifter • One data limiter • One MAC output limiter • One 16-bit barrel shifter 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 43: Address Generation Unit (Agu)
Its arithmetic unit can perform linear and modulo arithmetic. 1.7.3 Program Controller and Hardware Looping Unit The Program Controller performs: • Instruction prefetch • Instruction decoding • Hardware loop control • Interrupt (exception) processing 56F826/827 Overview, Rev. 3 Freescale Semiconductor...
Page 44: Bit Manipulation Unit (Bmu)
The External Address Bus (EAB) provides addresses for external memory. Data movement on both the 56F80x occurs over three bidirectional, 16-bit buses and at least one unidirectional 16-bit bus: • CGDB bidirectional • PDB bidirectional 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 45: Address And Data Buses
Program Data Bus 16-bit Unidirectional Instruction Word Fetches PGDB Peripheral Global Data Bus 16-bit Unidirectional Internal Data Movement XDB2 X Data Bus 2 16-bit Unidirectional Internal Data Movement External Data Bus 16-bit Bidirectional External Data Movement 56F826/827 Overview, Rev. 3 Freescale Semiconductor...
Page 46: On-Chip Emulation (Once) Module
• The PLL is designed to run for at least 100 instruction cycles if the oscillator source is removed. • The PLL generates output frequencies up to 80MHz. • The PLL can be bypassed to use an oscillator or prescalar outputs directly. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 47: Resets
Unaligned word,16-bit and byte, or long word 32-bit accesses are not supported on this IPBus. The 56800 supports only 16-bit word transfers on word boundaries. The IPBus Bridge also provides upper level address decoding and peripheral module enable generation. 56F826/827 Overview, Rev. 3 Freescale Semiconductor...
Page 48: Memory Modules
• Can be programmed and erased under software control • Optional interrupt on completion of intelligent program and erase functions 1.8.2 Program RAM • Single port RAM is compatible with the pipelined program bus structure • Single cycle reads at 40MHz 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 49: Data Flash
• Two external interrupt pins • Eight-channel programmable chip selects (56F827 only) • External RESET pin for hardware reset • JTAG/OnCE for unobtrusive, processor speed-independent debugging • Software-programmable, PLL-based frequency synthesizer for the core clock 56F826/827 Overview, Rev. 3 Freescale Semiconductor...
Page 50: Peripheral Descriptions
• Wait states programmable through BCR register of DSP56800 core. Changing number of wait states affects all chip select together. • Each chip select can be assigned either program memory or Data Memory or both. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 51: General-Purpose Input/Output Port (Gpio)
• Configurable for either master or slave operation • Multiple slaves may be enabled using GPIO pins • Double-buffered operation with separate Transmit and Receive registers 1.10.5 COP/Watchdog Timer and Modes of Operation Module The COP module provides two separate functions: 56F826/827 Overview, Rev. 3 Freescale Semiconductor...
Page 52: Jtag/Once Port
1.10.7 Quad Timer Module (TMR) • 56F826 — Timer A with four pins • 56F827 — Timer A with four pins Quad timer features: • Four channels, independently programmable as input capture or output compare 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 53: Analog-To-Digital Converter (Adc)
Serial Peripheral Interface (SPI). SSI features: • SSI with configurable six-pin port (or six additional GPIO lines) • Normal mode operation using frame sync • Gated Clock mode operation requiring no frame sync 56F826/827 Overview, Rev. 3 Freescale Semiconductor...
Page 54: Time-Of-Day (Tod)
IPR found on the 56800 core and the Priority Level Registers (PLRs) found in the Interrupt Controller (ITCN). Chapter 5 provides more details on interrupt vectors. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 55: Pin Descriptions
Chapter 2 Pin Descriptions Pin Descriptions, Rev. 3 Freescale Semiconductor...
Page 56 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 57: Introduction
Interrupt and Program Control Table 2-18 Alternately, GPIO pins (56F826 SCIs cannot be used as GPIO) Alternately, two SCIs can be used as an SPI In addition, two Bus Control pins can be programmed as PCS [0-1] Pin Descriptions, Rev. 3 Freescale Semiconductor...
Page 58: 56F826 Functional Group Pin Allocations
TRST Program RESET Control EXTBOOT Includes TCS pin, which is reserved for factory use and is tied to V Figure 2-1. 56F826 Functional Group Pin Allocations Alternate pin functionality is shown in parentheses 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 59: 56F827 Functional Group Pin Allocations
Interrupt/ IRQB Program RESET Control EXTBOOT Includes TCS pin, which is reserved for factory use and is tied to VSS Figure 2-2. 56F827 Functional Group Pin Allocations Alternate pin functionality is shown in parentheses Pin Descriptions, Rev. 3 Freescale Semiconductor...
Page 60: Power And Ground Signals
V TCS—This pin is reserved for factory use. It must be tied to V for normal use. In block diagrams, this pin is considered an additional V Signal Type is Input/Output (Schmitt). 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 61: Clock And Phase Lock Loop Signals
XTAL and a version of the device master clock at the output of the PLL. The clock frequency on this pin can be disabled by programming the CLKO Select Register (CLKOSR). Pin Descriptions, Rev. 3 Freescale Semiconductor...
Page 62: Address, Data, And Bus Control Signals
Data memory accesses. (GPIOG0-15) Input/ Port G GPIO—These 16 General Purpose I/O (GPIO) pins Output can be individually programmed as input or output pins. After reset, the default state is Address Bus. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 63: Bus Control Signals
When RD is deasserted high, the external data is latched inside the device. When RD is asserted, it qualifies the A0–A15, PS, and DS pins. RD can be connected directly to the OE pin of a Static RAM or ROM. Pin Descriptions, Rev. 3 Freescale Semiconductor...
Page 64: Quad Timer Module Signals
Test Data Output—This tri-statable output pin provides a serial (Schmitt) output data stream from the JTAG/OnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling (Input/ edge of TCK. Output) 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 65: Synchronous Serial Interface
After reset, the default state is GPIO input. GPIOD0– Input/ Input Port D GPIO—These eight dedicated General Purpose I/O GPIOD7 Output (GPIO) pins can be individually programmed as input or output pins. After reset, the default state is GPIO input. Pin Descriptions, Rev. 3 Freescale Semiconductor...
Page 66: Synchronous Serial Interface (Ssi) Signals
Input/ (GPIOC3) Output Input Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of being individually programmed as input or output. After reset, the default state is GPIO input. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 67 (GPIOC5) Input/ Input Port C GPIO—This is a General Purpose I/O (GPIO) pin with Output the capability of being individually programmed as input or output. After reset, the default state is GPIO input. Pin Descriptions, Rev. 3 Freescale Semiconductor...
Page 68: Serial Peripheral Interface (Spi) Signals
In slave mode, this pin is used to select the slave. GPIOF7 Input/ Input Port F GPIO—This General Purpose I/O (GPIO) pin can be Output individually programmed as input or output. After reset, the default state is SS. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 69: Serial Communications Interface (Sci) Or Serial Peripheral Interface (Spi0) Signals
SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave. After reset, the default state is SCI input. 2.10 Serial Communications Interface (SCI) or General Purpose Input/Output (GPIO) Signals Pin Descriptions, Rev. 3 Freescale Semiconductor...
Page 70: (56F827 Only)
V and a start-up time of 25ms, prior to beginning conversions. ADC Reference—These pins are Positive Reference for ADC — VREFHI Input Input and are generally connected to a 3.3V Analog (V supply. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 71: Programmable Chip Select Signals (56F827 Only)
Table 2-17. Programmable Chip Selects No. of State Pins Signal Signal During Signal Description Name Type Reset — PCS2-7 Input/ Tri-stated Programmable Chip Select - PCS2-7 are asserted low for Output external peripheral chip select Pin Descriptions, Rev. 3 Freescale Semiconductor...
Page 72: Interrupt And Program Control Signals
OnCE/JTAG module. In this case, assert RESET, but do not assert TRST. EXTBOOT Input Input External Boot—This input is tied to V to force device to boot (Schmitt) from off-chip memory. Otherwise, it is tied to ground. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 73: Memory And Operating Modes
Chapter 3 Memory and Operating Modes Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 74 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 75: Introduction
The 56F826/827 Memory Map Description 3.1 Introduction Devices 56F826 and 56F827 are members of the 56F800 Family core-based hybrid controllers. Both combine the processing power and the functionality of a microcontroller with a flexible set of peripherals on a single chip. Because of their low cost, configuration flexibility and compact program code, both chips are well suited for many applications.
Page 76: Program Memory Map For 56F826/827
Mode 0B, as any reset or COP reset changes the memory map back to Mode 0A. Note: Modes 0A and 0B are supported in this group of devices. For more information about other modes, please see Section 3.7.2 Section 3.7.3. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 77: Data Memory
When EX=1, the segment (hole) does not exist and may be accessed like all other external data memory. Note: For 56800 core instructions performing two reads from the data memory in a single instruction, the second access using the R3 pointer always occurs to on-chip memory, Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 78 3.3.1 Bus Control Register (BCR) – X:$FFF9 Read WAIT STATE FIELD for WAIT STATE Field for EXTERNAL X-MEMORY EXTERNAL P-MEMORY Write Reset Figure 3-1. Bus Control Register (BCR) See Programmer’s Sheet on Appendix page C-19 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 79: Port A Operation With Drv Bit = 0
Stop Mode Driven Driven Tri-Stated Wait Mode Driven Driven Tri-Stated Reset Mode Tri-stated Pulled high internally Tri-stated 3.3.1.3 Reserved—Bit 8 This bit field is reserved or not implemented. It is read/written as 0. Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 80: Programming Wsx[3:0] Bits For Wait States
3.3.2 Operating Mode Register (OMR) Bits Read Write Reset Figure 3-2. Operating Mode Register (OMR) See Programmer’s Sheet on Appendix page C-20 * MA and MB are latched from the EXTBOOT pin on reset. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 81: Looping Status
When cleared, the C, N, V, and Z condition codes are generated based on bit 35 of the data ALU result. The generation of the L, E, and U condition codes is not affected by the CC bit. The CC bit is cleared by the processor reset. Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 82 When the SA bit is set, three bits determine if saturation is performed on the MAC unit’s output and whether to saturate to the maximum positive or negative value, as illustrated in Table 3-9. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 83: Mac Unit Outputs With Saturation Mode Enabled (Sa=1)
This bit is latched from the EXTBOOT pin on reset. Please see Section 3.7 in the DSP56800 Family Manual. 3.3.2.9 Reserved—Bit 2 This bit field is reserved or not implemented. It is a read/write field using 0. Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 84: Bus Control Register (Bcr)
OnCE PGDB Bus Transfer Register (OPGDBR) Reserved Reserved Reserved Accessible Using I/O Short Addressing X:$FFFB Interrupt Priority Register (IPR) Reserved X:$FFF9 Bus Control Register (BCR) Reserved Not Accessible At All When EX=1 Reserved 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 85: On-Chip Peripheral Memory Map
• Serial Peripheral Interface 0 (SPI0) • Serial Peripheral Interface 1 (SPI1) • Serial Communications Interface 0 (SCI0) • Serial Communications Interface 1 (SCI1) • General-Purpose I/O port A (GPIOA) • General-Purpose I/O port B (GPIOB) Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 86: 56F826 Data Memory Peripheral Address Map
GPIOC_BASE = $11C0 Table 3-32 GPIOD $11D0 - $11DF GPIOD_BASE = $11D0 Table 3-33 GPIOE $11E0 - $11EF GPIOE_BASE = $11E0 Table 3-34 GPIOF $11F0 - $11FF GPIOF_BASE = $11F0 Table 3-35 Reserved 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 87: F56827 Data Memory Peripheral Address Map
Register Register Description Address Offset Base Address Abbreviation SYS_CTRL System Control Register SYS_BASE SYS_STS System Status Register SYS_BASE MSH_ID Most Significant Half of JTAG_ID SYS_BASE LSH_ID Least Significant Half of JTAG_ID SYS_BASE Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 88: 56F827 Program Flash Interface Unit #2 Registers
Program Flash Terase Limit Register PFIU2_BASE PFIU_TMEL Program Flash Time Limit Register PFIU2_BASE PFIU_TNVSL Program Flash Tnvs Limit Register PFIU2_BASE PFIU_TPGSL Program Flash Tpgs Limit Register PFIU2_BASE PFIU_TPROGL Program Flash Tprog Limit Register PFIU2_BASE 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 89: 56F826 Boot Flash Interface Unit Registers Address Map
Boot Flash Erase Enable Register BFIU_BASE BFIU_ADDR Boot Flash Address Register BFIU_BASE BFIU_DATA Boot Flash Data Register BFIU_BASE BFIU_IE Boot Flash Interrupt Enable Register BFIU_BASE BFIU_IS Boot Flash Interrupt Source Register BFIU_BASE Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 90 Group Priority Register 10 ITCN_BASE ITCN_GPR11 Group Priority Register 11 ITCN_BASE ITCN_GPR12 Group Priority Register 12 ITCN_BASE ITCN_GPR13 Group Priority Register 13 ITCN_BASE ITCN_GPR14 Group Priority Register 14 ITCN_BASE ITCN_GPR15 Group Priority Register 15 ITCN_BASE 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 91: 56F826 Quad Timer A Registers Address Map
TMRA_BASE TMRA0_CMP2 Compare Register 2 TMRA_BASE TMRA0_CAP Capture Register TMRA_BASE TMRA0_LOAD Load Register TMRA_BASE TMRA0_HOLD Hold Register TMRA_BASE TMRA0_CNTR Counter Register TMRA_BASE TMRA0_CTRL Control Register TMRA_BASE TMRA0_SCR Status and Control Register TMRA_BASE Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 92: 56F827 Quad Timer A Registers Address Map
Counter Register TMRA_BASE TRMA2_CTRL Control Register TMRA_BASE TRMA2_SCR Status and Control Register TMRA_BASE TMRA2_CMPLD1 Comparator Load Register 1 TMRA_BASE TMRA2_CMPLD2 Comparator Load Register 2 TMRA_BASE TMRA2_COMSCR Comparator Status and Control Register 2 TMRA_BASE Reserved 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 93 Clock Scaler Load TOD_BASE TODSEC Seconds TOD_BASE TODSAL Seconds Alarm TOD_BASE TODMIN Minutes TOD_BASE TODMAL Minutes Alarm TOD_BASE TODHR Hours TOD_BASE TODHAL Hours Alarm TOD_BASE TODDAY Days TOD_BASE TODDAL Days Alarm TOD_BASE Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 94 Table 3-25. 56F827 SCI2 Registers Address Map ( SCI2_BASE = $1180 Register Register Description Address Offset Base Address Abbreviation SCI2_SCIBR Baud Rate Register SCI2_BASE SCI2_SCICR Control Register SCI2_BASE SCI2_SCISR Status Register SCI2_BASE SCI2_SCIDR Data Register SCI2_BASE 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 95 Table 3-29. Clock Generation Registers Address Map ( CLKGEN_BASE = $10F0 Register Register Description Address Offset Base Address Abbreviation PLLCR Control Register CLKGEN_BASE PLLDB Divide-By Register CLKGEN_BASE PLLSR Status Register CLKGEN_BASE Reserved CLKOSR CLKO Select Register CLKGEN_BASE Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 96 Data Direction Register GPIOC_BASE GPIO_C_PER Peripheral Enable Register GPIOC_BASE GPIO_C_IAR Interrupt Assert Register GPIOC_BASE GPIO_C_IENR Interrupt Enable Register GPIOC_BASE GPIO_C_IPOLR Interrupt Polarity Register GPIOC_BASE GPIO_C_IPR Interrupt Pending Register GPIOC_BASE GPIO_C_IESR Interrupt Edge-Sensitive Register GPIOC_BASE 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 97 Data Direction Register GPIOF_BASE GPIO_F_PER Peripheral Enable Register GPIOF_BASE GPIO_F_IAR Interrupt Assert Register GPIOF_BASE GPIO_F_IENR Interrupt Enable Register GPIOF_BASE GPIO_F_IPOLR Interrupt Polarity Register GPIOF_BASE GPIO_F_IPR Interrupt Pending Register GPIOF_BASE GPIO_F_IESR Interrupt Edge-Sensitive Register GPIOF_BASE Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 98 $23, $24, $25, $26, $27, ADHLMT0–9 ADC High Limit Registers 0–9 ADC_BASE $28, $29, $2A, $2B, $2C $2D, $2E, $2F, $30, $31, ADOFS0–9 ADC Offset Registers 0–9 ADC_BASE $32, $33, $34, $35, $36 Reserved 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 99: Program Memory
Both may be modified by the application itself. When mode three is selected, all 64K words of program memory are external. 1.All 56800 chips have two low order wait state bits in BCR hardcoded to zero. Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 100: Operating Modes
Note: Please refer to Section 15.8 Figure 15-8 for additional information about SYS_CNTL. If EXTBOOT is asserted low during reset, then Mode 0A boot is automatically entered when exiting the Reset mode. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 101: Modes One And Two (Modes 1 And 2)
PFLASH. However, if the entries do not agree, then the PFLASH is reloaded through one of the external ports. Control is then redirected to the code just loaded into memory. Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 102: Executing Programs From Xram
COP reset because these conditions Reset the chip. Resetting takes precedence over all other interrupts. Table 3-41 provides the reset and interrupt priority structure for the 56F826/827 chip, including on-chip peripherals. Table 3-42 lists the reset and interrupt 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 103: Reset And Interrupt Priority
Priority Level Starting Addresses — $0000 Hardware RESET — COP Timer Reset $0002 $0004 — Reserved $0006 Illegal Instruction Trap $0008 Software Interrupt (SWI) $000A Hardware Stack Overflow $000C OnCE Trap $000E Reserved Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 104: Memory Architecture
This greatly increases throughput on algorithms requiring a high bandwidth feed of data values. The simplified diagram on the following page shows chips’ on-board address. Data buses help to illustrate the allowed and disallowed parallel data. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 105: 56F80X On-Board Address And Data Buses
• Dual read RAM using CGDB and XFLASH using XDB2 • Dual read XRAM using XDB2 and XFLASH using CGDB • Single read XRAM using CGDB • Single read XFLASH using CGDB Memory and Operating Modes, Rev. 3 Freescale Semiconductor...
Page 106 Neither chip connects the PGDB from the core to the peripherals, so instructions utilizing this data bus such as MOVEP, are not useful. The MOVEP instruction only functions for registers internal to the core such as OnCE PGDB Bus Transfer Register (OPGDBR), IPR, and BCR. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 107: On-Chip Clock Synthesis (Occs)
Chapter 4 On-Chip Clock Synthesis (OCCS) On-Chip Clock Synthesis (OCCS), Rev. 3 Freescale Semiconductor...
Page 108 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 109: Introduction
• Ability to power-down the internal PLL • Selectable PLL source clock • Selectable system Clock (ZCLK) from three sources The clock generation module provides the programming interface for both the PLL and on- and off-chip oscillators. On-Chip Clock Synthesis (OCCS), Rev. 3 Freescale Semiconductor...
Page 110: Block Diagram
These include, from left to right: • Crystal oscillator, uses EXTAL and XTAL pins • External clock source, uses XTAL pin EXTAL External Crystal Crystal Clock Source XTAL Figure 4-2. Reference Clock Sources 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 111 It is recommended when changing the prescaler ratio or the divide-by ratio, powering down, or powering up, the PLL should be deselected as the clocking source. Only after a lock is achieved should the PLL be used as a valid clocking source. On-Chip Clock Synthesis (OCCS), Rev. 3 Freescale Semiconductor...
Page 112: Timing
External Clock mode of operations are discussed in Section 4.5.2. 4.5.2 External Crystal Design Considerations Either an external crystal oscillator or an external frequency source can be used to provide a reference clock to the 56F826/827. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 113: Crystal Oscillator
Figure 4-5. The external clock source is connected to XTAL while the EXTAL pin is held at V DSP56F82x XTAL EXTAL External Clock Figure 4-5. Connecting an External Clock Signal using XTAL On-Chip Clock Synthesis (OCCS), Rev. 3 Freescale Semiconductor...
Page 114: Register Definitions
Name PLLCR PLLIE1 PLLIE0 LOCIE ZSRC LCKON PLLPD CHPMTRI PLLDB LORTP PLLCOD PLLCID PLLDB PLLSR LOLI1 LOLI0 LOCI LCK1 LCK0 ZSRC RESERVED CLKOSR CLKOSEL Read as 0 Reserved Figure 4-6. OCCS Register Map 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 115: Pll Control Register (Pllcr)
4.6.1.3 Loss of Clock Interrupt Enable (LOCIE)—Bit 11 An optional interrupt can be generated if the oscillator circuit output clock is lost. • 0 = Interrupt disabled • 1 = Interrupt enabled On-Chip Clock Synthesis (OCCS), Rev. 3 Freescale Semiconductor...
Page 116 IPBus clock. ZSRC is automatically set to 001b during STOP_MODE, or if PLLPD is set in order to prevent loss of the clock to the core. For 56F826/827, ZSRC may have the following values. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 117: Pll Divide-By Register (Plldb)
• 10 = Divide by four • 11 = Divide by eight 4.6.2.4 Reserved—Bit 7 This bit is reserved or not implemented. It is read as 0 and cannot be modified by writing. On-Chip Clock Synthesis (OCCS), Rev. 3 Freescale Semiconductor...
Page 118 160MHz, resulting in an FOUT/2 of 80MHz. Before changing the divide-by value, it is recommended the core clock be first switched to the prescaler clock. Note: Upon writing to the PLLDB register, the lock detect circuit is reset. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 119: Pll Status Register (Pllsr)
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 4.6.3.5 Loss of Lock 1 (LCK1)—Bit 6 • 0 = PLL is unlocked (fine) • 1 = PLL is locked (fine) On-Chip Clock Synthesis (OCCS), Rev. 3 Freescale Semiconductor...
Page 120: Clko Select Register (Clkosr)
All other clocks possibly muxed out are for test purposes only. CLKGEN_BASE+$4 Read CLKOSEL Write Reset Figure 4-10. CLKO Select Register (CLKOSR) See Programmer’s Sheet on Appendix page B- 112 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 121: Clock Operation In The Power-Down Modes
• Stop - This mode causes ZCLK and the IPBus_Clock to turn-off. Like the Wait mode, the Stop mode causes all internal clocks to the 56F800 core to shut down. Processing is suspended. The only possible recoveries from the Stop mode are a TOD alarm interrupt, TOD one second interrupt, an external interrupt IRQA/B or a power-on reset.
Page 122: Pll Recommended Range Of Operation
PLL lock time becomes an issue. It is recommended to avoid values of n resulting in the VCO frequency greater than 240MHz or less than 80MHz. Figure 4-13 shows the 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 123: Recommended Design Regions Of Occs Pll Operation
8MHz Fin_pll Figure 4-13. PLL Output Frequency vs. Input Frequency Note: The value of n and the specific coordinates of the Not Possible and Not Recommended areas are yet to be determined. On-Chip Clock Synthesis (OCCS), Rev. 3 Freescale Semiconductor...
Page 124: Pll Lock Time Specification
LCK0 bit is set to one. If, after 64 cycles of FREF there are the same number of FREF clocks as feedback clocks, the LCK1 bit is also set. The LCK bits stay set until: • Clocks fail to match 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 125 LCK1 is reset to zero, because the clocks did not match, LCK0 can stay high. This provides the processor the accuracy of the two clocks with respect to each other. On-Chip Clock Synthesis (OCCS), Rev. 3 Freescale Semiconductor...
Page 126 PLL Frequency Lock Detector Block 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 127: Interrupt Controller (Itcn)
Chapter 5 Interrupt Controller (ITCN) Interrupt Controller (ITCN), Rev. 3 Freescale Semiconductor...
Page 128 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 129: Introduction
The I1 and I0 bits in the 56F826/827 core Status Register (SR) determine the class of the permitted exceptions. • To permit maskable exceptions, I bits should be set to 01. • To disable the maskable exceptions, I bits should be set to 11. Interrupt Controller (ITCN), Rev. 3 Freescale Semiconductor...
Page 130: Interrupt Enable
I1:I0 bits in SR) these are nonmaskable interrupts, such as illegal instruction and COP Timer reset with an even higher priority. For more details, see Table 7-7 in the DSP56800 Family Manual. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 131: Interrupt Programming
Low-level sensitive High-level sensitive Falling-edge sensitive CH0- Enabled? Rising-edge sensitive — Note: To avoid spurious interrupts, it may be necessary to disable IRQx interrupts by clearing the IxL0 bit before modifying IxL1 or IxINV. Interrupt Controller (ITCN), Rev. 3 Freescale Semiconductor...
Page 132: Interrupt Request Signals
• Transmits without exception • Transmit and receive with exception 5.8.2 Serial Peripheral Interface (SPI0) • Receiver full and/or error • Transmitter empty 5.8.3 Serial Peripheral Interface (SPI1) • Receiver full and/or error • Transmitter empty 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 133: Serial Communications Interface (Sci0)
• Conversion complete 5.8.8 Timer Module (TMR A) • Channel three flag • Channel two flag • Channel one flag • Channel zero flag 5.8.9 Time-of-Day Module (TOD) • Alarm interrupt • One second interrupt Interrupt Controller (ITCN), Rev. 3 Freescale Semiconductor...
Page 134: Combined Interrupt Requests For Port A (Gpioa)
5.8.20 Phase Lock Loop Module (PLL) 5.8.21 Low Voltage Detect (LVD) 5.9 Priority Level and Vector Assignments Table 5-2 indicates the vector for each interrupt source. For a selected level, the highest vector has the highest priority. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 135: Itcn Register Summary
$0060 SCI #1 Receiver Error $005E SCI #1 Transmission Ready $005C SCI #1 Transmission Complete Reserved (56F826) — $005A SCI #2 Receiver Full (56F827) Reserved (56F826) — $0058 SCI #2 Receiver Error (56F827) Interrupt Controller (ITCN), Rev. 3 Freescale Semiconductor...
Page 136 Data Flash Interface (56F826) $001A Upper Program Flash Interface AU (56F827) Program Flash Interface (56F826) $0018 Lower Program Flash Interface AL (56F827) Boot Program Flash Interface (56F826) — $0016 Reserved (56F827) $0014 Reserved 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 137: Register Definitions
ITCN_GPR7 Group Priority Register 7 Read/Write Base + $8 ITCN_GPR8 Group Priority Register 8 Read/Write Base + $9 ITCN_GPR9 Group Priority Register 9 Read/Write Base + $A ITCN_GPR10 Group Priority Register 10 Read/Write Interrupt Controller (ITCN), Rev. 3 Freescale Semiconductor...
Page 138: Itcn Register Map Summary
PLR46 PLR45 PLR44 GRP12 PLR51 PLR50 PLR49 PLR48 GRP13 PLR55 PLR54 PLR53 PLR52 GRP14 PLR59 PLR58 PLR57 PLR56 GRP15 PLR63 PLR62 PLR61 PLR60 Read as 0 Reserved Figure 5-3. ITCN Register Map Summary 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 139: Register Definitions (Gpr2-Gpr15)
Write Reserved-826 PLR15 Interface-826 Interface-826 Data Flash Upper Prog. Flash Lower Prog. Flash Interface-827 Interface AU-827 INterface AL-827 Reset Figure 5-7. Group Priority Register 3 (GPR3) See Programmer’s Sheet on Appendix page B-21 Interrupt Controller (ITCN), Rev. 3 Freescale Semiconductor...
Page 140 PLR34 PLR33 PLR32 PLR35 Write Timer A Channel 1 Timer A Channel 0 TOD Alarm TOD One Sec Reset Figure 5-12. Group Priority Register 8 (GPR8) See Programmer’s Sheet on Appendix page B-23 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 141 Read PLR55 PLR52 PLR53 Reserved-826 ADC PLR54 Write SCI 0 Receiver Conversion SCI 0 Receiver Full Error Complete-827 Reset Figure 5-17. Group Priority Register 13 (GPR13) See Programmer’s Sheet on Appendix page B-24 Interrupt Controller (ITCN), Rev. 3 Freescale Semiconductor...
Page 142 See Programmer’s Sheet on Appendix page B-24 ITCN_BASE+$F Read PLR63 PLR62 PLR60 PLR61 Low Voltage Write PLL Loss of Lock SSI w/Exception Detector Reset Figure 5-19. Group Priority Register 15 (GRP15) See Programmer’s Sheet on Appendix page B-24 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 143: Flash Memory Interface (Flash)
Chapter 6 Flash Memory Interface (FLASH) Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 144 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 145: Introduction
• Page erase capability: 256 words per page • Block (mass) erase capability • Access time: 20ns (max) µ • Word (16-bit) program time: 20 s (min) • Page Erase time: 40ms (min) • Mass Erase time: 100ms (min) Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 146: Flash Description
Sense amplifier enable; very useful if Flash is set in standby mode, cutting power requirement Output Enable, tri-state Flash data out bus when OE = 0 Defines program cycle Defines erase cycle Defines mass erase cycle, erase whole block Defines non-volatile store cycle 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 147: Program Flash (Pflash)
Devices described within this section use Flash blocks as non-volatile memory. The Flash block is instantiated within the Program Address Space (PFLASH). PFLASH is connected to core buses via a Program Flash Interface. PFLASH configurations for the devices described here are presented in Table 6-4. Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 148: Program Flash Block Integration
Total Size Row Size #of Rows Page Size # of Pages 512 bits 31.5 words 56F826 31.5 x 16 bits (32 words) 512 bits 63 words 56F827 63 x 16 bits (32 words) 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 149: Data Flash (Dflash)
Table 6-7. Data Flash Information Block Organization Chip Total Size Row Size # of Rows Page Size # of Pages 512 bits 56F826 2 x 16 bits (32 words) 512 bits 56F827 4 x 16 bits (32 words) Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 150: Boot Flash (Bflash) 56F826 Only
This section details Program, Data, and Boot Flash Interface Unit features: • Single port memory compatible with core pipelined program bus structure • Single cycle reads at 40MHz across the automotive temperature range 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 151: Program/Data/Boot Flash Modes
— Reads out of range, trying to access a row past the first two in the Information Block — Read attempted during program — Read attempted during erase — Any of seven internal timer timeouts used during program/erase operations • Intelligent erase and word programming features Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 152: Functional Description Of The Pfiu, Pfiu2, Dfiu And Bfiu
The recommended Flash Programming mode is the Intelligent Word Programming, described in Section 6.10.1. Although the Dumb Word Programming is described in Section 6.10.2, it is not the preferred nor recommended method of programming Flash. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 153: Intelligent Word Programming
The Intelligent Programming feature can program only one word at a time. Multiple words may be programmed by repeating the process, or by switching to the Dumb Word Programming method, subsequently outlined. Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 154: Dumb Word Programming
6. Set the NVSTR bit in the FIU_CNTL register. 7. Delay for t 8. Set the YE bit in the FIU_CNTL register. 9. Delay for T PROG 10. Clear the YE bit in the FIU_CNTL register. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 155: Intelligent Erase Operation
6. Do not attempt to access the Flash again until the BUSY signal clears in the FIU_CNTL register, corresponding to the t interrupt, when it is enabled. 7. Ensure FIU_CNTL and FIU_EE registers are cleared when finished. Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 156: Flash Page Erase Cycle
Tnvs NVSTR NVSTR Tnvh Trcv Terase Figure 6-5. FLASH Page Erase Cycle IFREN IFREN XADR XADR MASI MAS1 YE=SE=OE=0 YE=SE=OE=0 ERASE ERASE Tnvs NVSTR NVSTR Tnvh1 Trcv Figure 6-6. Flash Mass Erase Cycle 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 157: Register Definitions
Interface Units are the same for Program Flash Interface Unit (PFIU). Since the 56F826/827 has 64K of Program Flash, 60K are usable while 4K is reserved, an extra Program Flash Interface Unit (PFIU2) is required to access the second half of Flash. Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 158: Flash Register Summary
TNVH1L Limit Register Read/Write Section 6.11.16 Base + $10 FIU_TRCVL TRCV Limit Register Read/Write Section 6.11.17 Bit fields of each of the 17 registers are summarized in Figure 6-7. Details of each follow. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 159: Flash Register Map Summary
ERASE NVSTR PAGE ADDR DATA CKDIVISOR TERASEL TERASEL TMEL TMEL TNVSL TNVSL TPGSL TPGSL TPROGL TPROGL TNVHL TNVHL TNVH1L TNVH1L TRCVL TRCVL Read as 0 Reserved Figure 6-7. FLASH Register Map Summary Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 160: Ifren Bit Effect
Read Information Block Read Main Memory Block Word Program Program Information Block Program Main Memory Block Page Erase Erase Information Block Erase Main Memory Block Mass Erase Erase Both Blocks Erase Main Memory Block 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 161: Flash Program Enable Register (Fiu_Pe)
Intelligent Programming mode, reflecting the state of the Flash NVSTR pin. 6.11.2 Flash Program Enable Register (FIU_PE) This register is reset upon any system reset. This register cannot be modified while the BUSY bit is asserted. IS[11] is asserted when this occurs. Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 162: Flash Erase Enable Register (Fiu_Ee)
6.11.3 Flash Erase Enable Register (FIU_EE) This register is reset upon any system reset. This register may not be modified while the BUSY bit is asserted. Should this happen, IS[11] is also asserted. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 163 NVSTR. Interrupt Source IS[0] bit is set to indicate an error. This is intended as a double check against accidental erasure. Similarly, set PAGE to be $00 when MAS1 = 1. These checks also apply for the Dumb Erase mode. Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 164: Flash Address Register (Fiu_Addr)
Data bits (D[15:0]) reflect the last value programmed, or the value written to initiate an erase. FIU_ADDR and FIU_DATA are set simultaneously by writing to Flash Memory space. This value can be read at any time. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 165: Flash Interrupt Enable Register (Fiu_Ie)
Under normal operation, only clear bits in FIU_IS can be cleared. The IS source bits can be cleared at any time. This register is reset upon any system reset. FIU_BASE+$6 Read Write Reset Figure 6-14. Flash Interrupt Source Register (FIU_IS) See Programmer’s Sheet on Appendix page B-31 Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 166 This Interrupt Source bit is asserted when there is a t (PROG/ERASE to NVSTR Setup Time) timeout. 6.11.7.11 Interrupt Source (IS[2])—Bit 2 This Interrupt Source bit is asserted when an illegal Flash read/write access is attempted during erase. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 167: Flash Interrupt Pending Register (Fiu_Ip)
6.11.9 Flash Clock Divisor Register (FIU_CKDIVISOR) This register is reset during any system reset. It may only be changed when the BUSY bit is clear. IS[11] is asserted should BUSY bit be cleared. Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 168 This register is reset during any system reset. The register may only be changed when the BUSY bit is clear. IS[11] is asserted should this occur. 6.11.10.1 Reserved—Bits 15–7 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 169 6.11.12 Flash T Limit Register (FIU_TNVSL) This register is reset during any system reset and may only be changed when the BUSY bit is clear. IS[11] is asserted when BUSY bit is clear. Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 170 Figure 6-20. Flash Limit Register (FIU_TPGSL) See Programmer’s Sheet on Appendix page B-37 6.11.13.1 Reserved—Bits 15–12 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 171 Flash. At a 40MHz bus clock, the maximum value of t PROG × (t PROG IPBUS PROG Max = 25ns × 16384 = 409.64µs PROG Reset = 25ns × 1024 = 25.6µs PROG Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 172 This register is reset during any system reset and may only be changed when the BUSY bit is clear. IS[11] is asserted should this occur. FIU_BASE+$F Read TNVH1L Write Reset Flash T Limit Register (FIU_TNVH1L) Figure 6-23. NVH1 See Programmer’s Sheet on Appendix page B-40 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 173: Flash Trcv Limit Register (Fiu_Trcvl)
× (t IPBUS RCVL Max = 25ns × 512 = 12.8µs Reset = 25ns × 64 = 1.6µs The counter controlled by this register is used for both Page and Mass Erase modes. Flash Memory Interface (FLASH), Rev. 3 Freescale Semiconductor...
Page 174: Flash Interface Unit Timeout Registers
BUSY bit is clear. Any attempt to do so will not affect the register contents, and it may cause an error interrupt to be posted if the corresponding enable bit in FIU_IE is set. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 175: External Memory Interface (Emi)
Chapter 7 External Memory Interface (EMI) External Memory Interface (EMI), Rev. 3 Freescale Semiconductor...
Page 176 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 177: Introduction
The names of the 56F826/827 External Memory port pins are as follows: • Address Bus Output (A15–0) • Data Bus (D15–0) • Read Enable (RD) • Write Enable (WR) • Program Memory Select (PS) • Data Memory Select (DS) External Memory Interface (EMI), Rev. 3 Freescale Semiconductor...
Page 178: Register Description
Write Reset Figure 7-2. Bus Control Register (BCR) See Programmer’s Sheet on Appendix page B-22 7.4.1.1 Reserved—Bits 15–10 This bit field is reserved or not implemented. It is read and written using 0. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 179: Programming Wsp[3:0] And Wsx[3:0] Bits For Wait States
T3 period, demonstrated by the dark gray area in Figure 7-3. Figure 7-4 exhibits an example of the bus cycles with wait states. For more information on wait states, see the corresponding chip’s technical data sheet. External Memory Interface (EMI), Rev. 3 Freescale Semiconductor...
Page 180: Bus Operation (Read/Write-Zero Wait States)
T2 Tw T2 T3 T0 T1 T2 Tw T2 Tw T2 Tw T2 Tw CLKO A15–A0 PS, DS PCSn Data In Data Out D15–D0 *827 only Figure 7-4. Bus Operation (Read/Write–Four Wait States) 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 181: State Of Pins In Different Processing States
Debug mode is a special state used to debug and test programming code. This state is detailed in Section 9 of the DSP56800 Family Manual, DSP56800FM The state is not described in the following tables. External Memory Interface (EMI), Rev. 3 Freescale Semiconductor...
Page 182: Programmable Chip-Select (56F827 Only)
7.6 Chip Select Features (56F827 Only) • Reduced system complexity — No external glue logic required for typical systems, if the chip-selects are used. • Eight programmable active-low chip-selects (PCS7 - PCS0) • Control for external boot device 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 183: Programmability
This provides compatibility to the other 56800 Family parts by using PCS0 and PCS1 as PS and DS respectively. All individual chip-selects including PCS0 and PCS1 are programmable through Base Address registers PCSBARn and Option registers PCSORn. External Memory Interface (EMI), Rev. 3 Freescale Semiconductor...
Page 184: Register Definitions
Note: Register Address = Base Address + Address Offset, where the Base Address is defined at chip level and the Address Offset is defined at the module level. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 185: Pcs Registers Summary
PCSOR6 PCS Option Register 6 Read/Write Base + $F PCSOR7 PCS Option Register 7 Read/Write Bit fields of each of the 16 registers are summarized in Figure 7-5. Details of each follow. External Memory Interface (EMI), Rev. 3 Freescale Semiconductor...
Page 186: Pcs Registers Map Summary
7.8.1 PCS Base Address Registers (PCSBAR0, ... ,PCSBAR7) PCS_BASE+$0 Read ADDR ADDR ADDR ADDR ADDR ADDR ADDR BLKSZ Write Reset Figure 7-6. PCS Base Address Register 0 (PCSBAR0) See Programmer’s Sheet on Appendix page B - 74 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 187 See Programmer’s Sheet on Appendix page B - 74 PCS_BASE+$5 Read ADDR ADDR ADDR ADDR ADDR ADDR ADDR BLKSZ Write Reset Figure 7-11. PCS Base Address Register 5 (PCSBAR5) See Programmer’s Sheet on Appendix page B - 74 External Memory Interface (EMI), Rev. 3 Freescale Semiconductor...
Page 188: Pcsbar Encoding Of The Blksz Field
The value of the base address must be an integer multiple of the block size. For example, the base address must be at the block size boundary only. If the base address is not at 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 189: Pcs Option Registers (Pcsor0, Pcsor1,..., Pcsor7)
Figure 7-15. PCS Option Register 1 (PCSOR1) See Programmer’s Sheet on Appendix page B - 75 PCS_BASE+$A Read PDSEN Write Reset Figure 7-16. PCS Option Register 2 (PCSOR2) See Programmer’s Sheet on Appendix page B - 75 External Memory Interface (EMI), Rev. 3 Freescale Semiconductor...
Page 190 Figure 7-21. PCS Option Register 7 (PCSOR7) See Programmer’s Sheet on Appendix page B - 75 7.8.2.0.1 Reserved (PCSORn)—Bits 15-2 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 191: Pcsor Encoding Of Pcs Ps / Ds Functionality
Table 7-8. PCSOR Encoding of PCS PS / DS Functionality PDSEN[1:0] Description Disable DS Only PS Only Both DS and PS Note: The Programmable Chip-Select PCSn can be disabled by setting the PDSEN field to zero (00) of the PCSORn. External Memory Interface (EMI), Rev. 3 Freescale Semiconductor...
Page 192 Register Definitions 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 193: General Purpose Input/Output (Gpio)
Chapter 8 General Purpose Input/Output (GPIO) General Purpose Input/Output (GPIO), Rev. 3 Freescale Semiconductor...
Page 194 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 195: Introduction
8.4 Chip Specific Configurations Dedicated GPIOs are, of course, intended only for use as GPIOs. Shared indicates pins may be alternately used as a GPIO. The programming model is identical for dedicated versus shared GPIO. General Purpose Input/Output (GPIO), Rev. 3 Freescale Semiconductor...
Page 196: Gpio Assignments
Port E Port F Port G 56F826 8 Shared 8 Dedicated 6 Shared 8 Dedicated 8 Shared 8 Shared – 56F827 16 Shared 8 Dedicated 8 Shared 8 Dedicated – 8 Shared 16 Shared 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 197: Block Diagram Showing Gpio Port Connections For 56F826
PE5/A5 PORT E PE4/A4 PE3/A3 PE2/A2 PE1/A1 PE0/A0 PF7/SS PF6/MISO GPIO PF5/MOSI PORT F PF4/SCLK Quad Timer A PF3/TA3 PF2/TA2 PF1/TA1 PF0/TA0 Figure 8-1. Block Diagram Showing GPIO Port Connections for 56F826 General Purpose Input/Output (GPIO), Rev. 3 Freescale Semiconductor...
Page 198: Block Diagram Showing Gpio Port Connections For 56F827
GPIO PF4/SCLK PF3/TA3 PORT F PF2/TA2 PF2/TA1 PF2/TA0 Quad Timer A PG15/D15 PG14/D14 GPIO External Data PORT G PG1/D1 (16 bit) PG0/D0 [15:0] Figure 8-2. Block Diagram Showing GPIO Port Connections for 56F827 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 199: Bit-Slice View Of The Gpio Logic
In any case, if the I/O is set to be an output, the pull-up is disabled. The 56F826/827 GPIO interfaces with the following on-chip devices: • External Address Bus • SCI (56F827 only) • SPI General Purpose Input/Output (GPIO), Rev. 3 Freescale Semiconductor...
Page 200: Gpio Interrupts
GPIO pin is active high. If IPOLR is set to one, the interrupt at the GPIO pin is active low. DATA_WR WRITE_EN ck Qb IPOL ck Qb Figure 8-4. Edge Detector Circuit 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 201: Register Summary
No interrupt is registered. A one indicates an GPIO_IPR Interrupt Pending Register $00000000 interrupt. Interrupt Edge Sensitive A one indicates an edge has been detected. IESR $00000000 Register Table 8-4 illustrates the state of the PAD and pull-up resistor. General Purpose Input/Output (GPIO), Rev. 3 Freescale Semiconductor...
Page 202: Gpio Programming Algorithms
;data input • Vector Setup — P:$0000 ;Cold Boot — START ;Hardware RESET vector — P:START ;Start of program • General Setup — MOVE #$0200,X:BCR ;External memory has 0 states • Port B Setup 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 203 ;Selects Port B pins as outputs • Main Routine — OUTPUT ;Output Loop — MOVE X:data_o,X0 ;Put bits 0-7 of "data_o" on pins PB0-PB7 — MOVE X0,X:PBDR ;Memory to memory move requires 2 moves — OUTPUT General Purpose Input/Output (GPIO), Rev. 3 Freescale Semiconductor...
Page 204: Register Definitions
Please refer to Table 3-11 for the Data Memory Peripheral Address Map. Table 8-5. GPIO Memory Map Device Name Base Address GPIOA_BASE $11A0 GPIOB_BASE $11B0 GPIOC_BASE $11C0 826/827 GPIOD_BASE $11D0 GPIOE_BASE $11E0 GPIOF_BASE $11F0 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 205: Gpio Register Summary
Section 8.8.7 Base + $7 GPIOX_IPR Interrupt Pending Register Read/Write Section 8.8.8 Base + $8 GPIOX_IESR Interrupt Edge-Sensitive Register Read/Write Section 8.8.9 Each GPIO module has nine, 8-bit registers provided in Figure 8-5. General Purpose Input/Output (GPIO), Rev. 3 Freescale Semiconductor...
Page 206: Gpio Pull-Up Enable Register (Pur)
Bits within this read/write register control whether pull-ups are enabled in either Normal or GPIO mode. Pull-ups are automatically disabled for outputs in both modes. • 1 = Pull-ups enabled for inputs by default • 0 = Pull-ups disabled for inputs 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 207: Data Register (Dr)
Figure 8-8. Data Register (DR) See Programmer’s Sheets on Appendix page B-43 GPIO_BASE+$1 Read Write Reset Figure 8-9. Data Register (DR) for Port A and Port G (56F827 Only) See Programmer’s Sheets on Appendix page B-43 General Purpose Input/Output (GPIO), Rev. 3 Freescale Semiconductor...
Page 208: Data Direction Register (Ddr)
• 1 = Normal mode; pin operation is controlled by peripheral • 0 =GPIO mode; pin operation is controlled by GPIO registers GPIO_BASE+$3 Read Write Reset Figure 8-12. Peripheral Enable Register (PER) See Programmer’s Sheets on Appendix page B-45 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 209: Interrupt Assert Register (Iar)
GPIO pin. The interrupts are recorded in the GPIO_IPR. • 1 = Enable the edge detection for external interrupt from the GPIO pin • 0 = Disable the edge detection General Purpose Input/Output (GPIO), Rev. 3 Freescale Semiconductor...
Page 210: Interrupt Polarity Register (Ipolr)
Figure 8-18. Interrupt Polarity Register (IPOLR) See Programmer’s Sheets on Appendix page B-48 GPIO_BASE+$6 Read IPOL Write Reset Figure 8-19. Interrupt Polarity Register (IPOLR) Port A and Port G (56F827 Only) See Programmer’s Sheets on Appendix page B-47 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 211: Gpio Interrupt Pending Register (Gpio_Ipr)
GPIO_IPR is being cleared. Note: For the 56F826 device, write only zeros into this register to clear the GPIO_IPR. On the 56F827 device, write only ones into this register to clear the GPIO_IPR. General Purpose Input/Output (GPIO), Rev. 3 Freescale Semiconductor...
Page 212: Gpio Data Transfers Between I/O Pad And Ipbus
DR value is read by the IPbus. No effect on the pin or Input Read from DR DR value. Output Read from DR DR value is read by the IPbus. Data is seen at the pin. = Don’t Care 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 213: Analog-To-Digital Converter (Adc)
Chapter 9 Analog-to-Digital Converter (ADC) 56F827 Only Analog-to-Digital Converter (ADC), Rev. 3 Freescale Semiconductor...
Page 214 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 215: Introduction
• Operating Voltage 3.3V 1.Once in Loop Mode, the time between each conversion is six ADC Clock cycles (2.4 µs). Samples per second is calculated according to 2.4µs per sample or 416666 samples per second. Analog-to-Digital Converter (ADC), Rev. 3 Freescale Semiconductor...
Page 216: Block Diagram
10 unique single-ended channels, and up to 10 differential channel pairs, or some combination of these. The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or perform the programmed scan sequence repeatedly until manually stopped. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 217: Operating Modes
Channel List Register. A mix and match combination of single-ended and differential configurations may exist. For example: • AN0 and AN3 are differential • AN4 and AN9 are both single-ended Analog-to-Digital Converter (ADC), Rev. 3 Freescale Semiconductor...
Page 218: Low Power Mode
Any write to the result register in the ADC-STOP mode is treated as if the analog core supplied the data, therefore, limit checking and zero crossing and associated interrupts can occur if enabled. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 219: Timing
Because the conversion is a pipeline process, once the last sample has been acquired in the sample and hold circuit, the ADC can not be restarted until the pipeline is emptied. However, the conversion cycle can be aborted by issuing an ADC-STOP command. Analog-to-Digital Converter (ADC), Rev. 3 Freescale Semiconductor...
Page 220: Pin Descriptions
The ADC provides three Output reference voltages between V and V REFHI REFLO • V –Output reference voltage Positive REFP • V –Output reference voltage Middle REFMID • V –Output reference voltage Negative REFN 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 221: Register Definitions
The base address is defined at the core. The address offset is defined at the module level. Please reference Table 3-37. Note: Register Address = Base Address + Address Offset, where the Base Address is defined at Chip level and the Address Offset is defined at the module level. Analog-to-Digital Converter (ADC), Rev. 3 Freescale Semiconductor...
Page 222: Adc Register Summary
0 and a write does nothing. Functions that are not implemented are indicated by a shaded bit. Bit fields of each of the registers are summarized in Figure 9-6. Details of each follow. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 223: Adc Register Map Summary
RSLT1 ADRSLT1 SEXT RSLT2 ADRSLT2 SEXT RSLT3 ADRSLT3 SEXT RSLT4 ADRSLT4 SEXT RSLT5 ADRSLT5 SEXT RSLT6 ADRLST6 SEXT RSLT7 ADRSLT7 SEXT RSLT8 ADRSLT8 SEXT RSLT9 ADRSLT9 SEXT Figure 9-6. ADC Register Map Summary Analog-to-Digital Converter (ADC), Rev. 3 Freescale Semiconductor...
Page 224 HLMT3[ ADHLMT3 HLMT4 ADHLMT4 HLMT5 ADHLMT5 HLMT6 ADHLMT6 HLMT7 ADHLMT7 HLMT8 ADHLMT8 HLMT9 ADHLMT9 OFFSET0 ADOFS0 OFFSET1 ADOFS1 OFFSET2 ADOFS2 OFFSET3[ ADOFS3 OFFSET4 ADOFS4 OFFSET5 ADOFS5 Figure 9-6. ADC Register Map Summary (Continued) 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 225: Adc Control Register 1 (Adcr1)
PDNS status bit gets de asserted, or set to zero. When ADC is powered down, the output reference Voltages VREFP, VREFMID and VREFN are set to low (V ) and ADC data output is driven low. Analog-to-Digital Converter (ADC), Rev. 3 Freescale Semiconductor...
Page 226 ADC Clock. A Start bit reasserted while the ADC is executing a conversion cycle is ignored. The ADC must be idle in order for it to recognize this event. • 0 = No action • 1 = Start command is issued 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 227 This enables the optional interrupt if the current result value is greater then the High Limit register value. The raw result value is compared to the Limit register (HLMT[11:0]) before the offset register value is subtracted. • 0 = Interrupt disabled • 1 = Interrupt enabled Analog-to-Digital Converter (ADC), Rev. 3 Freescale Semiconductor...
Page 228 Reasserted start bits and sync pulses presented during an active sample sequence are not recognized. The ADC must be in its idle state (CIP low) to recognize these events. • 11 = Factory Reserved Use The SMODE is set to Triggered Sequential on Reset. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 229: Adc Control Register 2 (Adcr2)
BASE+$2 Read ZCE7 ZCE6 ZCE5 ZCE4 ZCE3 ZCE2 ZCE1 ZCE0 Write Reset Figure 9-3. ADC Zero Crossing Control Register (ADZCC1) See Programmer’s Sheets on Appendix page B- 53 Analog-to-Digital Converter (ADC), Rev. 3 Freescale Semiconductor...
Page 230: Adc Channel List Registers (Adlst1-Adlst5)
Figure 9-6. ADC Channel List Register 2 (ADLST2) See Programmer’s Sheets on Appendix page B- 55 BASE+$6 Read SAMPLE5 SAMPLE4 Write Reset Figure 9-7. ADC Channel List Register 3 (ADLST3) See Programmer’s Sheets on Appendix page B- 55 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 231: Adc Input Conversion For Sample Bits
Table 9-7. ADC Input Conversion for Sample Bits SAMPLEn[6:0] Single Ended Differential – – – – – – – – – – Others Reserved – even – AN0+, AN0- – AN2+, AN0- – AN4+, AN0- Analog-to-Digital Converter (ADC), Rev. 3 Freescale Semiconductor...
Page 232 • SAMPLE0: AN0+ and AN3- differential • SAMPLE1: AN4 single-ended • SAMPLE2: AN9 single-ended • SAMPLE3: AN8+ and AN1- differential • SAMPLE4: AN2 single-ended • SAMPLE5: AN4+ and AN5- differential • SAMPLE6: AN1 single-ended 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 233: Adc Sample Disable Register (Adsdis)
Reset Figure 9-10. ADC Sample Disable Register (ADSDIS) See Programmer’s Sheets on Appendix page B- 56 9.8.5.1 Reserved—Bits 15–10 This bit field is reserved or not implemented. It cannot be read or modified. Analog-to-Digital Converter (ADC), Rev. 3 Freescale Semiconductor...
Page 234: Adc Status Registers (Adstat1 And Adstat2)
PDN bit has been cleared. The analog portion of the ADC cannot be used until the PDNS bit gets cleared. For example, a new conversion sequence cannot be started until PDNS status bit is deasserted. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 235 This bit is cleared by clearing all asserted bits in the zero crossing status register (ADZCSTAT). • 0 = No ZCI IRQ • 1 = Zero Crossing encountered, IRQ pending if ZCIE is set Analog-to-Digital Converter (ADC), Rev. 3 Freescale Semiconductor...
Page 236 Figure 9-12. ADC Status Register 2 (ADSTAT2) See Programmer’s Sheets on Appendix page B- 58 • 0 = Channel not ready or has been read • 1 = Channel ready to be read 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 237: Adc High And Low Limit Status Registers (Adhlstat And Adllstat)
See Programmer’s Sheets on Appendix page B- 59 BASE+$D Read HLS9 HLS8 HLS7 HLS6 HLS5 HLS4 HLS3 HLS2 HLS1 HLS0 Write Reset Figure 9-14. ADC Limit Status Register (ADHLSTAT) See Programmer’s Sheets on Appendix page B- 59 Analog-to-Digital Converter (ADC), Rev. 3 Freescale Semiconductor...
Page 238: Adc Zero Crossing Status Register (Adzcstat)
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 9.8.8.2 Zero Crossing Status—Bits 9–0 • 0 = Channel n has not crossed offset n value • 1 = Channel n crossed offset n value 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 239: Adc Result Registers (Adrslt0,...,Adrslt9)
PDN bit is set to one. This write operation is treated as if it came from the ADC analog core. Therefore, the limit checking, zero crossing, and the offset registers function Analog-to-Digital Converter (ADC), Rev. 3 Freescale Semiconductor...
Page 240: Result Register Data Manipulation
If the Offset register is programmed with a value of zero, the result register value is unsigned and equals the cyclic converter unsigned result. 9.8.9.3 Reserved—Bits 2–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 241: Low And High Limit Registers (Adllmt0-9
ADC High Limit Register 8—Address: ADC_BASE + $2B ADC High Limit Register 9—Address: ADC_BASE + $2C BASE+$23 Read HLMT Write Reset Figure 9-18. ADC High Limit Status Register (ADHLMTn) See Programmer’s Sheets on Appendix page B- 62 Analog-to-Digital Converter (ADC), Rev. 3 Freescale Semiconductor...
Page 242: Adc Offset Registers (Adofs0-9)
ADC Offset Register 8—Address: ADC_BASE + $35 ADC Offset Register 9—Address: ADC_BASE + $36 BASE+$2D Read OFFSET Write Reset Figure 9-19. ADC Offset Register (ADOFS0-9) See Programmer’s Sheets on Appendix page B- 63 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 243: Serial Communications Interface (Sci)
Chapter 10 Serial Communications Interface (SCI) Serial Communications Interface (SCI), Rev. 3 Freescale Semiconductor...
Page 244 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 245: Introduction
— Transmitter idle — Receiver full — Receiver overrun — Noise error — Framing error — Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection Serial Communications Interface (SCI), Rev. 3 Freescale Semiconductor...
Page 246: Block Diagram
When initializing the SCI, be certain to set the proper peripheral enable bits in the General Purpose Input/Output (GPIO) registers as well as any pull-up enables if the SCI pins are multiplexed with GPIO pins. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 247: Data Frame Format
1.The address bit identifies the frame as an address character. Please see Section 10.4.4.6, Receiver Wake-Up. 2. The user must implement the second stop bit by setting the MSB of the data bits when transmitting and by masking the MSB when receiving. Serial Communications Interface (SCI), Rev. 3 Freescale Semiconductor...
Page 248: Baud Rate Generation
10.4.3.1 Character Length The SCI transmitter accommodates either 8- or 9-bit data characters, determined by the state of the M bit in the SCICR. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 249: Sci Transmitter Block Diagram
Bit (LSB) position of the Transmit Shift register. A Logic 1 STOP bit goes into the Most Significant Bit (MSB) position of the frame. Hardware supports odd or even parity. When parity is enabled, the MSB of the data character is replaced by the PARITY bit. Serial Communications Interface (SCI), Rev. 3 Freescale Semiconductor...
Page 250 The SCI recognizes a break character when a START bit is followed by eight or nine Logic 0 data bits and a Logic 0 where the STOP bit should be. Receiving a break character has these effects on SCI registers: 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 251: Receiver
3. After setting the TE bit, immediately write the first character of the second transmission to the SCIDR. 10.4.4 Receiver Figure 10-4 illustrates the block diagram of the SCI receiver function. Serial Communications Interface (SCI), Rev. 3 Freescale Semiconductor...
Page 252: Sci Receiver Block Diagram
SCIDR. The Receive Data Register Full (RDRF) flag in the SCISR is set, indicating the received character can be read. If the Receive Full Interrupt Enable (RFIE) bit in the SCICR is also set, the RDRF flag generates an RDRF interrupt request. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 253: Receiver Data Sampling
If two of three samples are 0s (not all 0s), Noise Flag (NF) is set. If START bit verification is not successful, the RT clock is reset and a new search for a START bit begins. Serial Communications Interface (SCI), Rev. 3 Freescale Semiconductor...
Page 254: Data Bit Recovery
STOP bit samples. If all three samples are not the same, Noise Flag (NF) is set. If STOP bit detecting fails, Framing Error Flag (FE) is set. Table 10-6. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 255: Slow Data
The maximum percentage difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: For a 9-bit (all 0s) data character, data sampling of the STOP bit takes the receiver: Serial Communications Interface (SCI), Rev. 3 Freescale Semiconductor...
Page 256: Fast Data
10-bit × 16 RT cycles = 160 RT cycles The maximum percentage difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: 154 -160 × 3.90% --------------------- 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 257 • Address Mark Wake-Up (WAKE = 1)—In this wake-up method, a Logic 1 in the MSB position of a frame clears the RWU bit, awakening the SCI. The Logic 1 in the MSB position marks a frame as an address frame containing addressing information. The address frame Serial Communications Interface (SCI), Rev. 3 Freescale Semiconductor...
Page 258: Special Operating Modes
Setting the TE bit in the SCICR enables the transmitter, configuring TXD as the output for transmitted data. Clearing the TE bit disables the transmitter, configuring TXD as the input for received data. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 259: Loop Operation
Clearing the Transmitter Enable (TE) or Receiver Enable (RE) bits in the SCICR reduces power consumption in Run mode. SCI registers are still accessible when TE or RE bits are cleared, but clocks to the SCI module are disabled. Serial Communications Interface (SCI), Rev. 3 Freescale Semiconductor...
Page 260: Sci Memory Map
10-10. A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 261: Register Descriptions
The count in this register determines the baud rate of the SCI. The formula for calculating baud rate is: SCI Baud Rate = IPBus Clock 16 × SBR Section 10.4.2 for more details and examples. Serial Communications Interface (SCI), Rev. 3 Freescale Semiconductor...
Page 262: Sci Control Register (Scicr)
When LOOP = 1, the RSRC bit determines the internal feedback path for the receiver. See Section 10.5.1 Section 10.5.2 for more details. • 0 = Receiver input internally connected to transmitter output • 1 = Receiver input connected to TXD pin 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 263 With even parity, an even number of ones, clears the PARITY bit, while an odd number of ones, sets the PARITY bit. However, with odd parity, an odd number of ones, clears the PARITY bit, while an even number of ones, sets the PARITY bit. Serial Communications Interface (SCI), Rev. 3 Freescale Semiconductor...
Page 264 The TE bit can be used to queue an idle preamble. • 0 = Transmitter disabled • 1 = Transmitter enabled 10.6.2.14 Receiver Enable (RE)—Bit 2 This bit enables the SCI Receiver. • 0 = Receiver disabled • 1 = Receiver enabled 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 265: Sci Status Register (Scisr)
This bit is set when the TDRE flag is set and no data, preamble, or break character is being transmitted. When TIDLE is set, the TXD pin becomes idle (Logic 1). Clear TIDLE by reading the SCISR, then write to the SCIDR. Serial Communications Interface (SCI), Rev. 3 Freescale Semiconductor...
Page 266 This bit is set when the SCI detects noise on the receiver input. The NF bit is set during the same cycle as the RDRF flag, but it is not set in the case of an overrun. Clear NF by reading the SCISR, then write the SCISR with any value. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 267: Sci Data Register (Scidr)
10.6.4 SCI Data Register (SCIDR) The SCIDR can be read and modified at any time. Reading accesses the SCI Receive Data register. Writing to the register accesses the SCI Transmit Data register. Serial Communications Interface (SCI), Rev. 3 Freescale Semiconductor...
Page 268: Clocks
Any system reset completely resets the SCI. 10.9 Interrupts Table 10-10. SCI Interrupt Sources Interrupt Source Flag Local Enable Description TDRE TEIE Transmit Empty Transmitter TIDLE TIIE Transmit Idle RDRF RFIE Receive Full Receiver REIE Receive Error 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 269: Transmitter Empty Interrupt
The interrupt service routine should read the SCISR to determine which of the error flags was set. The error flag is cleared by writing anything to the SCISR. Then the appropriate action should be taken by the software to handle the error condition. Serial Communications Interface (SCI), Rev. 3 Freescale Semiconductor...
Page 270 Interrupts 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 271: Serial Peripheral Interface (Spi)
Chapter 11 Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI), Rev. 3 Freescale Semiconductor...
Page 272 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 273: Introduction
— SPI Transmitter Empty (SPTE) • Mode Fault Error flag interrupt capability Note: Throughout this chapter, there are references to the SPI module clock. The SPI module clock is the IPBus clock. Serial Peripheral Interface (SPI), Rev. 3 Freescale Semiconductor...
Page 274: Block Diagram
SCLK 1 Select Clock Logic SS 0 SS 1 SPR1 SPR0 SPMSTR CPHA CPOL MODFEN TRANSMITTER INTERRUPT REQUEST ERRIE SPTIE CONTROL RECEIVER/ERROR SPRIE INTERRUPT REQUEST SPRF SPTE OVRF MODF Figure 11-1. SPI Block Diagram 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 275: Operating Modes
Slave Select (SS) bit of the master 16-bit controller held high is only necessary if MODFEN = 1. Tying the Slave 16-bit controller SS bit to ground should only be executed if CPHA = 1. Serial Peripheral Interface (SPI), Rev. 3 Freescale Semiconductor...
Page 276: Slave Mode
MISO pin. The slave can load its Shift register with new data for the next transmission by writing to its SPDTR. The slave must write to its SPDTR at least one bus cycle before the master 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 277: Pin Descriptions
SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin. The slave SPI simultaneously receives data from its MOSI pin and transmits data on its MISO pin. Serial Peripheral Interface (SPI), Rev. 3 Freescale Semiconductor...
Page 278: Serial Clock (Sclk)
SPI Configuration State of SS Logic Not Enabled SS ignored by SPI Slave Input-only to SPI Master without MODF SS ignored by SPI Master with MODF Input-only to SPI x = Don’t care 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 279: Transmission Formats
Note: Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing the SPI Enable (SPE) bit. Serial Peripheral Interface (SPI), Rev. 3 Freescale Semiconductor...
Page 280: Transmission Format When Cpha = 0
BIT 3 BIT 2 BIT 1 (from Master) MISO BIT 14 BIT 13 BIT 3 BIT 2 BIT 1 (from Slave) SS (to Slave) CAPTURE STROBE Figure 11-3. Transmission Format (CPHA = 0) 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 281: Transmission Format When Cpha = 1
The SS pin can remain low between transmissions. This format may be preferable in systems having only one master and slave driving the MISO data line. Note: Figure 11-5 assumes 16-bit data lengths and the MSB shifted out first. Serial Peripheral Interface (SPI), Rev. 3 Freescale Semiconductor...
Page 282: Transmission Initiation Latency
DIV4, eight bus cycles for DIV8, and so on up to a maximum of 256 cycles for DIV256. Note: Figure 11-6 assumes 16-bit data lengths and the MSB shifted out first. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 283: Transmission Data
Figure 11-7 illustrates the timing associated with doing back-to-back transmissions with the SPI (SCLK has CPHA: CPOL = 1:0). Note: Figure 11-7 assumes 16-bit data lengths and the MSB shifted out first. Serial Peripheral Interface (SPI), Rev. 3 Freescale Semiconductor...
Page 284: Sprf/Spte Interrupt Timing
Also, if no new data is written to the data buffer, the last value contained in the Shift register is the next data to be transmitted. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 285: Error Conditions
To prevent this loss, either enable the OVRF interrupt or take another read of the SPSCR following the read of the SPDRR. This ensures the OVRF was not set before the SPRF was cleared and future transmissions can set the SPRF bit. Serial Peripheral Interface (SPI), Rev. 3 Freescale Semiconductor...
Page 286: Missed Read Of Overflow Condition
WITH SPRF BIT SET AND OVRF BIT CLEAR. SPDRR CLEARING SPRF BIT. DATA 3 SETS OVRF BIT. DATA 3 IS LOST. 16-BIT CONTROLLER READS SPSCR AGAIN TO CHECK OVRF BIT. Figure 11-9. Clearing SPRF When OVRF Interrupt Is Not Enabled 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 287: Mode Fault Error
MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then later unselected with no transmission occurring. Therefore, MODF does not occur since a transmission was never begun. Serial Peripheral Interface (SPI), Rev. 3 Freescale Semiconductor...
Page 288: Register Definitions
SPI registers in ascending address, including their acronyms and address of each register. The read/write registers should be accessed only with word accesses. Accesses other than word lengths result in undefined results. Figure 11-10 portrays a map summary of the registers. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 289: Spi Status And Control Register (Spscr)
• Selects master SPI baud rate • Determines data shift order • Enables SPI module interrupt requests • Configures SPI module as master or slave • Selects serial clock polarity and phase • Indicates the SPI status Serial Peripheral Interface (SPI), Rev. 3 Freescale Semiconductor...
Page 290 This read/write bit enables the MODF, if MODFEN is also set, and OVRF bits to generate inter- rupt requests. • 0 = MODF and OVRF cannot generate interrupt requests • 1 = MODF and OVRF can generate interrupt requests 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 291 For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set. It does not affect any other part of SPI operation. Serial Peripheral Interface (SPI), Rev. 3 Freescale Semiconductor...
Page 292: Spi Master Baud Rate Selection
11.8.1.13 Clock Phase (CPHA)—Bit 2 This read/write bit controls the timing relationship between the serial clock and SPI data. Please Figure 11-3 Figure 11-5. To transmit data between SPI modules, the SPI modules must 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 293: Spi Data Size Register (Spdsr)
These bits are reserved or not implemented. They are read as 0 and cannot be modified by writing. 11.8.2.2 Data Size ( DS)—Bits 3-0 Please see Table 11-4 for detailed transmission data. Serial Peripheral Interface (SPI), Rev. 3 Freescale Semiconductor...
Page 294: Spi Data Receive Register (Spdrr)
If new data is not written while in the Master mode, a new transaction will not be initiated until this register is written. When in Slave mode, the old data will be re- transmitted. All data should be written with the LSB at bit zero. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 295: Resets
By not resetting the SPRF, OVRF, and MODF flags, it is possible to service the interrupts after the SPI has been disabled. Disable SPI by writing zero to the SPE bit. SPI can also be disabled by a Mode Fault occurring in a SPI configured as a master. Serial Peripheral Interface (SPI), Rev. 3 Freescale Semiconductor...
Page 296: Interrupts
ERRIE bit to generate receiver/error 16-bit (Mode Fault) MODFEN = 1) controller interrupt requests. SPTE SPI TRANSMITTER SPTIE INTERRUPT REQUEST SPRIE SPRF SPI RECEIVER/ERROR INTERRUPT REQUEST ERRIE MODF OVRF Figure 11-15. SPI Interrupt Request Generation 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 297: Synchronous Serial Interface (Ssi)
Chapter 12 Synchronous Serial Interface (SSI) Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 298 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 299: Introduction
• Programmable word length from 8,10, 12, or 16 bits • Program options for frame sync and clock generation • SSI power-down feature • Completely separate clock and frame sync selections for the receive and transmit sections Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 300: Ssi Architecture
The SSI block diagram consists of three control registers. The control registers set up the port, one status/control register, separate transmit and receive circuits FIFO registers, and separate serial clock and frame sync generation for the transmit and receive sections. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 301: Ssi Block Diagram
Slot Register and State RX Sync Transmit Machine SRFS Generator Data Register TXFIFO Transmit TXSR STXD Shift Register RXFIFO Receive Data Register RXSR Receive SRXD Shift Register Figure 12-2. SSI Block Diagram Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 302: Ssi Clocking
Otherwise the clock enable signals, SSI_TX_CLK_OEN or SSI_RX_CLK_OEN are disabled. A programmable frame rate divider and a word length divider are used for frame rate sync signal generation. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 303: Ssi Transmit Clock Generator Block Diagram
Transmit Control Register (SCRTX). The receive section contains an equivalent circuit for the frame sync generator. DC[4:0] Word Clock STFS Frame Frame Rate Sync Tx Frame Sync Out Control Tx Frame Sync In Figure 12-5. SSI Transmit Frame Sync Generator Block Diagram Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 304: Programming Model
— Standard read/write bit. Other than a hardware reset, only software can change the bit’s value. • Provides the reset value of the bit. Possible values: — 0 = Will reset to a Logic 0 — 1 = Will reset to a Logic 1 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 305: Ssi Register Map Summary
TFSL TEFS TSHFD TSCKP STXCR SRXCR RSV[32:16] SRXCR DUMMY REGISTER, WRITTEN DURING INACTIVE TIME SLOTS (NETWORK MODE) STSR RFCNT TFCNT SFCSR RFWM TFWM Read as 0 Reserved Figure 12-3. SSI Register Map Summary Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 306: Ssi Transmit Register (Stx)
When a gated clock is used, data is shifted out to the SSI_TXD_OUT pin by the selected internal/external gated clock. The two Word Length (WL) control bits in the STXCR determine the number of 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 307: Transmit Data Path (Tshfd=0)
Figure 12-5. Transmit Data Path (TSHFD=0) 16 bits TXSR SSI_TXD_out 10 bits 12 bits 8 bits Figure 12-6. Transmit Data Path (TSHFD=1) 1.This is described as SSI transmit and receive control registers. Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 308: Ssi Receive Data Register (Srx)
Data is transferred to the SSI Receive (data) SRX register. If the receive buffer is enabled after 8, 10, 12, or 16 bits have been shifted in, data may be received by 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 309: Ssi Control/Status Register 1 (Scsr)
SSI to interrogate the status and serial input flags of the SSI. The control and status bits are described in the following paragraphs. Note: SSI status flag is updated when SSI is enabled. Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 310: Ssi Control/Status Register 1 (Scsr1)
SSI RFF bit in the SCSR is set, only if receive FIFO is enabled (RFEN = 1). Otherwise, if RFEN = 0, a DMA request is generated when the RDR bit is set. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 311 The SSI Receive Data Ready (RDR) flag bit is set when receive data register SRX or receive FIFO is loaded with a new value. RDR is cleared when the CPU reads the SRX register. If receive FIFO is enabled, RDR is cleared when receive FIFO is empty. Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 312 When a TUE occurs, the previously sent data is retransmitted. A transmit time slot in the normal mode occurs when the frame synchronization is asserted. In network mode, each time slot requires data transmission and is, therefore, a transmit time slot (TE = 1). 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 313 FIFO enabled and when the data level in the transmit FIFO falls below the selected TFWM threshold. When set, the TFE bit notifies data can be written to the transmit FIFO register. Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 314: Ssi Receive Control Register 2 (Scr2)
Reading the SRX register clears the RDR bit, thus clearing the pending interrupt. Two Receive Data Interrupts with separate interrupt vectors are available: 1. Receive data with exception status 2. Receive data without exception status Table 12-12 illustrates the conditions of the generated interrupts. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 315: Ssi Receive Data Interrupts
SRX register. However, if the RE bit is re-enabled during a time slot before the second-to-last bit, then the data will be received. Clearing this bit while clearing SSI Enable (SSIEN) is recommended. Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 316 RXSR. Conditionally, if the RXDIR bit is set, the clock is generated internally and it is output to the SSI_RCK_OUT pin, but only if it is not configured as GPIO. When the RXDIR bit is cleared, the clock source is external. The internal clock generator is disconnected from the 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 317: Frame Sync And Clock Pin Configuration
The codec device labels the MSB as bit zero, whereas the SSI labels the LSB as bit zero. Therefore, when using a standard codec, the SSI MSB, or codec bit zero, is shifted out first and the TSHFD bit should be cleared. Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 318 The TEFS bit set, the frame sync is initiated one bit before the data is transmitted or received. The frame sync is disabled after one bit-for-bit length frame sync and after one word-for-word length frame sync. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 319: Ssi Transmit And Receive Control Registers
Its use allows a 128kHz master clock to be generated for MC1440x series codecs. The maximum internally generated bit clock frequency /(4 × 8 × 256). is F /4, and the minimum internally generated bit clock frequency is F Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 320: Ssi Data Word Lengths
A divide ratio from 1 to 256 (PM = $00 to $FF) can be selected. The bit clock output is available at the clock SCK. The bit clock on the SSI can be calculated from the system clock value using the equation in Figure 12-17. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 321: Ssi Bit Clock Equation
2.048MHz and 1.536 MHz rates, and a 24.704MHz clock frequency can be used to generate the standard 1.544 MHz rate. Table 12-2 illustrates PM values available to generate different bit clocks. Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 322: Ssi Time Slot Register (Stsr)
For the purposes of timing, the Time Slot register is a write-only register behaving like an alternate Transmit Data register. Its exception is instead of transmitting data, the SSI_TXD_oen_b signal is disabled. Using this register is important to avoid overflow/underflow during inactive time slots. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 323: Ssi Fifo Control/Status Register (Sfcsr)
7 Data Words in Receive FIFO 1000 8 Data Words in Receive FIFO 12.4.11.2 Transmit FIFO Counter (TFCNT)—Bits 11-8 These status bits illustrate the number of data words in the Transmit FIFO. Please refer to Table 12-4. Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 324: Data Fifo Transmit
RFF set when more than or equal to seven data words have 0111 7,8 Data Words been written to the Receive FIFO RFF set when more than or equal to eight data words have 1000 8 Data Words been written to the Receive FIFO 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 325: Transmit Fifo Empty Flag
<=1 Data Transmit FIFO 1000 TFE set when there are eight empty slots in Transmit FIFO = 0 Data Table 12-7. TFWM Settings Transmit Number of Data in TXFIFO FIFO WaterMark (TFWM) Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 326: Ssi Option Register (Sor)
SSI. On the 56F826, these are not used and should be left at 0 × 00 default value. 12.4.12.5 Frame Syn Reset (SYNRST)—Bit 0 The Frame Sync Reset (SYNRST) bit automatically resets the accumulation of data in receive FIFO (RXFIFO) on frame synchronization. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 327: Ssi Data And Control Pins
GPIO pins, if desired. Note: This GPIO is a separate module itself, multiplexing and connecting the SSI data and control signals to the six dedicated I/O pins for SSI. Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 328: Asynchronous (Syn=0) Ssi Configurations-Continuous Clock
STFS SRCK SRFS SSI Continuous Clock (RXDIR=1, TXDIR=0, RFDIR=1, TFDIR=0, SYN=0) SSI=GPIO STXD SRXD STCK STFS SRCK SRFS SSI Continuos Clock (RXDIR=0, TXDIR=1, RFDIR=0, TFDIR=1, SYN=0) Figure 12-21. Asynchronous (SYN=0) SSI Configurations-Continuous Clock 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 329: Synchronous Ssi Configuration-Continuous And Gated Clock
SSI (RXDIR=1,TXDIR=0, RFDIR=X, TFDIR=0, SYN=1) SSI+GPIO STXD SRXD STCK SSI Continuous Gated Clock (RXDIR=1, TXDIR=1, SYN=1) SSI=GPIO STXD SRXD STCK SSI Continuous Gated Clock (RXDIR=0, TXDIR=1, SYN=0) Figure 12-22. Synchronous SSI Configuration-Continuous and Gated Clock Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 330: Configuration Of The Ssi Pins
The frame sync is used by the receiver to synchronize the transfer of data. The frame sync signal can be one bit or one word in length and can occur one bit before the transfer of data or right at the transfer of data. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 331: Operating Modes
The SSI has three basic operating modes, with the option of asynchronous or synchronous protocol, as follows: 1. Normal mode — Asynchronous protocol — Synchronous protocol 2. Network mode — Asynchronous protocol Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 332: Ssi Operating Modes
DC bits in either the SRXCR or STXCR register, depending on whether data is being transferred or received. The number of words transferred per frame depends on the mode of the SSI. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 333: Normal Mode
The SSI_TXD_OEN signal is disabled except during the data transmission period. For a continuous clock, the optional frame sync output and clock outputs are not inactive, even if both receiver and transmitter are disabled. Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 334: Normal Mode Timing-Continuous Clock
Continuous Data SSI_TXD_out SSI_RXD Figure 12-24. Normal Mode Timing—Continuous Clock Figure 12-25 illustrates a similar case for a gated clock. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 335: Network Mode
The exception to this is when data is always being shifted into the RXSR and transferred to the SRX register. The core reads the SRX register and either uses the data or discards it. Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 336 However, the Receive Enable only takes place during that time slot if RE is enabled before the second-to-last bit of the word. If the RE bit is cleared, the receiver is disabled immediately. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 337 SCR2. The transmitter and receiver timing for an 8-bit word with a continuous clock, FIFO disabled, and three words per frame synchronization in the network mode is shown in Figure 12-26. Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 338: Gated Clock Operation
Once the transmission of data has completed, the clock enable pin is disabled. Gated clocks are allowed for both the transmit and receive sections with either an internal or external clock and in normal mode. Gated clocks are not allowed in Network mode. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 339: Reset And Initialization Procedure
To ensure proper operation of the SSI, use the power-on or SSI reset before changing any of the following control bits listed in Table 12-9. Note: These control bits should not be changed during SSI operation. Synchronous Serial Interface (SSI), Rev. 3 Freescale Semiconductor...
Page 340: Ssi Control Bits Requiring Reset Before Change
Reset and Initialization Procedure Table 12-9. SSI Control Bits Requiring Reset Before Change Control Register SRXCR STXCR SCR2 TEFS TFSI TFSL TSCKP SCSR REFS RFSI RFSL RSCKP RSHFD 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 341: Quad Timer Module (Tmr)
Chapter 12 Quad Timer Module (TMR) Quad Timer Module (TMR), Rev. 3 Freescale Semiconductor...
Page 342 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 343: Introduction
OFLAG signal can be set, cleared, or toggled. At match time, an interrupt is generated if enabled. Within a time module there is a set of four counter/timers allowing the input pins to be apportioned. Quad Timer Module (TMR), Rev. 3 Freescale Semiconductor...
Page 344: 56F826 Counter/Timer Block Diagram
Introduction OUTPUT PRESCALER OFLAG inputs other cntrs COUNTER COMPARATOR COMPARATOR CONTROL CAPTURE HOLD CMP1 CMP2 LOAD STATUS & CONTROL DATA BUS Figure 12-1. 56F826 Counter/Timer Block Diagram Figure 12-2. 56F827 Counter/Timer Block Diagram 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 345: Features
• Quad Timer Hold (HOLD) register • Quad Timer Capture (CAP) register • Quad Timer Compare (CMP1 and CMP2) registers • Quad Timer Status and Control Register (SCR) • Quad Timer Control (CTRL) register Quad Timer Module (TMR), Rev. 3 Freescale Semiconductor...
Page 346: Functional Description
OFLAG output signal may be output to an external pin shared with an external input signal. The OFLAG output signal enables each counter to generate square waves, PWM, or pulse stream outputs. The polarity of the OFLAG output signal is selectable. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 347: Master Signal
This mode is used to time the duration of external events. If the selected input is inverted by setting the IPS bit, then the counter will count while the selected secondary input is low. Quad Timer Module (TMR), Rev. 3 Freescale Semiconductor...
Page 348: Quad Count Mode
This is a sub mode of triggered event count mode; the count mode field is set to 110 while: • Count length (LENGTH) is set • The OFLAG output mode is set to 101 • ONCE bit of the Control Register (CTRL) is set to 1 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 349: Cascade Count Mode
The number of output pulses is equal to the compare value minus the initialization value. This mode is useful for driving step motor systems. Quad Timer Module (TMR), Rev. 3 Freescale Semiconductor...
Page 350: Fixed-Frequency Pwm Mode
In this variable frequency PWM mode, the CMP2 value defines the desired pulse width of the on-time, and the CMP1 register defines the off-time. The variable frequency PWM mode is defined for positive counting only. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 351: Capture Register Use
Load Register Read/Write Section 12.7.6 Base + $4 HOLD Hold Register Read/Write Section 12.7.7 Base + $5 CNTR Counter Register Read/Write Section 12.7.8 Base + $6 CTRL Control Register Read/Write Section 12.7.1 Quad Timer Module (TMR), Rev. 3 Freescale Semiconductor...
Page 352: Tmr Register Map Summary
CAPTURE TCF TCFIE TOF TOFIE IEFIE MSTR EEOF MODE FORCE CMPLD1 COMPARATOR LOAD 1 CMPLD2 COMPARATOR LOAD 2 COMSCR TCF2 TCF1 TCF2EN TC1EN Read a 0 Reserved Figure 12-1. TMR Register Map Summary 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 353: Tmr Control Registers (Ctrl)
1.Rising Edges counted only when IPS = 0. Falling edges counted when IPS = 1. 2.Rising Edges counted only when IPS = 0. Falling edges counted when IPS = 1. 3.Primary Count Source must be set to one of the counter outputs. Quad Timer Module (TMR), Rev. 3 Freescale Semiconductor...
Page 354 CMP1 value. If counting down, successful compare occurs when the counter reaches a CMP2 value. When the compare occurs the timer is stopped by changing the timer’s Count mode to Stop Mode (CM=0). 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 355 For example, when Output mode is $4, the counter counts until CMP1 value is reached, reinitializes, then counts until CMP2 value is reached, reinitializes, then counts until CMP1 value is reached, etc. Quad Timer Module (TMR), Rev. 3 Freescale Semiconductor...
Page 356: Tmr Status And Control Registers (Scr)
The two Capture Mode (CM) bits must be set to a non-zero value before this flag can be set. The CM field of the SCR must be set to 110 (binary) in order to have the timer module set the IEF flag. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 357: Capture Register Operation
When set, this bit enables the compare function’s output to be broadcast to the other counters/ timers in the module. This signal then can be used to reinitialize the other counters and/or force their OFLAG signal outputs. Quad Timer Module (TMR), Rev. 3 Freescale Semiconductor...
Page 358: Tmr Compare Register 1 (Cmp1)
COMPARISON VALUE Write Reset Figure 12-4. TMR Compare Register 1 (CMP1) See Programmer’s Sheet on Appendix page B - 90 This read/write register stores the value used for comparison with the counter value. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 359: Tmr Compare Register 2 (Cmp2)
Read LOAD VALUE [15:0] Write Reset Figure 12-7. TMR Load Register (LOAD) See Programmer’s Sheet on Appendix page B - 93 This read/write register stores the value used to initialize the counter. Quad Timer Module (TMR), Rev. 3 Freescale Semiconductor...
Page 360: Tmr Hold Register (Hold)
TMRA3_CMPLD1 (Timer A, Channel 3 CMPLD1)—Address: TMRA_BASE + $38 – 56F827 Only BASE+$8,18,28,38 Read COMPARATOR LOAD 1 Write Reset Figure 12-10. TMR Comparator Load 1 (CMPLD1) See Programmer’s Sheet on Appendix page B - 96 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 361: Tmr Comparator Load Register 2 (Cmpld2)-56F827 Only
An interrupt is issued when both this bit and the TCF2 bit are set. 12.7.11.3 Timer Compare One Interrupt Enable (TCF1EN)—Bit 6 An interrupt is issued when both this bit and the TCF1 bit are set. Quad Timer Module (TMR), Rev. 3 Freescale Semiconductor...
Page 362: Timer Group A Functionality
Individual timers often use their own I/O pin. However, timers may use any other available pin within their group as an input. The timers are limited to their own I/O pin for use as an output pin. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 363: Timer Group A
Time inputs are sampled at the peripheral clock rate. There is a delay of one peripheral clock period before the input can affect the behavior of a counter. This is typical of synchronous counters systems. A gated counter is the only exception. Quad Timer Module (TMR), Rev. 3 Freescale Semiconductor...
Page 364 Timer Group A Functionality 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 365: Time-Of-Day (Tod)
Chapter 13 Time-of-Day (TOD) Time-of-Day (TOD), Rev. 3 Freescale Semiconductor...
Page 366 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 367: Introduction
• Works with crystal frequency of 2 – 4MHz • Capable to generate interrupt, pulling the part out of Sleep mode • Capable to track time up to 179.5 years • Can be configured to generate an alarm at a designated time Time-of-Day (TOD), Rev. 3 Freescale Semiconductor...
Page 368: Counter Operation Block Diagram
TOD input clock (frequency range from 0~65536 Hz) if TODEN = 1. This clock pulse will be used to clock the next counter, SECONDS counter, in the chain. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 369: Time Registers
13.5.1 Stop Mode During Stop mode the TOD module will continue to keep track of the current time. The TOD alarms will still activate and can wake the processor up for TOD related processing. Time-of-Day (TOD), Rev. 3 Freescale Semiconductor...
Page 370: Tod Alarms
For the 56F826, The TODAL bit is cleared by writing 0 to it while it contains a one. For the 56F827, the TODAL bit is cleared by writing 1 to it. The interrupt will not be taken unless it is also enabled in the interrupt controller module. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 371: One-Second Interrupt Flag And Outputs
Hours Alarm Register 0-23 Always Base + 8 TODDAY Days Counter 0-65535 TODEN=0 Base + 9 TODDAL Days Alarm 0-65535 Always 13.7 Register Definitions Table 13-2. TOD Memory Map Device Peripheral Address 826/827 TOD_BASE $10C0 Time-of-Day (TOD), Rev. 3 Freescale Semiconductor...
Page 372: Tod Register Summary
Base + $8 TODDAY Days Counter Register Read/Write Section 13.7.9 Base + $9 TODDAL Days Alarm Register Read/Write Section 13.7.10 Bits of the 10 registers are summarized in Figure 13-2. Details of each follow. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 373: Tod Control Status (Todcs)
For the 56F826, this bit is cleared by writing 0 to the bit position. For the 56F827, the TODSIO bit is cleared by writing 0 to it. This bit must be cleared before exiting the Interrupt Service Routine (ISR). Time-of-Day (TOD), Rev. 3 Freescale Semiconductor...
Page 374 • 1 = Seconds alarm interrupt, requiring match of days alarm register to days counter, is enabled 13.7.1.9 TOD Seconds Interrupt Enable (TODSEN)—Bit 3 • 0 = Disables TOD seconds interrupt • 1 = Enables TOD seconds interrupt 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 375: Tod Clock Scaler (Todcsl)
The value of the counter can be read through corresponding seconds latch, but it cannot be modified. When TODEN is cleared, TOD counting is disabled, and this counter can be modified. When TODEN is set to one again, the counting resumes from the new set time. Time-of-Day (TOD), Rev. 3 Freescale Semiconductor...
Page 376: Tod Seconds Alarm Register (Todsal)
When TODEN is set to one again, the counting resumes from the new set time. BASE + $4 Read TODMIN Write Reset Figure 13-7. TOD Minutes Register (TODMIN) See Programmer’s Sheet on Appendix page B-103 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 377: Tod Minutes Alarm Register (Todmal)
(TODAEN) bit are both set and all other enabled alarm registers also match the current time. BASE + $7 Read TODHAL Write Reset Figure 13-10. TOD Hours Alarm Register (TODHAL) See Programmer’s Sheet on Appendix page B-106 Time-of-Day (TOD), Rev. 3 Freescale Semiconductor...
Page 378: Tod Days Counter (Todday)
(TODAEN) bit are both set and all other enabled alarm registers also match the current time. BASE + $9 Read TODDAL Write Reset Figure 13-12. TOD Days Alarm Register (TODDAL) See Programmer’s Sheet on Appendix page B-108 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 379: Reset, Low Voltage, Stop And Wait Operations
Chapter 15 Reset, Low Voltage, Stop and Wait Operations Reset, Low Voltage, Stop and Wait Operations, Rev. 3 Freescale Semiconductor...
Page 380 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 381: Introduction
Pulse Stretcher 56F826/827 External RESET IN Hardware RESET (Active Low) Delay delay output switches high on T2 only ires Power-On Reset Pulse Stretcher System Reset Figure 15-1. Sources of RESET Reset, Low Voltage, Stop and Wait Operations, Rev. 3 Freescale Semiconductor...
Page 382: Power-On Reset And Low Voltage Interrupt
High speed operation is not guaranteed until both the 2.7V and 2.2V interrupt sources are inactive. Please see the SYS_STS register, Section 15-9. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 383: External Reset
Some internal portions of the chip may be synchronously reset. The internal waveform shaper ensures the internal reset remains low long enough for all portions of the chip to achieve their reset value. Reset, Low Voltage, Stop and Wait Operations, Rev. 3 Freescale Semiconductor...
Page 384: Computer Operating Properly (Cop) Module
Software must periodically service the COP module in order to clear the counter and prevent a reset. 32 Clock Cycles Low-V Interrupt Interrupt cleared by user software here Grayed levels show outputs from analog circuitry. Figure 15-3. POR Vs. Low-Voltage Interrupts 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 385: Cop Functional Description
The COP module can run or be disabled in Stop mode. When the COP Stop Enable (CSEN) bit in COPCTL is set, the COP counter will run in Stop mode. However, when the CSEN bit is cleared, the COP counter will be disabled in Stop mode. Reset, Low Voltage, Stop and Wait Operations, Rev. 3 Freescale Semiconductor...
Page 386: Register Definitions
LVIE27 LVIE22 AP_B SYS_STS COPR EXTR POR LVIS27 LVIS22 MSH_ID LSH_ID Both MSH and LSH register values are hard coded and cannot be reset. Read as 0 Reserved Figure 15-4. COP/SIM Registers Map Summary 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 387: Cop Control Register (Copctl)
COP Timeout (COPTO) register. Once set, this bit can only be cleared by system reset. • 0 = COPCTL, COPTO may be modified • 1 = COPCTL, COPTO are read-only Reset, Low Voltage, Stop and Wait Operations, Rev. 3 Freescale Semiconductor...
Page 388: Cop Timeout Register (Copto)
COP counter to prevent a reset. This routine consists of writing a $5555 to the COPSRV followed by writing a $AAAA to the COPSRV before the expiration of the selected timeout period. The 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 389: Stop And Wait Mode Disable Function
System Control (SYS_CNTL) register, as described in the next section. Permanently assigned applications are last only until their next reset. Reset, Low Voltage, Stop and Wait Operations, Rev. 3 Freescale Semiconductor...
Page 390: System Control Register (Sys_Cntl)
In the 56F826 this bit is set, the pull-ups for the data bus I/O pins are disabled. Normally, the pull-ups are enabled. This bit is Reserved in the 56F827. 15.8.1.6 Reserved—Bits 7–5 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 391: System Status Register (Sys_Sts)
This register is reset upon any system reset. It is initialized only by a Power-On Reset (POR). SYS_BASE +$1 Read LVIS LVIS COPR EXTR POR Write Reset — — — Figure 15-9. System Status Register (SYS_STS) See Programmer’s Sheet on Appendix page B-118 Reset, Low Voltage, Stop and Wait Operations, Rev. 3 Freescale Semiconductor...
Page 392: Most Significant Half Of Jtag Id (Msh_Id)
15.8.3 Most Significant Half of JTAG ID (MSH_ID) This read-only register displays the Most Significant Half of the JTAG ID for the chip. For both 56F826/827 chips, read as $01F3. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 393: Least Significant Half Of Jtag Id (Lsh_Id)
This read-only register displays the Least Significant Half of the JTAG ID for the chip. For both 56F826/827 chips, read as $A01D. SYS_BASE +$7 Read Write Reset Figure 15-11. Least Significant Half of JTAG_ID (LSH_ID) See Programmer’s Sheet on Appendix page B-119 Reset, Low Voltage, Stop and Wait Operations, Rev. 3 Freescale Semiconductor...
Page 394 Stop and Wait Mode Disable Function 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 395: Once Module
Chapter 16 OnCE Module OnCE Module, Rev. 3 Freescale Semiconductor...
Page 396 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 397: Introduction
Features 16.1 Introduction This chapter describes the 56F800 core-based family chips providing board and chip-level testing capability through two on-chip modules. The 56F826/827 modules are accessed through the JTAG/OnCE port. Those ports are: ™ • On-Chip Emulation (OnCE) module • Test Access Port (TAP) plus a 16-state controller, known also as the Joint Test Action...
Page 398 • Force test data onto the outputs of a IC, while replacing its BSR in the serial data path with a single-bit register • Enable a weak pull-up current device on all input signals of a IC, ensuring deterministic test results in the presence of a continuity fault during interconnect testing 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 399: Combined Jtag/Once Interface Overview
TDI, TDO, TCK, and TMS signals. The 56F826/827 also uses the optional Test Reset (TRST) input signal and a pin used for Debug Event (DE) monitoring. Pin functions are detailed in Table 16-1. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 400: Jtag/Once Pin Descriptions
OCR control bits are reset only by assertion of RESET or COP timer reset. When the ENABLE_ONCE instruction is in the JTAGIR at the time of reset, the OCR bits are not modified. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 401: Once Module Architecture
Figures 16-2 continued in Figure 16-3 displays the OnCE module registers accessible through the JTAG port. The same module portrays the OnCE module registers accessible through the core and its corresponding OnCE interrupt vector. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 402: 56F80X Once Block Diagram
& Control OBAR OBAR2 Breakpoint and Trace Breakpoint XAB1 Logic Trace CGDB OCNTR OPDBR Pipeline PGDB Registers OPGDBR OPABFR FIFO OPABDR History OPABER Buffer Change-of-Flow Peripheral FIFO FIFO Figure 16-2. 56F80x OnCE Block Diagram 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 403: Register Summary
• OnCE Status Register (OSR) OCMDR—$00 Write Only Reset OnCE Command Register OSR—$01 Read Only EM1 EM0 HBO SBO Reset OnCE Status Register OnCE Reset* = $00 Figure 16-2. OnCE Module Registers Accessed Through JTAG OnCE Module, Rev. 3 Freescale Semiconductor...
Page 404 OnCE PGDB Register OPDBR—$09 Read 16-Bit Register Used to Execute Instructions in Debug Mode and Restore Pipeline Upon Exit Write Reset OnCE PDB Register Figure 16-2. OnCE Module Registers Accessed Through JTAG (Continued) 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 405 16-Bit Program Decode Address Reset OnCE PDB Decode Register OBAR2—$05 Read 16-bit Breakpoint Address Register (Address or Data Breakpoints) Write Reset OnCE Breakpoint Address Register 2 Figure 16-2. OnCE Module Registers Accessed Through JTAG (Continued) OnCE Module, Rev. 3 Freescale Semiconductor...
Page 406: Once Module Registers Accessed From The Core
OnCE Trap OnCE TRAPs are level 1 interrupts and are not programmable in the IPR. Note: OnCE module registers. They share functionality with the core. If used incorrectly, they can give unexpected results. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 407: Command, Status, And Control Registers
It is not possible to modify this register. MSB..LSB OSHR bits Figure 16-4. OnCE Shift Register (OSHR) Note: OnCE instructions are shifted on the data side (Select-DR-Scan) of the TAP controller not the instruction side (Select-IR-Scan). OnCE Module, Rev. 3 Freescale Semiconductor...
Page 408: Once Command Register (Ocmdr)
OnCE Program Address Register—Fetch cycle (OPABFR) FIFO halted Read-only Reserved 01100 Clear OCNTR Reserved Reserved Reserved 10000 OnCE Program Address Register—Execute cycle (OPABER) FIFO halted Read-only 10001 OnCE Program address FIFO (OPFIFO) FIFO halted Read-only 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 409: Once Decoder (Odec)
FIFO is halted while accessing the Program Address Bus (PAB) pipeline registers from User mode. The ODEC works closely with the OnCE state machine on register reads and writes. This register is not memory mapped and cannot be modified. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 410: Once Control Register (Ocr)
In addition, these bits can also be used to setup a breakpoint on one address and an interrupt on another address. Table 16-10 lists the different breakpoint configurations. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 411: Breakpoint Configuration Bits Encoding-Two Breakpoints
EM bits and breakpoint circuitry. Note: The FIFO is halted immediately after the FH bit is set. This means the FIFO can be halted in the middle of instruction execution, leading to incoherent OPFIFO register contents. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 412 To rearm an event in EM encoding 00, Debug mode must be exited, typically by executing a core instruction when setting EX and GO in the OCMDR, thereby clearing the status bits and releasing DE. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 413: Event Modifier Selection
ROM patch or the 11 encoding is used for profiling code. The EM[1:0] bits add some powerful debug techniques to the OnCE module. Profile code easily with the 01 encoding, or perform special tasks when events occur with the 10 encoding. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 414 Program Memory Fetch, Program Memory Access, or First X Memory Access. These bits are cleared on hardware reset, and are described in Table 16-12. These bits are used only in determining triggering conditions for Breakpoint 1, not for additional future breakpoint comparators. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 415: Bs[1:0] Bit Definition
Access means either a read/write can take place. These bits are cleared on hardware reset. Table 16-14 describes the bit functions. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 416: Breakpoint Programming With The Bs[1:0] And Be[1:0] Bits
16-15. The register is read/write by the OnCE unit. It is used to setup the second breakpoint for Breakpoint Operation. This register is accessed as the lowest three bits of a 16-bit word. The upper bits are reserved and should be written with 0, ensuring future compatibility. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 417: Once Status Register (Osr)
OnCE command, writing to the OCMDR, and allowing for efficient status polling. The OSR and all other OnCE registers are inaccessible in Stop mode. Bits Read HBO9 Write Reset Figure 16-16. OnCE Status Register (OSR) OnCE Module, Rev. 3 Freescale Semiconductor...
Page 418: Core Status Bit Description
SBO bit is cleared by hardware reset, provided ENABLE_ONCE is not decoded in the JTAGIR. It is also cleared by the event rearm conditions described in Section 16.7.5.5. The EM[1:0] bits determine if the core or the FIFO is halted. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 419: Breakpoint And Trace Registers
It is important to note the breakpoint/trace logic is only enabled for instructions executed outside of Debug mode. Instructions forced into the pipeline via the OnCE module do not cause trace or breakpoint events. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 420: Once Memory Address Latch Register (Omal)
Traditionally, processors had set a breakpoint in program memory. Those processors were set by replacing the instruction at the breakpoint address with an illegal instruction, thus causing a breakpoint exception. This technique is limiting 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 421: Pipeline Registers
DEBUG_REQUEST (0111) can be used to force Debug mode. 16.9 Pipeline Registers The OnCE module provides a halt capability of the core on any instruction boundary. Upon halting the core, instructions can be executed from Debug mode, providing access to on-chip OnCE Module, Rev. 3 Freescale Semiconductor...
Page 422: Once Pab Fetch Register (Opabfr)
Program Counter (PC) value. This instruction is decoded if the chip is not entered in Debug mode. OPABDR is available for read-only operations through the JTAG/OnCE port. This register is not affected by the operations performed during Debug mode. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 423: Once Pab Execute Register (Opaber)
JTAG/OnCE serial interface and only when the chip is in Debug mode. Any attempted read of OPDBR when the chip is not in Debug mode results in the JTAG shifter capturing and shifting unspecified data. Similarly, any attempted write has no effect. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 424: Once Pdb Register (Opdbr)
Debug mode. The set of supported instructions for execution from Debug mode, GO but not EX are: • JMP #xxxx • MOVE #xxxx,register 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 425: Once Pgdb Register (Opgdbr)
Debug mode results in the JTAG shifter capturing and shifting unspecified data. Note: The OPGDBR accesses corrupt PDB. Therefore, if there is a need to save the value on PDB, an OPDBR read should be executed before the first OPGDBR access in any debug session. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 426: Once Fifo History Buffer
The nth read in an n deep OPFIFO returns the latest change- of-flow address. It is recommended all OPFIFO locations are read. For example, n reads for an n deep OPFIFO so the oldest-to-newest ordering is maintained when address capture resumes. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 427: Once Fifo History Buffer
When the OPFIFO is halted in response to setting the FH bit, PAB capture halts immediately and transfers in progress can be interrupted. For instance, while determinate values are in the registers, the values may not provide entirely coherent information regarding the recent history of program flow. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 428: Breakpoint 2 Architecture
EM = 01 than when it is halted with the core due to an event occurring when EM = 00. 16.10 Breakpoint 2 Architecture All 56F800 chips contain a Breakpoint 1 Unit. The 56F80x provides a Breakpoint 2 Unit providing greater flexibility in setting breakpoints. Adding a Second Breakpoint greatly increases the debug capability of the device.
Page 429: Breakpoint Configuration
EM bits in the OnCE Control register. Figure 16-26 illustrates the breakpoint programming model for the dual breakpoint system. Note: Registers OMAC, OMAL, OMAC2, and OMAL2 are not memory mapped and their bits cannot be modified or read. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 430: Once Breakpoint Programming Model
OMAC permits setting breakpoints in RAM or ROM while in any operating mode. The OBAR is dedicated to Breakpoint 1 Logic. Figure 16-27 illustrates a block diagram of the Breakpoint 1 Unit. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 431: Breakpoint 1 Unit
OCNTR. The Breakpoint 2 Unit operates in a similar manner. A valid Breakpoint 2 address comparison occurs when the value on the PAB or CGDB matches the value in the OBAR2 for the bits selected with the OnCE Breakpoint Mask Register 2 (OBMSK2). OnCE Module, Rev. 3 Freescale Semiconductor...
Page 432: Breakpoint 2 Unit
X memory access with the first breakpoint unit. The BE/BS bits conditions may be define determining a valid breakpoint. Using these bits, breakpoints could be restricted to occur on first data memory reads or only on fetched executed 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 433: Programming The Breakpoints
3. The BE[1:0] bits in the OnCE Control register are set to 00. 4. Write the breakpoint address into the OBAR. 5. Write n – 1 into the OnCE Count register, where n is the number of valid address comparisons and before generating an OnCE event. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 434: Once Trace Logic Operation
Similarly, for EM = 01, FIFO halt, an OnCE Control register write attempts to clear the Trace Occurrence, but again the flag remains set since the conditions are still valid for Trace. To clear the Trace Occurrence and capture additional FIFO values, complete the following: 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 435: The Debug Processing State
Debug mode when the previously set trigger condition occurs, provided EM = 00, OnCE events cause entry to Debug mode. Capabilities available in Debug mode include: • Read and write the OnCE registers • Read the instruction FIFO • Reset the OnCE event counter OnCE Module, Rev. 3 Freescale Semiconductor...
Page 436: Once Normal, Debug, And Stop Modes
This execution should be avoided. Recognize this occurrence by capturing the OnCE Status (OS) bits in the JTAGIR Capture-Instruction Register (IR) then choose to send a DEBUG_REQUEST to bring the core out of Stop. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 437: Entering Debug Mode
For this reason, polling for OS = 11 is always recommended. Sending a debug request when the chip is in a Normal mode results in the chip entering Debug mode as soon as the instruction currently executing finishes. Again, the JTAGIR should be polled OnCE Module, Rev. 3 Freescale Semiconductor...
Page 438 OPDBR with GO = 1, EX = 0. Next, write a NOP to OPDBR with GO = EX = 1 • Hardware reset (assertion of RESET) brings the chip out of Debug mode provided DEBUG_REQUEST is not decoded in the JTAGI. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 439: Accessing The Once Module
JTAG to a known state. To enter the Test-Logic-Reset state on power-up, both TRST and RESET should be asserted, as shown in Figure 16-29. See the appropriate technical data sheet for minimum assertion pulse widths. TRST can change at any time with respect to TCK. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 440: Entering The Jtag Test-Logic-Reset State
JTAG state machine changes state on rising edges of TCK, or on TRST assertion and power-up. This sequence provides a simple way of resetting JTAG into a known state. JTAG Shift-DR Test-Logic-Reset State Figure 16-30. Holding TMS High to Enter Test-Logic-Reset State 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 441: Loading The Jtag Instruction Register
OnCE instructions are loaded into the Instruction Register (IR) through the Data Register (DR) path of the state machine. JTAG instructions are loaded in the IR path. The following sequence shown in Figure 16-32 demonstrates how to load the instruction DEBUG_REQUEST into the JTAGIR. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 442: Loading Debug_Request
TDO are constant: first one, and then zero. The following two bits are the OnCE Status (OS[1:0]) bits. Note: The value in OS[1:0] is shifted out whenever a new JTAG instruction is shifted in. This provides a convenient means to obtain status information. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 443: Accessing A Jtag Data Register
The first bit shifted out of TDO is a constant zero because the BYPASS register captures zero on Capture-DR per the IEEE Standard. The ensuing bits are just the bits shifted into TDI delayed by one period. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 444 Figure 16-34. As long as ENABLE_ONCE is decoded in JTAGIR, one of the two shifters is available for shifting. If a different JTAG instruction is shifted in, the BYPASS register is selected. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 445: Once Shifter Selection State Diagram
ENABLE_ONCE is being decoded in JTAGIR, the JTAG state machine is at Run-Test/Idle. The DR path can not yet have been entered, meaning the OnCE module has selected the 8- bit shifter. Please refer to Figure 16-35. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 446: Executing A Once Command By Reading The Ocr
16-bit shift is to occur (in this case, yes) and if so, whether it is a read or write. If it is a read, the register selected by the Register Select (RS) field in the OCMDR is 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 447: Executing A Once Command By Writing The Ocntr
In this sequence, $00 was read out from the OnCE Status Register, indicating the chip is in Normal mode, or the core is running. The OnCE opcode shifted in is $01, corresponding to write OnCE Count Register. In the ensuing 16-bit shift, $0003 is shifted in. Since the OnCE Count OnCE Module, Rev. 3 Freescale Semiconductor...
Page 448: Osr Status Polling
16-bit access is not associated with this opcode. On the second 8-bit sequence, $1A is read from the OnCE Status register. This read indicates the chip is in Debug mode and a hardware breakpoint has occurred. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 449: Jtagir Status Polling
ENABLE_ONCE is again shifted in. The OS bits are now eleven, indicating the chip is in Debug mode. ENABLE_ONCE does not have to be shifted in for JTAGIR polling. After reading proper status, the Data Register path can be entered directly for OnCE register accesses. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 450: Once Module Low Power Operation
Program ROM, if this is the location of the application code. 7. The chip then correctly triggers in the application code when the desired breakpoint condition is detected. 8. The JTAG port can be polled to detect the occurrence of this breakpoint. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 451 The OnCE module reset can still be forced on chip reset even if there is an ENABLE_ONCE instruction in the JTAGIR. This is accomplished by asserting the TRST pin in addition to the RESET pin, guaranteeing Reset of the OnCE module. OnCE Module, Rev. 3 Freescale Semiconductor...
Page 452 Accessing the OnCE Module 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 453: Jtag Port
Chapter 17 JTAG Port JTAG Port, Rev. 3 Freescale Semiconductor...
Page 454 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 455: Introduction
17.2 Features • Perform boundary scan operations to test circuit board electrical continuity • Bypass the for a given circuit board test by replacing the Boundary Scan Register (BSR) with a single-bit register JTAG Port, Rev. 3 Freescale Semiconductor...
Page 456: Pin Descriptions
Bit 14 of the OnCE Control Register (OCR). The TRST pin has an on-chip pull-up resistor. Debug Event—This output signal debugs events detected on a trigger condition. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 457: Jtag Port Architecture
Figure 17-2. JTAG Block Diagram A block diagram of the JTAG port is provided in Table 17-2. The JTAG port has four read/write registers: 1. IR 2. BSR 3. Device identification register 4. Bypass register JTAG Port, Rev. 3 Freescale Semiconductor...
Page 458: Register Summary
5. ENABLE_ONCE, discussed in Section 17.5.1.8 6. DEBUG_REQUEST, discussed in Section 17.5.1.9 The four bits B[3:0] of the IR, decode the nine instructions, and are illustrated in Table 17-4. All other encodings are reserved. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 459: Jtagir Register
(LSBs) of the instruction shift register are preset to 01, where the one is in the LSB location as required by the standard. The two Most Significant Bits (MSBs) may either capture status or be set to zero. New instructions are moved into the instruction shift register stage in Shift-IR state. JTAG Port, Rev. 3 Freescale Semiconductor...
Page 460: Jtagir Bypass
The data can be observed by shifting it transparently through the BSR. In a normal system configuration, many signals require external pull-ups assuring proper system operation. Consequently, the same is true for the SAMPLE/PRELOAD functionality. Data latched into the BSR during the 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 461 When this instruction is used in board-level testing with heavily loaded nodes, it may require a charging delay greater than the two TCK periods required to transition from the Update- DR state to the Capture-DR state. Two methods of providing an increase delay are available: JTAG Port, Rev. 3 Freescale Semiconductor...
Page 462 JTAG state machine is set to its reset state. • CLAMP asserts internal system reset for the system logic for the duration of CLAMP in order to force a predictable internal state while performing external boundary scan operations. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 463: Jtag Chip Identification (Cid) Register
Regsiter Read Only ID—(IR = $2) Chip PNUM PNUM PNUM PNUM MFGID MFGID MFGID MFGID MFGID MFGID MFGID MFGID MFGID MFGID MFGID MFGID Identification Regsiter Read Only Figure 17-6. JTAG Chip Identification Register (CID) JTAG Port, Rev. 3 Freescale Semiconductor...
Page 464: Chip Identification Register Configuration
0000 (For initial version only—these bits may vary) 27–22 Freescale Design Center ID 00 0111 21–12 Family and part ID 11 0010 0101 Freescale Manufacturer ID 0000 0000 1110 IEEE Requirement Always 1 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 465: Jtag Boundary Scan Register (Bsr)
BC_1 A13—Output Input/Output BC_1 A13—Output Enable Control BC_1 – – A13—Pull-up Enable Control BC_1 – – A12—Input Input/Output BC_1 A12—Output Input/Output BC_1 A12—Output Enable Control BC_1 – – A12—Pull-up Enable Control BC_1 – – JTAG Port, Rev. 3 Freescale Semiconductor...
Page 466 – A6—Output Enable Control BC_1 – – A6—Pull-up Enable Control BC_1 – – A5—Input Input/Output BC_1 – A5—Output Input/Output BC_1 – A5—Output Enable Control BC_1 – – A5—Pull-up Enable Control BC_1 – – 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 467 RD_B—Input Input/Output BC_1 RD_B—Output Input/ Output BC_1 – RD_B—Output Enable Control BC_1 – – RD_B—Pull-up Enable Control BC_1 – – WR_B—Input Input/Output BC_1 – WR_B—Output Input/Output BC_1 – WR_B—Output Enable Control BC_1 – – JTAG Port, Rev. 3 Freescale Semiconductor...
Page 468 BC_1 – D2—Output Enable Control BC_1 – D2—Pull-up Enable Control BC_1 D3—Input Input/Output BC_1 D3—Output Input/Output BC_1 – D3—Output Enable Control BC_1 – – D3—Pull-up Enable Control BC_1 – D4—Input Input/Output BC_1 – 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 469 D9—Output Enable Control BC_1 – – D9—Pull-up Enable Control BC_1 – – D10—Input Input/Output BC_1 – D10—Output Input/Output BC_1 D10—Output Enable Control BC_1 – – D10—Pull-up Enable Control BC_1 – – RESET_B—Input Input BC_1 – JTAG Port, Rev. 3 Freescale Semiconductor...
Page 470 BC_1 SRD—Output Enable Control BC_1 – – SRD—Pull-up Enable Control BC_1 – – SRFS—Input Input/Output BC_1 – SRFS—Output Input/Output BC_1 – SRFS—Output Enable Control BC_1 – – SRFS—Pull-up Enable Control BC_1 – – 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 471 – – MPIOB0—Pull-up Enable Control BC_1 – – MPIOB1—Input Input/Output BC_1 – MPIOB1—Output Input/Output BC_1 – MPIOB1—Output Enable Control BC_1 – MPIOB1—Pull-up Enable Control BC_1 – MPIOB2—Input Input/Output BC_1 – MPIOB2—Output Input/Output BC_1 – JTAG Port, Rev. 3 Freescale Semiconductor...
Page 472 MPIOB7—Pull-up Enable Control BC_1 – – MPIOD0—Input Input/Output BC_1 – MPIOD0—Output Input/Output BC_1 – MPIOD0—Output Enable Control BC_1 – – MPIOD0—Pull-up Enable Control BC_1 – – MPIOD1—Input Input/Output BC_1 – MPIOD1—Output Input/Output BC_1 – 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 473 – – MPIOD6—Pull-up Enable Control BC_1 – – MPIOD7—Input Input/Output BC_1 – MPIOD7—Output Input/Output BC_1 – MPIOD7—Output Enable Control BC_1 – – MPIOD7—Pull-up Enable Control BC_1 – – SCLK—Input Input/Output BC_1 SCLK—Output Input/Output BC_1 JTAG Port, Rev. 3 Freescale Semiconductor...
Page 474 BC_1 – – TA2—Pull-up Enable Control BC_1 – – TA1—Input Input/Output BC_1 TA1—Output Input/Output BC_1 TA1—Output Enable Control BC_1 – – TA1—Pull-up Enable Control BC_1 – – TA0—Input Input/Output BC_1 TA0—Output Input/Output BC_1 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 475: Jtag Bypass Register (Jtagbr)
Individual devices, or other devices, can be programmed with the bypass instruction so individually they become pass-through devices during testing. This allows testing of a specific chip, while still having all of the chips connected through the JTAG ports. JTAG Port, Rev. 3 Freescale Semiconductor...
Page 476: Tap Controller
TCK. The TDO pin remains in the high impedance state except during the Shift-DR or Shift-IR controller states. In these controller states, TDO is updated on the falling edge of TCK. TDI is sampled on the rising edge of TCK. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 477: Tap Controller State Diagram
JTAGIR. After this is selected, the OnCE module registers and commands are read and written through the JTAG pins using the Shift-DR-Scan path. Asserting the JTAG’s TRST pin asynchronously forces the JTAG state machine into the test-logic-reset state. JTAG Port, Rev. 3 Freescale Semiconductor...
Page 478: 56F826/827 Restrictions
V to achieve minimal power consumption. Because all 56F826/827 clocks are disabled during Stop mode, the JTAG interface provides the means of polling the device status, sampled in the Capture-IR state. 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 479: Appendix A Glossary
Appendix A Glossary Glossary, Rev. 3 Freescale Semiconductor...
Page 480 56F826/827 Peripheral User Manual, Rev. 3 Freescale Semiconductor...
Page 481: A.1 Glossary
Part of the ALU that allows single cycle shifting and rotating of data word Bus Control Register Brush DC Motor Breakpoint Enable BFIU Boot Flash Interface Unit BFLASH Boot Flash Breakpoint Configuration Bit BLDC Brushless DC Motor BOTNEG Bottom-side PWM Polarity Bit Glossary, Rev. 3 Freescale Semiconductor...
Page 482 Computer Operating Properly/Real Time Interface COPCTL COP Control COPDIS COP Timer Disable COPR COP Reset COPSRV COP Service COPTO COP Time Out CPHA Clock Phase CPOL Clock Polarity Central Processing Unit Cyclic Redundancy Code 56F826/827 Peripheral User Manual, Rev. 3 Freescale Semiconductor...
Page 483 Digital Signal Processor Edge-Aligned or Center-Aligned PWMs Erase Enable EEOF Enable External OFLAG Force Event Modifier Enable3 ENCR Encoder Control Register EOSI End of Scan Interrupt EOSIE End of Scan Interrupt Enable ERASE Erase Cycle Glossary, Rev. 3 Freescale Semiconductor...
Page 484 DSPs to optimise the data throughput Hardware Breakpoint Occurrence HLMTI High Limit Interrupt HLMTIE High Limit Interrupt Enable HOLD Hold Register HOME Home Switch Input Hardware Stack Interrupt Assert Integrated Circuit Interrupt Enable 56F826/827 Peripheral User Manual, Rev. 3 Freescale Semiconductor...
Page 485 Interrupt Service Routine ITCN Interrupt Controller JTAG Joint Test Action Group JTAGBR JTAG Bypass Register JTAGIR JTAG Instruction Register Liquid Crystal Display Loss of Lock LDOK Load Okay Lower Initialization Register LLMTI Low Limit Interrupt Glossary, Rev. 3 Freescale Semiconductor...
Page 486 Mode Fault Enable MOSI Master Out/Slave In Most Significant Bit MSH_ID Most Significant Half of JTAG ID MSTR Master Mode Multiplexer Noise Flag Nested Looping No Operation An inversion of the logical OR function 56F826/827 Peripheral User Manual, Rev. 3 Freescale Semiconductor...
Page 487 Output Polarity Select Overrun OnCE Status bits OS1 and OS0 OSHR OnCE Shift Register OnCE status bits OS1 and OS0 Oscillator OnCE Status Register OVRF Overflow Program Address Bus Permanent STOP/WAIT Disable Program Data Bus Glossary, Rev. 3 Freescale Semiconductor...
Page 488 PMFSA PWM Fault Status Acknowledge PMOUT PWM Output Control Register PMPORT PWM Port Register Polarity Power on Reset PRAM Program RAM PROG Program Cycle Processor Status Register Parity Type Peripheral Test Mode 56F826/827 Peripheral User Manual, Rev. 3 Freescale Semiconductor...
Page 489 Receive FIFO Full RIDLE Receiver Idle Line Receiver Full Interrupt Enable Read Only Memory Re-programmable Stop/Wait Disable Register Select RSCKP Receive Clock Priority RSRC Receiver Source Bit Rate Tolerance Receiver Wake-up RXSR Receive (data) Shift Register Saturation Glossary, Rev. 3 Freescale Semiconductor...
Page 490 SPI Receiver Full SPRIE SPI Receiver Interrupt Enable SPSCR SPI Status Control Register SPTE SPI Transmitter Empty SPTIE SPI Transmit Interrupt Enable Status Register Switched Reluctance Motor SSI Receive Data Slave Select 56F826/827 Peripheral User Manual, Rev. 3 Freescale Semiconductor...
Page 491 Transmitter Idle Interrupt Enable TIRQ Test Interrupt Request Register TISR Test Interrupt Source Register Test Mode bit TMEL Time Limit TMODE Test Mode bit Quadrature Timer TMR PD Timer I/O Pull-up Disable TNVHL TNVH Limit TNVSL TNVS Limit Glossary, Rev. 3 Freescale Semiconductor...
Page 492 Wake-up Condition Watchdog Enable Write Protect WSPM Wait State P Memory Wait State Data Memory Watchdog Timeout Register World Wide Web Memory words (data memory) XDB2 X Data Bus X Address Enable 56F826/827 Peripheral User Manual, Rev. 3 Freescale Semiconductor...
Page 493 Use Negative Edge of Index Pulse XRAM Data RAM XTAL External pins for clocks, oscillators, and so on Y Address Enable Zero Crossing Interrupt ZCIE Zero Crossing Interrupt Enable Zero Crossing Status ZSRC Zclock Source Glossary, Rev. 3 Freescale Semiconductor...
Page 494 56F826/827 Peripheral User Manual, Rev. 3 Freescale Semiconductor...
Page 495: Appendix B Programmer's Sheets
Appendix B Programmer’s Sheets Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 496 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 497: Introduction
Seven data ALU and five AGU registers HHHH X0, Y0, Y1 R0-R3, N A, A2, A1, A0 B, B2, B1, B0 Y1, Y0, X0 R0, R1, R2, R3 DDDDD All CPU registers N, SP OMR, SR LA, LC Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 498 X0, Y0, Y1 Three 16-bit data registers Two 36-bit accumulators accessible during ALU A, B operations The 16-bit MSP portion of two accumulators accessible A1, B1 as source operands in parallel move instructions 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 499 Immediate addressing more operator #> Immediate long addressing mode for operator #< Immediate short addressing mode force operator Miscellaneous operand notations, including generic source, destination operands, and immediate data specifiers are summarized in Table B-6. Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 500 — move) (parallel 2 + mv move) parallel — — — — move) #iiii,X:<ea> ANDC . . . 2 + ea 4 + mvb — — — — — — — #iiii,D 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 501 2 + ea — — — — — — — #iii,X:<ea> 6 + mvb #iii,D 4 + mvb xxxx . . . 6 + j x — — — — — — — — Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 502 . . . 8 + jx — — — — — — — — (no paral- ea, D 1 + ea 2 + ea — — — — — — lel move) 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 503 . . . #xxxx, D MOVE(C) 1 + ea 2 + mvc S, D X:(R2 + xx),D S,X:(R2 + xx) MOVE(I) #xx, D . . . — — — — — — — — Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 504 — — — NORM Rn, D — — (no parallel — — — — move) X:<ea> NOTC . . . 2 + ea 4 + mvb — — — — — — — 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 505 — — — — — — — move) (parallel 2 + mv — move) (no parallel TST(W) 2 + tst — move) — . . . — — — — — — — WAIT Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 506: Interrupt, Vector, And Address Tables
Table 3-38 56F827 PCS Registers Address Map (PCS_BASE = $1190) Table 3-39 Program Memory Chip Operating Modes Table 3-40 Loading Program Words Table 3-41 Reset and Interrupt Priority Table 3-42 Reset and Interrupt Starting Addresses 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 507: Programmer's Sheets
Group Priority Register (GPR9) B-23 Group Priority Register (GPR10) B-23 Group Priority Register (GPR11) B-23 Group Priority Register (GPR12) B-24 Group Priority Register (GPR13) B-24 Group Priority Register (GPR14) B-24 Group Priority Register (GPR15) B-24 Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 508 ArchIO_PortD arch.h: ArchIO.PortE (826 Only) GPIOE_BASE: 56F826 = $11E0 registers.h: ArchIO_PortE (826 Only) arch.h: ArchIO.PortF GPIOF_BASE: 56F826/827 = $11F0 registers.h: ArchIO_PortF arch.h: ArchIO.PortG (827 Only) GPIOG_BASE: 56F827 = $1240 registers.h: ArchIO_PortG (827 Only) 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 509 ArchIO_Sci1 arch.h: ArchIO.Sci2 (827 Only) SCI2_BASE: 56F827 = $1180 registers.h: ArchIO_Sci2 (827 Only) SCI Baud Rate Register (SCIBR) B-64 SCI Control Register (SCICR) B-65 SCI Control Register (SCICR) B-66 SCI Data Register (SCIDR) B-68 Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 510 TMRA_BASE: 56F826 =$10A0 registers.h: ArchIO_TimerA (826) arch.h: ArchIO.TimerA (827) TMRA_BASE: 56F827 = $1200 registers.h: ArchIO_TimerA (827) TMR Control Register (CTRL) B-85 TMR Status and Control Register (SCR) B-88 TMR Compare Register 1 (CMP1) B-90 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 511 PLL Status Register (PLLSR) B-111 PLL Select Register (CLKOSR) B-112 RESET arch.h: ArchIO.Cop COP_BASE: 56F826/827 = $1120 registers.h: ArchIO_Cop COP Control Register (COPCTL) B-113 COP Time-out Register (COPTO) B-114 COP Service Register (COPSRV) B-115 Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 512 COP System Control Register (SYS_CNTL) B-116 COP System Status Register (SYS_STS) B-118 COP Most Significant Half of JTAG_ID (MSH_ID) B-119 COP Least Significant Half of JTAG_ID (LSH_ID) B-119 Safe Storage Register (SSREG0-4) B-118 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 513 All Others Illegal Bits 15 14 13 12 11 10 Bus Control Read WAIT STATE FIELD for WAITSTATE FIELD for Register (BCR) EXTERNAL X-MEMORY EXTERNAL P-MEMORY Write $FFF9 Reset 0 Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 514 Nested Looping Not Allowed Two DO loops active Nested Looping Allowed Bits Operating Mode Read Register (OMR) Write (CPU Register) Reset *MA and MB are latched from the EXTBOOT pin on reset. Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 515 Group Priority Prog. Flash Data Flash Reserved-826 Register (GPR3) PLR15 Interface-826 Interface -826 Data Flash Write Lower Prog. Flash ITCN_BASE+$3 Upper Prog. Flash Interface-827 Interface AU-827 Interface AL-827 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 516 SPI 1 Transmitter Write and/or Error Empty and/or Error Empty ITCN_BASE+$6 Reset Bits Group Priority Read PLR29 PLR28 Register (GPR7) PLR31 PLR30 Write SPI 0 Reserved SPI 0 Reserved ITCN_BASE+$7 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 517 Bits Read PLR45 PLR44 Group Priority PLR46 PLR47 Reserved-826 Reserved-826 Register (GPR11) SCI 1 Transmission Write Transmission Ready SCI 2 Receiver SCI 2 Receiver Complete ITCN_BASE+$B Full-827 Error-827 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 518 Write Exception w/Exception Exception ITCN_BASE+$E or Limit Error-827 Reset Bits Group Priority Read PLR63 PLR62 PLR60 Register (GPR15) PLR61 Low Voltage SSI w/Exception Write PLL Loss of Lock Detector ITCN_BASE+$F Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 519 Disabled Write Inhibited to FIU Registers– Flash Enabled program/erase operation in progress. Flash Control Bits Register Read BUSY IFREN XE YE PROG ERASE MAS1 NVSTR (FIU_CNTL) Write FIU_BASE+$0 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 520 ArchIO_BootFlash_ProgramReg (826) Intelligent Programming Disabled Enabled Dumb Programming Row Number Disabled Row number currently allowed to be 0–1024 Enabled programmed. Flash Program Bits Enable Register Read DPE IPE (FIU_PE) Write FIU_BASE+$1 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 521 Enabled Intelligent Erase PAGE Page Number Disabled Page number currently allowed to be 0–128 Enabled erased. Bits Flash Erase Enable Read Register (FIU_EE) DEE IEE PAGE Write FIU_BASE+$2 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 522 This register is set to the program/erase address by development and error analysis. Program attempting to write to memory space occupied by Address flash memory. Flash Address Bits Register Read (FIU_ADDR) Write FIU_BASE+$3 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 523 Program Writing to Flash memory space sets this Data register to the program data value. Bits Flash Data Register Read (FIU_DATA) Write FIU_BASE+$4 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 524 Tnvh Timeout Tnvs Timeout Illegal Flash Read/Write Access Attempt During Erase Illegal Flash Read/Write Access Attempt During Program Flash Access Out-Of-Range Flash Interrupt Bits Enable Register Read (FIU_IE) Write FIU_BASE+$5 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 525 Interrupt Source Bit Active: Error Detected Illegal Flash Read/Write Access Attempt During Erase Illegal Flash Read/Write Access Attempt During Program Flash Access Out-Of-Range Flash Interrupt Bits Source Read Register (FIU_IS) Write FIU_BASE+$6 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 526 Tnvh Timeout Tnvs Timeout Illegal Flash Read/Write Access Attempt During Erase Illegal Flash Read/Write Access Attempt During Program Flash Access Out-Of-Range Flash Interrupt Bits Pending Read Register (FIU_IP) Write FIU_BASE+$7 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 527 Clock Divisor (N+1) Value of Clock Divisor = 2 0–15 (Values = 2, 4, 8, 16, . . . 65536) Flash Clock Divisor Bits Register Read (FIU_CKDIVISOR) Write FIU_BASE+$8 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 528 (TERASEL + 1) where N = the Clock Divisior Value 0–127 Default Erase Time = 2 x 25ns = 26.2ms Flash Terase Limit Bits Register Read TERASEL (FIU_TERASEL) Write FIU_BASE+$9 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 529 (TMEL + 1) where N = the Clock Divisior Value 0–255 Default Erase Time = 2 x 25ns = 26.2ms Flash Tme Limit Bits Register Read TMEL (FIU_TMEL) Write FIU_BASE+$A Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 530 TNVSL Timer Non-Volatile Storage Limit Tnvs = (TNVSL + 1) 0–2047 Tnvs default value = 25ns x 2 = 6.4µs Flash Tnvs Limit Bits Register Read TNVSL (FIU_TNVSL) Write FIU_BASE+$B Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 531 Timer Erase Limit Tpgs = (TPGSL + 1) 0–4095 Tpgs default value = 25ns x 2 = 12.8µs Flash Tpgs Limit Bits Register Read TPGSL (FIU_TPGSL) Write FIU_BASE+$C Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 532 TPROGL Timer Program Limit Tprog = (TPROGL + 1) 0–16383 Default Program Time Limit = 2 x 25ns = 25.6µs. Flash Tprog Limit Bits Register Read TPROGL (FIU_TPROGL) Write FIU_BASE+$D Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 533 Timer Non-Volatile Hold Limit Tnvh = (TNVHL + 1) 0–2047 Default Tnvh Value = 2 x 25ns = 6.4µs Flash Tnvh Limit Bits Register Read TNVHL (FIU_TNVHL) Write FIU_BASE+$E Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 534: Flash T Nvh1 Limit Register (Fiu_Tnvh1L)
Timer Non-Volatile Hold 1 Limit Tnvh1 = (TNVH1L + 1) 0–32767 Tnvh1 Default Value = 2 x 25ns = 102.4µs Flash Tnvh1 Limit Bits Register Read TNVH1L (FIU_TNVH1L) Write FIU_BASE+$F Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 535 Timer Recovery Limit Trcv = (TRCVL + 1) 0–511 Trcv Default Value = 2 x 25ns = 1.6µs Flash Trcv Limit Bits Register Read TRCVL (FIU_TRCVL) Write FIU_BASE+$10 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 536 Input Enabled table for all possible combinations. Bits Pull-Up Enable Read Register (PUR) Write GPIO_BASE+$0 Reset Bits Pull-Up Enable* Read Register (PUR) Write GPIO_BASE+$0 Reset *Ports A and G 827 Only Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 537 GPIO pin or the IPBus. Bits Data Register (DR) Read GPIO:_BASE+$1 Write Reset Bits Data Register (DR)* Read GPIO:_BASE+$1 Write Reset *Ports A and G 827 Only Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 538 Input Disabled corresponding GPIO pin. Input Enabled Bits Data Direction Read Register (DDR) Write GPIO_BASE+$2 Reset Bits Data Direction* Read Register (DDR) Write GPIO_BASE+$2 Reset *Ports A and G 827 Only Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 539 GPIO pin. Input Enabled Bits Peripheral Enable Read Register (PER) Write GPIO_BASE+$3 Reset Bits Peripheral Enable* Read Register (PER) Write GPIO_BASE+$3 Reset *Ports A and G 827 Only Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 540 Note: The IAR register is only for software testing. Bits Interrupt Assert Read Register (IAR) Write GPIO:_BASE+$4 Reset Bits Interrupt Assert* Read Register (IAR) Write GPIO:_BASE+$4 Reset *Ports A and G 827 Only Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 541 Interrupt detection disabled. Interrupt detection enabled. Bits Interrupt Enable Read Register (IENR) Write GPIO_BASE+$5 Reset Bits Interrupt Enable* Read Register (IENR) Write GPIO_BASE+$5 Reset *Ports A and G 827 Only Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 542 Register IPOLR is disabled IENR = 0 Bits Interrupt Polarity Read Register (IPOLR) IPOL Write GPIO_BASE+$6 Reset Bits Interrupt Polarity* Read Register (IPOLR) IPOL Write GPIO_BASE+$6 Reset *Ports A and G 827 Only Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 543 Write zeros into the IESR register. Interrupts incoming interrupt. Bits Interrupt Pending Read Register (IPR) Write GPIO:_BASE+$7 Reset Bits Interrupt Pending* Read Register (IPR) Write GPIO:_BASE+$7 Reset *Ports A and G 827 Only Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 544 IENR is set to 1. Interrupt Bits Edge-Sensitive Read Register (IESR) Write GPIO_BASE+$8 Reset Interrupt Bits Edge-Sensitive* Read Register (IESR) Write GPIO_BASE+$8 Reset *Ports A and G 827 Only Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 545 Interrupt disabled Power-down ADC the analog core command Interrupt enabled Bits ADC Control Read Register 1 (ADCR1) SYNC EOSIE ZCIE LLMTIE HLMTIE SMODE STOP Write START ADC_BASE+$0 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 546 Clock Divisor Select Value = 0–15 N = DIV[4:] + 1 = (F ) / 2N = Analog-to-Digital Converter Frequency = Interface Peripheral Bus Clock Frequency Bits ADC Control Read Register (ADCR2) Write ADC_BASE+$1 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 547 Bits Control Register Read ZCE7 ZCE6 ZCE5 ZCE4 ZCE3 ZCE2 ZCE1 ZCE0 (ADZCC1) Write ADC_BASE+$2 Reset ADC Zero Crossing Bits Control Register Read ZCE9 ZCE8 (ADZCC2) Write X:ADC_BASE+$3 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 548 • Select sequential,loop or triggered Scan Mode with SMODE[1:0] bits in register ADCR1. • Select Sample range in register ADSDIS with DSx bits. Sampling stops on encountering a set DSx bit. Sequential sampling starts at SAMPLE0. • Observe differential input restrictions Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 549 SAMPLE3 SAMPLE2 Write ADC_BASE+$5 Reset Bits ADC Channel List Read Register (ADLST4) SAMPLE7 SAMPLE6 Write ADC_BASE+$7 Reset Bits ADC Channel List Read Register (ADLST5) SAMPLE9 SAMPLE8 Write ADC_BASE+$8 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 550 To clear a specific ZCS[7:0] bit, write a value of 1 to that bit. ADC Sample Bits Disable Register Read DS9 DS8 DS7 DS6 DS5 DS4 DS3 DS2 DS1 DS0 (ADSDIS) Write ADC_BASE+$9 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 551 Zero Crossing encountered, IRQ pending itgnore all sync pulses or Start commands if ZCI is set ADC Status Bits Register1 Read CIP PDNS ZCI LLMTI HLMTI EOSI (ADSTAT1) Write ADC_BASE+$A Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 552 Channel ready to be read ADC Status Bits 15 14 13 12 11 10 Register2 Read RDY9 RDY8 RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY2 RDY0 (ADSTAT2) Write ADC_BASE+$B Reset 0 Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 553 The high limit value the result (ADRSLT0–9) is compared against. ADC Limit Status Bits Register Read HLS9 HLS8 HLS7 HLS6 HLS5 HLS4 HLS3 HLS2 HLS1 Write (ADHLSTAT) ADC_BASE+$D Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 554 Channel n result equals offset n value Channel n result not equal to offset value ADC Zero Crossing Bits Status Register Read ZCS9 ZCS8 ZCS7 ZCS6 ZCS5 ZCS4 ZCS3 ZCS2 ZCS1 ZCS0 (ADZCSTAT) Write ADC_BASE+$E Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 555 ADC Result Register 4–Address: ADC_BASE+$13 ADC Result Register 5–Address: ADC_BASE+$14 ADC Result Register 6–Address: ADC_BASE+$15 ADC Result Register 7–Address: ADC_BASE+$16 ADC Result Register 8–Address: ADC_BASE+$17 ADC Result Register 9–Address: ADC_BASE+$18 Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 556 ADC High Limit Register 4–Address: ADC_BASE+$27 ADC High Limit Register 5–Address: ADC_BASE+$28 ADC High Limit Register 6–Address: ADC_BASE+$29 ADC High Limit Register 7–Address: ADC_BASE+$2A ADC High Limit Register 8–Address: ADC_BASE+$2B ADC High Limit Register 9–Address: ADC_BASE+$2C Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 557 ADC Offset Register 4–Address: ADC_BASE+$31 ADC Offset Register 5–Address: ADC_BASE+$32 ADC Offset Register 6–Address: ADC_BASE+$33 ADC Offset Register 7–Address: ADC_BASE+$34 ADC Offset Register 8–Address: ADC_BASE+$35 ADC Offset Register 9–Address: ADC_BASE+$36 Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 558 Note: The baud rate generator is disabled until the TE or RE bit in register SCICR is set for the first time after reset. Bits SCI Baud Rate Read Register (SCIBR) Write SCI_BASE+$0 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 559 When LOOP = 1, the RSRC bit determines to RXD the internal feedback path for the receiver. Single-Wire Mode with TXD Output Fed (See the Loop Functions table at the right Back to RXD for details.) Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 560 No break characters transmitted Error interrupt requests disabled Transmit break characters Error interrupt requests enabled Bits SCI Control Read Register (SCICR) LOOP SWAI RSRC WAKE POL TEIE TIIE REIE RWU SBK Write SCI_BASE+$1 Reset 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 561 Data not available in SCI data register No Noise Received data available in SCI data Noise register Bits SCI Status Register Read TDRE TIDLE RDRF RIDLE OR (SCISR) Write SCI_BASE+$2 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 562 During a read, 9 bits of received data may be accessed. During a write, 9 bits of data to be transmitted may be accessed. Bits SCI Data Register Read RECEIVE DATA (SCIDR) Write TRANSMIT DATA SCI_BASE+$3 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 563 Clearing MODFEN does not clear the Overflow MODF flag. SPI Status and Control Reg. SPRF OVRF MODF SPTE EERIE SPR1 SPR0 SPRIE SPMSTR CPOL CPHA SPE SPTIE (SPSCR) SPI_BASE+$0 Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 564 Note: SPTE is set when a full data length transfers values. from the SPDTR register to the shift register. SPI Status and Control Reg. SPRF OVRF MODF SPTE EERIE SPR1 SPR0 SPRIE SPMSTR CPOL CPHA SPE SPTIE (SPSCR) SPI_BASE+$0 Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 565 Note 2: To cause a new value to take effect, disable and then enable the SPE bit in the SPSCR register. Bits SPI Data Size Read Register (SPDSR) DS3 DS2 DS1 DS0 Wrte SPI_BASE+$1 Reset Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 566 The SPI Transmitter Empty Bit (SPTE) in the SPSCR register indicates when the next write to register SPDRR can occur. Bits SPI Data Receive Read R15 R14 R13 R12 R11 R10 Register (SPDRR) Write SPI_BASE+$2 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 567 Note: Register SPDTR can only be written when the SPI is enabled, SPE=1. Bits SPI Data Transmit Read Register (SPDTR) Write R15 R14 R13 R12 R11 R10 SPI_BASE+$3 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 568 Read ADDR ADDR ADDR ADDR ADDR ADDR ADDR BLKSZ PCS_BASE+$0 & Write PCS_BASE+$1 Reset Bits PCSBARn Read Registers ADDR ADDR ADDR ADDR ADDR ADDR ADDR BLKSZ PCS_BASE+$2 to Write PCS_BASE+$7 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 569 Where ? = 0, 1, 2, 3, 4, 5, 6, or 7 Bits PCSORn[15:0] Read Registers PDSEN Write PCS_BASE+$0 Reset Bits Read PCSORn Registers PDSEN PCS_BASE+$1 Write Reset Bits PCSORn Registers Read PCS_BASE+$2 to PDSEN Write PCS_BASE + $7 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 570 Transmit Shift Register (TXSR) when shifting of previous data is completed. Note: Enable SSI (SSIEN=1) before writing to SSI Transmit Register. Bits SSI Transmit Read Register (STX) HIGH BYTE LOW BYTE Write SSI_BASE+$0 Reset 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 571 Receive Data Register then receives its values from this FIFO register after SSI Receive Data (SRX) register is full. Bits SSI Receive Read HIGH BYTE LOW BYTE Register (SRX) SSI_BASE+$1 Write Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 572 FIFO has more than threshold Data written to the STX or the STSR values. Bits SSI Control/Status Read DIV4 Register (SCSR) RFSI RFSL REFS RSHFD RSCKP RDMAE TDMAE Write SSI_BASE+$2 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 573 Clock source is external Bits 15 14 13 12 SSI Control Read Register (SCR2) RIE TIE RE TE RFEN TFEN RXDIR TXDIR SYN TSHFD TSCKP SSIEN NET TFSI TFSL TEFS Write SSI_BASE+$3 Reset 0 Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 574 (PM[7:0] = $00 to $FF) can be selected. Bits SSI Transmit Control Register Read PSR WL1 WL0 DC4 DC3 DC2 DC1 DC0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 (STXCR) Write SSI_BASE+$0x04 Reset Number of Bits/Word 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 575 (PM[7:0] = $00 to $FF) can be selected. Bits SSI Receive Read Control Register PSR WL1 WL0 DC4 DC3 DC2 DC1 DC0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 (SRXCR) Write SSI_BASE+$5 Reset Number of Bits/Word Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 576 The time slot register is a write-only register. It behaves like an alternate transmit data register. SSI Time Slot Register (STSR) Write DUMMY REGISTER, WRITTEN DURING INACTIVE TIME SLOTS (NETWORK MODE) SSI_BASE+$6 Reset 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 577 Indicates the number of words in the Transmit FIFO. empty flag. See Table 12-10. SeeTable 12-8. Bits SSI FIFO Read RFCNT TFCNT Control/Status RFWM TFWM Register (SFCSR) Write SSI_BASE+$7 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 578 Transmit Frame Direction Frame sync is generated internally Frame sync is generated internally Frame sync is external Frame sync is external Bits SSI Option Read Register (SOR) RFDIR TFDIR Write SSI_BASE+$9 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 579 TMRA1_CTRL (Timer A, Channel 1 Control)—Address: TMRA_BASE + $E 56F826 – $16 56F827 TMRA2_CTRL (Timer A, Channel 2 Control)—Address: TMRA_BASE + $16 56F826 – $26 56F827 TMRA3_CTRL (Timer A, Channel 3 Control)—Address: TMRA_BASE + $1E 56F826 – $36 56F827 Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 580 TMRA1_CTRL (Timer A, Channel 1 Control)—Address: TMRA_BASE + $E 56F826 – $16 56F827 TMRA2_CTRL (Timer A, Channel 2 Control)—Address: TMRA_BASE + $16 56F826 – $26 56F827 TMRA3_CTRL (Timer A, Channel 3 Control)—Address: TMRA_BASE + $1E 56F826 – $36 56F827 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 581 TMRA1_CTRL (Timer A, Channel 1 Control)—Address: TMRA_BASE + $E 56F826 – $16 56F827 TMRA2_CTRL (Timer A, Channel 2 Control)—Address: TMRA_BASE + $16 56F826 – $26 56F827 TMRA3_CTRL (Timer A, Channel 3 Control)—Address: TMRA_BASE + $1E 56F826 – $36 56F827 Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 582 TMRA1_SCR (Timer A, Channel 1 Status & Control)—Address: TMRA_BASE + $F 56F826 – $17 56F827 TMRA2_SCR (Timer A, Channel 2 Status & Control)—Address: TMRA_BASE + $17 56F826 – $27 56F827 TMRA3_SCR (Timer A, Channel 3 Status & Control)—Address: TMRA_BASE + $1F 56F826 – $37 56F827 Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 583 TMRA2_SCR (Timer A, Channel 2 Status & Control)—Address: TMRA_BASE + $17 56F826 – $27 56F827 TMRA3_SCR (Timer A, Channel 3 Status & Control)—Address: TMRA_BASE + $1F 56F826 – $37 56F827 Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 584 TMRA1_CMP1 (Timer A, Channel 1 Compare 1)—Address: TMRA_BASE + $8 56F826 – $10 56F827 TMRA2_CMP1 (Timer A, Channel 2 Compare 1)—Address: TMRA_BASE + $10 56F826 – $20 56F827 TMRA3_CMP1 (Timer A, Channel 3 Compare 1)—Address: TMRA_BASE + $18 56F826 – $30 56F827 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 585 TMRA1_CMP2 (Timer A, Channel 1 Compare 2)—Address: TMRA_BASE + $9 56F826 – $11 56F827 TMRA2_CMP2 (Timer A, Channel 2 Compare 2)—Address: TMRA_BASE + $11 56F826 – $21 56F827 TMRA3_CMP2 (Timer A, Channel 3 Compare 2)—Address: TMRA_BASE + $19 56F826 – $31 56F827 Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 586 TMRA1_CAP (Timer A, Channel 1 Capture)—Address: TMRA_BASE + $A 56F826 – $12 56F827 TMRA2_CAP (Timer A, Channel 2 Capture)—Address: TMRA_BASE + $12 56F826 – $22 56F827 TMRA3_CAP (Timer A, Channel 3 Capture)—Address: TMRA_BASE + $1A 56F826 – $32 56F827 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 587 TMRA1_LOAD (Timer A, Channel 1 Load)—Address: TMRA_BASE + $B 56F826 – $13 56F827 TMRA2_LOAD (Timer A, Channel 2 Load)—Address: TMRA_BASE + $13 56F826 – $23 56F827 TMRA3_LOAD (Timer A, Channel 3 Load)—Address: TMRA_BASE + $1B 56F826 – $33 56F827 Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 588 TMRA1_HOLD (Timer A, Channel 1 Hold)—Address: TMRA_BASE + $C 56F826 – $14 56F827 TMRA2_HOLD (Timer A, Channel 2 Hold)—Address: TMRA_BASE + $14 56F826 – $24 56F827 TMRA3_HOLD (Timer A, Channel 3 Hold)—Address: TMRA_BASE + $1C 56F826 – $34 56F827 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 589 TMRA1_CNTR (Timer A, Channel 1 Counter)—Address: TMRA_BASE + $D 56F826 – $15 56F827 TMRA2_CNTR (Timer A, Channel 2 Counter)—Address: TMRA_BASE + $15 56F826 – $25 56F827 TMRA3_CNTR (Timer A, Channel 3 Counter)—Address: TMRA_BASE + $1D 56F826 – $35 56F827 Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 590 TMRA1_CMP1 (Timer A, Channel 1 Compare1)—Address: TMRA_BASE + $18 56F827 Only TMRA2_CMP1 (Timer A, Channel 2 Compare1)—Address: TMRA_BASE + $28 56F827 Only TMRA3_CMP1 (Timer A, Channel 3 Compare1)—Address: TMRA_BASE + $38 56F827 Only 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 591 TMRA1_CMP2 (Timer A, Channel 1 Compare2)—Address: TMRA_BASE + $19 56F827 Only TMRA2_CMP2 (Timer A, Channel 2 Compare2)—Address: TMRA_BASE + $29 56F827 Only TMRA3_CMP2 (Timer A, Channel 3 Compare2)—Address: TMRA_BASE + $39 56F827 Only Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 592 TMRA1_COMSCR (Timer A, Channel 1 COMSCR )—Address: TMRA_BASE + $1A 56F827 Only TMRA2_COMSCR (Timer A, Channel 2 COMSCR )—Address: TMRA_BASE + $2A 56F827 Only TMRA3_COMSCR (Timer A, Channel 3 COMSCR )—Address: TMRA_BASE + $3A 56F827 Only Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 593 Bits 13 12 11 10 9 8 TOD Clock Read Control/Status TODSIO TODAL TEST TODDA TODHA TODMA TODSA TODSEN TODAEN TODEN (TODCS) Write TOD_BASE+$0 Reset 0 0 0 Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 594 All bits can be written when TODEN (bit 0 of TODCS) is low. Decimal range is 0-65535, Bits 0-15. Bits TOD Clock Scaler Read TIME OF DAY CLOCK SCALER (TODCSL) Write TOD_BASE+$1 Reset 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 595 ArchIO_Tod_SecondsReg TOD Second Register (TODSEC) Can be written only when TODEN is low. Decimal range is 0-59. Bits 0-5. Bits TOD Seconds Read (TODSEC) TODSEC Write TOD_BASE+$2 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 596 4 of 10 Sheet TOD Seconds Alarm Register (TODSAL) arch.h: ArchIO.Tod.SecondsAlarmReg registers.h: ArchIO_Tod_SecondsAlarmReg TOD Seconds Alarm Register Can always be modified. Bits 0-5. Bits TOD Seconds Read Alarm (TODSAL) TODSAL Write TOD_BASE+$3 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 597 TOD Minutes Register Can always be modified when TODEN is low. Decimal range is 0-59. Other bits are reserved. Bits 0-5. Bits TOD Minutes Read (TODMIN) TODMIN Write TOD_BASE+$4 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 598 TOD Minutes Alarm Register (TODMAL) arch.h: ArchIO.Tod.MinutesAlarmReg registers.h: ArchIO_Tod_MinutesAlarmReg TOD Minutes Alarm Register Can always be modified. Decimal range is 0-59. Bits 0-5. Bits TOD Minutes Read Alarm (TODMAL) TODMAL Write TOD_BASE+$5 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 599 ArchIO.Tod.HoursReg registers.h: ArchIO_Tod_HoursReg TOD Hour Register Can be modified only when TODEN is low. Decimal range is 0-23. Bits 0-4. Bits TOD Hours Read (TODHR) TODHR Write TOD_BASE+$6 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 600 TOD Hours Alarm Register (TODHAL) arch.h: ArchIO.Tod.HoursAlarmReg registers.h: ArchIO_Tod_HoursAlarmReg TOD Hour Alarm Register Can always be modified. Decimal range is 0-23. Bits 0-4. Bits TOD Hours Alarm Read (TODHAL) TODHAL Write TOD_BASE+$7 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 601 ArchIO_Tod_DaysReg TOD Day Register Can be modified only when TODEN is low. Decimal range is 0-65535. Bits 0-15. Bits TOD Days Register Read TODDAY (TODDAY) Write TOD_BASE+$8 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 602 TOD Days Alarm Register (TODDAL) arch.h: ArchIO.Tod.DaysAlarmReg registers.h: ArchIO_Tod_DaysAlarmReg TOD Day Alarm Register Can always be modified. Decimal range is 0-65535. Bits 0-15. Bits TOD Days Alarm Register Read TODDAL (TODDAL) Write TOD_BASE+$9 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 603 Postscaler output Lock detector enabled 00, 11 Reserved Bits 15 14 13 12 PLL Control Read Register (PLLCR PLLIE1 PLLIE0 LOCIE LCKON CHPMPTRI PLLPD ZSRC Write CLKGEN_BASE+$0 Reset 0 Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 604 Note: The value for n should be programmed so fout is in the normal operating range, 80 - 160MHz. Divide by 4 Divide by 8 Bits PLL Divide-By Read Register (PLLDB) LORTP PLLCOD PLLCID PLLDB Write CLKGEN_BASE+$1 Reset Reserved Bits Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 605 Note: ZSRC takes more than one IPBus clock to indicate a new selection. PLL is locked (course) Bits PLL Status Read Register (PLLSR) LOLI1 LOLI0 LOCI LCK1 LCK0 PLLPDN PRECSS ZSRC Write CLKGEN_BASE+$2 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 606 Selects clock to be “multiplexed out” on the CLKO pin. 10000 No Clock 00000 ZCLK (Default) 00001 – Reserved for factory test 01111 Bits CLKO Select Read Register (CLKOSR) CLKOSEL Write CLKGEN_BASE+$4 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 607 For the COP to run in Stop COPCTL, COPTO registers are mode, the CEN bit must also be set. read-only Bits Control Register Read (COPCTL) CSEN CWEN CEN CWP Write SYS_BASE+$0 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 608 Note: These bits can only be changed when the CWP bit in COPCTL is set to zero. Bits COP Timeout Read Register (COPTO) COP TIMEOUT Write SYS_BASE+$1 Reset Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 609 (as set in the COPTO register) expires. Note: The writes to COPSRV must be performed in the correct order BEFORE the counter times out. Bits Service Register Read COUNT (COPSRV) Write COP SERVICE REGISTER SYS_BASE+$2 Reset Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 610 0 0 0 56F826 Bits 15 14 13 12 System Control Register Read BOOT SPI PD CTRL PD SPI_SEL LVIE27 LVIE22 PD RPD MAP_B (SYS_CNTL) Write SYS_BASE +$0 Reset 0 56F827 Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 611 0 0 0 56F826 Bits 15 14 13 12 System Control Register Read BOOT SPI PD CTRL PD SPI_SEL LVIE27 LVIE22 PD RPD MAP_B (SYS_CNTL) Write SYS_BASE +$0 Reset 0 56F827 Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 612 Setting this bit will not cause a reset operation.) 2.2 V. Bits System Status Register Read COPR EXTR POR LVIS27 LVIS22 (SYS_STS) Write SYS_BASE +$1 Reset — — — Reserved Bits 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 613 SYS_BASE +$6 Reset: Bit 0 IEEE Requirement—Always = 1 Bits 11-1 Manufacturer ID = 14 (Constant Value) Bits Least Significant Half of JTAG_ID Read (LSH_ID) Write SYS_BASE +$7 Reset Reserved Bits Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 614 Safe Storage Register 0 (SSREG0)—Address: SYS_BASE + $18 Safe Storage Register 1 (SSREG1)—Address: SYS_BASE + $19 Safe Storage Register 2 (SSREG2)—Address: SYS_BASE + $1A Safe Storage Register 3 (SSREG3)—Address: SYS_BASE + $1B Safe Storage Register 4 (SSREG4)—Address: SYS_BASE + $1C 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 615 Application: Date: Programmer: Sheet Appendix B - Programmer’s Sheets, Rev. 3 Freescale Semiconductor...
Page 616 56F826/827 User Manual, Rev. 3 Freescale Semiconductor...
Page 617 Capture Mode (Input Capture Mode) bit 13-17 ADRSLT (ADC Result Registers) 9-27 Capture Register Usage 13-11 ADSDIS Cascade-count Mode 13-9 ADSDIS (ADC Sample Disable Register) 9-21 ADSTAT CC (Condition Code) bit ADSTAT (ADC Status Register) 9-22 Freescale Semiconductor Index - i...
Page 618 DEBUG_REQUEST instruction 17-11 COPDIS COPDIS (COP Timer disable) bit 16-16 Decoder COPR JTAG 17-6 COPR (COP Reset) bit 15-14 COPSRV DEE (Dumb Erase Enable) bit 6-21 COPSRV (COP Service Register) 15-10 56F826/827 User Manual, Rev. 3 Index - ii Freescale Semiconductor...
Page 619 Timing Relationships External Memory Interface (EMI) 1-22 Tme Limit Register (FIU_TMEL) 6-27 external memory port TNVH Limit Register (FIU_TNVHL) 6-30 architecture TNVH1 Limit Register (FIU_TNVH1L) 6-30 External Memory Port Architecture Tnvs Limit Register (FIU_TNVSL) 6-27 Freescale Semiconductor Index - iii...
Page 620 HLMTIE (High Limit Interrupt Enable) bit 9-15 IPR (Interrupt Pending Register) 8-19 HOLD IPR register HOLD (Hold Register) 13-20 Hold Register (HOLD) 13-20 IPS (Input Polarity Select) bit 13-17 HOME 56F826/827 User Manual, Rev. 3 Index - iv Freescale Semiconductor...
Page 621 JTAGBR MAS1 (Mass Erase Cycle Definition) bit 6-19 JTAGIR Master Mode SPI 11-5 JTAGIR (JTAG Instruction Register) 17-6 Master Signal 13-7 JTAGIR Status Polling 16-55 MB (Operating Mode B) bit 3-11 Memory Map Controls 15-13 Freescale Semiconductor Index - v...
Page 622 16-14 OnCEPort 16-7 OCNTR On-Chip Core Configuration Register Memory Map 3-12 OCNTR (OnCE Breakpoint/Trace Counter) 16-25 On-Chip Emulation (OnCE) 1-24 On-Chip Emulation (OnCE) Module 1-18 OCR (OnCE Control Register) 16-16 56F826/827 User Manual, Rev. 3 Index - vi Freescale Semiconductor...
Page 623 PFIU Registers Address Map 3-16 Program Memory 3-27 PFLASH A-10 Program RAM 1-20 PGDB A-10 programming model PGDB (Peripheral Global Data Bus) 1-17 12-8 Pin Descriptions SPI 11-7 A-10 Pipeline Registers 16-27 PSR bit 12-23 A-10 A-10 Freescale Semiconductor Index - vii...
Page 624 6-20 Interrupt Sources 10-27 Flash Terase Limit Register (FIU_TERASEL) 6-26 Loop Operation 10-17 Flash TME1 Limit Register (FIU_TMEL) 6-27 Recovery from Wait Mode 10-27 Flash TNVH Limit Register (FIU_TNVHL) 6-30 56F826/827 User Manual, Rev. 3 Index - viii Freescale Semiconductor...
Page 625 Slave Mode SPI 11-6 SPTE A-12 Slave Select SS SPI 11-8 SPTE (SPI Transmitter Empty) bit 11-21 SMODE A-12 SPTIE A-12 SMODE (Scan Mode) 9-16 SPTIE (SPI Transmit Interrupt Enable) bit 11-23 Sources of Reset 15-3 A-12 Freescale Semiconductor Index - ix...
Page 626 A-14 System Control Register (SYS_CNTL) 15-12 TOFIE (Timer Overflow Flag Interrupt Enable) bit 13-16 System Status Register (SYS_STS) 15-13 TOPNEG A-14 TPGS (Timer Program Setup Limit) bits 6-29 TPGSL A-14 56F826/827 User Manual, Rev. 3 Index - x Freescale Semiconductor...
Page 627 A-14 VLMODE A-14 VREF A-14 A-14 A-14 VSSA A-14 Wait State Data Memory (WSX) WAKE A-14 A-14 WL[1:0] bits 12-24 Word Length bits (WL[1:0]) 12-24 A-14 WSPM A-14 A-14 WSX (Wait State Data Memory) bits Freescale Semiconductor Index - xi...
Page 628 56F826/827 User Manual, Rev. 3 Index - xii Freescale Semiconductor...
Page 630 Freescale Semiconductor was negligent re- garding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.