Sci Memory Map - Freescale Semiconductor 56F800 User Manual

Register Descriptions
10.5.3.2 Wait Mode
SCI operation in Wait mode depends on the state of the SWAI bit in the SCICR.
• If SWAI is clear, SCI operates normally when CPU is in Wait mode.
• If SWAI is set, SCI clock generation ceases and the SCI module enters a power
conservation state when the CPU is in Wait mode. Setting SWAI does not affect the state
of the RE bit or the TE bit.
When SWAI is set, any transmission or reception in progress stops at Wait mode entry. The
transmission or reception resumes when either an internal or external interrupt brings the
processor out of Wait mode.
When SWAI is set the SCI module cannot generate interrupt requests during Wait mode.
Any enabled SCI interrupt request can bring the processor out of Wait mode as long as SWAI is
clear.
10.5.3.3 Stop Mode
The SCI is inactive in STOP mode for reduced power consumption. The Stop instruction does not
affect the register states. SCI operation resumes after an external interrupt brings the processor
out of Stop mode.
10.6 Register Descriptions
There are four accessible registers on SCI described in
10-10. A register address is the sum of a base address and an address offset. The base address is
defined at the system level and the address offset is defined at the module level.
18
Table 10-8. SCI Memory Map
Device Name
SCI0_BASE
826
SCI1_BASE
827 SCI2_BASE
56F826/827 User Manual, Rev. 3
Address
$1160
$1170
$1180
Table 10-9 and summarized in
Freescale Semiconductor
Table