Freescale Semiconductor 56F800 User Manual page 266

Register Descriptions
• 0 = Transmission in progress
• 1 = No transmission in progress
10.6.3.3 Receive Data Register Full Flag (RDRF)—Bit 13
This bit is set when the data in the Receive Shift register transfers to the SCIDR. Clear RDRF by
reading the SCISR, then read the SCIDR.
• 0 = Data not available in SCIDR
• 1 = Received data available in SCIDR
10.6.3.4 Receiver Idle Line Flag (RIDLE)—Bit 12
This bit is set when ten consecutive Logic 1s (if M = 0) or eleven consecutive Logic 1s (if M = 1)
appear on the receiver input. Once the RIDLE flag is cleared by the receiver detecting a Logic 0,
a valid frame must again set the RDRF flag before an idle condition can set the RIDLE flag.
• 0 = Receiver input is either active now or has never become active since the RIDLE flag
was last cleared by reset
• 1 = Receiver input has become idle (after receiving a valid frame)
Note: When the Receiver Wake-Up (RWU) bit is set, an idle line condition does not set the
RIDLE flag.
10.6.3.5 Overrun Flag (OR)—Bit 11
This bit is set when software fails to read the SCIDR before the Receive Shift register receives
the next frame. The data in the Shift register is lost, but the data already in the SCIDR is not
affected. Clear OR by reading the SCISR, then write the SCISR with any value.
• 0 = No overrun
• 1 = Overrun
10.6.3.6 Noise Flag (NF)—Bit 10
This bit is set when the SCI detects noise on the receiver input. The NF bit is set during the same
cycle as the RDRF flag, but it is not set in the case of an overrun. Clear NF by reading the SCISR,
then write the SCISR with any value.
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56F826/827 User Manual, Rev. 3
Freescale Semiconductor