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DSP56800E_Quick_Start

User's Manual

Targeting Freescale 56F8xxx Platform

Rev. 2.4, 01/04/2009

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Summary of Contents for Freescale Semiconductor DSP56800E

Page 1 DSP56800E_Quick_Start User’s Manual Targeting Freescale 56F8xxx Platform Rev. 2.4, 01/04/2009...
Page 2 Freescale was negligent regarding the design or manufacture of the part. Freescale is registered trademarks of Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. is an Equal Opportunity/Affirmative Action Employer. All other tradenames, trademarks, and registered trademarks are the property of their respective owners.
Page 3: Table Of Contents
- set two’s complement rounding mode ..2-9 2.4.1.9 archSetConvRound - set convergent rounding mode ....2-10 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform Table of Contents...
Page 4 Startup Source Code ......... 2-41 Chapter 3 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 5 Detailed API Specification ........5-91 FREESCALE SEMICONDUCTOR...
Page 6 Quick Reference ..........5-349 FREESCALE SEMICONDUCTOR...
Page 7 API Specification ......... . 5-552 FREESCALE SEMICONDUCTOR...
Page 8 API Definition..........5-869 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 9 MSCAN Bit-Timing ........5-1009 FREESCALE SEMICONDUCTOR...
Page 10 Application Configuration File Structure ......7-7 Chapter 8 viii Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 11 Software License Agreement ......... 8-1 FREESCALE SEMICONDUCTOR...
Page 12 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 13 OCCS_INIT ioctl call arguments ........5-13 FREESCALE SEMICONDUCTOR...
Page 14 INTC Module Base Address........5-61 FREESCALE SEMICONDUCTOR...
Page 15 ..........5-113 FREESCALE SEMICONDUCTOR...
Page 16 SYS_CLKOUT_DISABLE ioctl call arguments ..... . 5-165 5-119 SYS_SET_CLKOUT_0_SOURCE ioctl call arguments ....5-166 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 17 PMC_INIT ioctl call arguments ........5-213 5-158 PMC_CLEAR_FLAGS ioctl call arguments ......5-214 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform Table of Contents...
Page 18 FCAN_LOOPBACK_MODE ioctl call arguments ....5-258 5-194 FCAN_TIMER_SYNC_MODE ioctl call arguments ....5-259 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 19 FCANMB_SET_RTR ioctl call arguments ......5-296 5-231 FCANMB_SET_LEN ioctl call arguments ......5-297 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform xvii...
Page 20 ADC Module Base Address ........5-349 xviii Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 21 ADC_CLEAR_STATUS_LLMTI ioctl call arguments ....5-396 5-309 ADC_CLEAR_STATUS_HLMTI ioctl call arguments....5-397 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform Table of Contents...
Page 22 ADC_SET_INPUT_CHANNEL_A ioctl call arguments....5-441 5-348 ADC_SET_INPUT_CHANNEL_B ioctl call arguments....5-442 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 23 PDB_INIT ioctl call arguments ........5-483 5-387 PDB_SET_PRESCALER ioctl call arguments ..... . . 5-484 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform Table of Contents...
Page 24 DEC_WRITE_FILTER ioctl call arguments ......5-523 5-426 DEC_WRITE_WATCHDOG_TIMEOUT ioctl call arguments ..5-524 xxii Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 25 5-465 PWM_LOAD_OK ioctl call arguments ......5-572 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 26 PWM_GET_FAULT_INPUT_x ioctl call arguments ....5-609 5-504 PWM_SOFTWARE_OUTPUTS_CONTROL ioctl call arguments ..5-610 xxiv Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 27 SCI_RECEIVER ioctl call arguments ......5-658 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 28 ........5-694 5-578 interrupt routines of the SCI driver for the write function in non-blocking mode . . 5-694 xxvi Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 29 SPI_GET_TX_EMPTY ioctl call arguments ......5-739 5-617 SPI_GET_RX_FULL ioctl call arguments......5-740 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform xxvii...
Page 30 IIC_I_BUS_INT ioctl call arguments....... 5-786 5-654 IIC_MASTER_SLAVE_MODE ioctl call arguments ....5-787 xxviii Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 31 IIC_MASTER_OPERATION ioctl call arguments ....5-830 5-693 IIC_USE_REPEATED_START ioctl call arguments ....5-831 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform xxix...
Page 32 QT_INIT ioctl call arguments........5-876 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 33 QT_READ_COMPARE_REG2 ioctl call arguments ....5-915 5-771 QT_READ_LOAD_REG ioctl call arguments......5-916 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform xxxi...
Page 34 CMP Configuration Items for appconfig.h ......5-964 xxxii Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 35 DAC_READ_STEP ioctl call arguments ......5-1003 5-849 DAC_WRITE_MINVAL ioctl call arguments..... . . 5-1004 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform xxxiii...
Page 36 MSCAN_CLEAR_RXFRM ioctl call arguments..... 5-1048 5-888 MSCAN_STOP_IN_WAIT ioctl call arguments ..... 5-1049 xxxiv Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 37 RTC Driver Arguments - ioctl ........5-1090 FREESCALE SEMICONDUCTOR...
Page 38 TSA Type Constants ..........6-23 xxxvi Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 39 The appconfig.h File ..........7-8 FREESCALE SEMICONDUCTOR...
Page 40 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 41 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform xxxix Table of Contents...
Page 42 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR Table of Contents...
Page 43: Overview
Freescale 56F8xxx software development. Therefore it is required that users of the DSP56800E_Quick_Start tool should be familiar with the 56800E family in general, as described in the DSP56800E 16-Bit DSP Core Reference Manual (DSP56800ERM/D), MC56F8300 Peripheral User Manual (MC56F8300UM/D) and the 56F8000 Peripheral Reference Manual (MC56F8000RM), before continuing.
Page 44: Software Structure
The DSP56800E_Quick_Start tool contains many sample applications that demonstrate how to use on-chip drivers and how to implement some user-specific tasks. These sample examples are kept simple and illustrative and their intention is to minimize the learning curve. Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 45: Graphical Configuration Tool
It provides a lot of excellent features, including: • Real-Time debugging • Diagnostic tool • Demonstration tool • Education tool The full description can be found in the FreeMASTER User Manual attached to the FreeMASTER tool. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 46: Quick Start
• Copy or type the key starting on a new line at the bottom of the license.dat file. For more detailed instructions see the License_Install.txt file in the Licensing directory. • Save the license.dat file. Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 47: Install Dsp56800E_Quick_Start
In the Debugger combo box, select CCS 56800E Protocol Plug-in g) In the Connection Type combo box, select CCS Remote Connection h) Leave the check boxes unchecked (this is the default state) i) Click the OK button FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 48: Supplementary Dsp56800E_Quick_Start Installation Steps
To integrate the Graphical Configuration Tool with CodeWarrior IDE, perform the following steps: a) Launch CodeWarrior IDE from the Start->Programs->Freescale CodeWarrior menu b) Open the Commands and Key Bindings dialog window using Edit->Commands and Key Bindings Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 49 Now you should be able to execute the Graphical Configuration Tool from the CodeWarrior IDE menu or by pressing the chosen key shortcut. Note that the DSP56800E_Quick_Start project should be open in the IDE to quickly execute the Graphical Configuration Tool. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 50: Install Freemaster (Pc Master Software)
Install MC56F8xxxEVM Hardware The DSP56800E_Quick_Start for 56F8xxx has been designed and tested with the MC56F83xxEVM or MC56F8xxxDEMO target hardware. If the user wants to quickly exercise software applications included with DSP56800E_Quick_Start, MC56F8xxxEVM/DEMO hardware must be installed. Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 51 The MC56F8xxxEVM/DEMO installation information is provided with CodeWarrior installation and can be found in the following document (located in the CodeWarrior installation directory): <...>\CodeWarrior\CodeWarrior Manuals\PDF\Targeting_DSP56800E.pdf It is recommended that all DSP56800E_Quick_Start users read through this document, before proceeding with software development. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 52: Build And Run Sample Application
LED is blinking periodically. The subsequent chapters describe how to create a new application, how to use interrupts, how to use on-chip drivers and other information required to successfully create a new application. 1-10 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 53: Boot Sequence
The default value of COP Reset vector is Start(), so the standard power-up code is processed. The user is able to redefine the COP Reset service routine same way the other interrupt vectors are installed (see Section 2.5.2 on page 2-27 for more details). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 54: Power-Up/Reset
In applications developed with the DSP56800E_Quick_Start tool, the default entry point is the Start() assembly routine in the startup.c file. Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 55: Boot Sequence
It is the place where the user writes the application code. By default the function is located in the main.c file, but the file can be renamed by the user. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 56: Userpostmain()
The userPostMain() function is called after the main application code is finished. The user can add any additional code he/she wishes. By default the processor is halted by debughlt instruction here. The function is located in the appconfig.c file. Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 57: Data Types
NULL - represents null pointer • MAX_32 - maximum 32-bit signed (Word32) value • MIN_32 - minimum 32-bit signed (Word32) value • MAX_16 - maximum 16-bit signed (Word16) value • MIN_16 - minimum 16-bit signed (Word16) value FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 58: Archio Peripheral Register Structures
D0 Compare Register 1 (CMP1). Example 2-2. Using the ArchIO structure UWord16 RegValue; RegValue = periphMemRead(&ArchIO.TimerD.Channel0.HoldReg); periphMemWrite(0x8000, &ArchIO.TimerD.Channel0.CompareReg1); Code Example 2-2 shows the same operation using the periphMemRead and periphMemWrite macros described later in Section 2.4.2: Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 59: Core System's Routines And Macros
Description: The archEnableIntLvl123 macro enables interrupts at levels 1, 2 and 3 while masking the interrupts at level 0. It is accomplished by clearing bit I1 (Bit 9) and setting bit I0 (Bit 8) in the Status Register (SR). Example 2-4. archEnableIntLvl123 macro usage archEnableIntLvl123(); FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 60: Archenableintlvl23 - Enable Interrupts Levels 2 And 3
Example 2-6. archDisableInt macro usage archDisableInt(); 2.4.1.5 archResetLimitBit - reset limit bit Call(s): void archResetLimitBit(void); Arguments: None. Description: The archResetLimitBit macro resets limit bit (L) - Bit 6 in the Status Register (SR). Example 2-7. archResetLimitBit macro usage archResetLimitBit(); Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 61: Archsetnosat - Set No Saturation Mode
Arguments: None. Description: The archSet2CompRound macro sets the two’s complement rounding mode. This macro sets the rounding (R) bit - Bit 5 in the Operating Mode Register (OMR). Example 2-10. archSet2CompRound macro usage archSet2CompRound(); FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 62: Archstop - Stop Processing State
Example 2-12. archStop macro usage archStop(); 2.4.1.11 archTrap - initiate a software interrupt Call(s): void archTrap(void); Arguments: None. Description: The archTrap macro initiates a software interrupt by executing a swi instruction. Example 2-13. archTrap macro usage archTrap(); 2-10 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 63: Archwait - Wait Processing State
- get and set saturation mode Call(s): Word16 archGetSetSaturationMode(bool bSatMode); Arguments: Table 2-1. archGetSetSaturationMode arguments bSatMode State of the saturation mode to be set. false - set no saturation mode true - set saturation mode FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-11...
Page 64: Archdelay - Delay
Description: The archDelay inline function delays the program execution by the specified number of CPU cycles. Returns: None. Special Issues: The delay corresponds just roughly to the number of CPU cycles. Example 2-17. archDelay function usage archDelay(1000); 2-12 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 65: Macros For Peripheral Memory Access
Description: The periphMemRead macro reads a 16-bit word from the memory location addressed by parameter pAddr. Example 2-18. periphMemRead macro usage UWord16 RegValue; RegValue = periphMemRead(&ArchIO.TimerD.ch0.hold); This code reads the content of the timer/counter D0 Hold Register (HOLD). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-13...
Page 66: Periphmemwrite - Memory Write
Description: The periphBitSet macro sets the selected bits in a memory location addressed by parameter pAddr. Example 2-20. periphBitSet macro usage periphBitSet(0xC000, &ArchIO.TimerD.ch0.scr); This code sets bits 15 and 14 in the timer/counter D0 Status and Control Register (SCR). 2-14 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 67: Periphmeminvbitset - Invert Memory Content And Set Selected Bits
Description: The periphBitClear macro clears the selected bits in a memory location addressed by parameter pAddr. Example 2-22. periphBitClear macro usage periphBitClear(0xC000, &ArchIO.TimerD.ch0.scr); This code clears bits 15 and 14 in the timer/counter D0 Status and Control Register (SCR). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-15...
Page 68: Periphbitgrpsr - Set Bit Group To Given Value
This code sets the lower 7 bits of PLL Divide-By register to the value 10. Other bits in the register are not affected. 2.4.2.7 periphBitGrpRS - set bit group to given value Call(s): void periphBitGrpRS(UWord16 GroupMask, UWord16 Mask, UWord16 *pAddr); Arguments: Table 2-9. periphBitSet arguments GroupMask Group mask 2-16 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 69: Periphbitgrpzs - Set Bit Group To Given Value
Mask value are cleared. The “ZS” variant uses two non-interruptible instructions bfclr and bfset to accomplish the requested operation. The bfclr first clears all bits in GroupMask and bfset then sets the “one” bits there. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-17...
Page 70: Periphbitgrpset - Set Bit Group To Given Value
Example 2-26. periphBitGrpSet macro usage periphBitGrpSet(0x007f, 10, &ArchIO.Pll.plldb); This code sets the lower 7 bits of PLL Divide-By register to the value 10. Other bits in the register are not affected (but see “Caution” above). 2-18 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 71: Periphsafeackbyone - Clear (Acknowledge) Bit Flags Which Are Active-High And Are Cleared By Write-One2-19
Call(s): void periphBitChange(UWord16 Mask, UWord16 *pAddr); Arguments: Table 2-13. periphBitChange arguments Mask Bit mask. pAddr The memory address. Description: The periphBitChange macro complements the selected bits in a memory location addressed by parameter pAddr. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-19...
Page 72: Periphbittest - Test Selected Bits
Example 2-29. periphBitTest macro usage if (periphBitTest(0x8000, &ArchIO.TimerD.ch0.scr)) periphBitClear(0x8000, &ArchIO.TimerD.ch0.scr); This code checks if Timer Compare Flag (Bit 15) in the timer/counter D0 Status and Control Register (SCR) is set. 2-20 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 73: Miscellaneous Routines
(signed) unsig second argument (unsigned) Description: The impysu function multiplies 16-bit signed integer and 16-bit unsigned integer as an and returns the 32-bit signed integer result. ⋅ Returns: result of multiplication sig unsig FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-21...
Page 74: Shl2 - Optimized Version Of Shl Intrinsic Function
Word16 var1 = 1; UWord16 var2 = 15; Word16 result; result = shl2(var1, var2); /* returns 0x8000 */ This code shifts var1 variable var2 times to the left and returns the result in result variable. 2-22 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 75: Shr2 - Optimized Version Of Shr Intrinsic Function
The DSP56800E_Quick_Start tool exploits the system intrinsic functions defined in intrinsics_56800E.h header file distributed with the CodeWarrior Development Studio 56800/E Hybrid Controllers. To preserve compatibility with the DSP56800_Quick_Start tool, the intrinsics_56800E.h is included in types.h header file. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-23...
Page 76: Interrupts
Executing the JSR instruction results in the program changing its flow directly to an ISR. Also the status register and the program counter are pushed onto the stack. When the user ISR finishes, it 2-24 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 77: Isrs
C function and to restore those register values upon exiting. Also it places an RTI instruction instead of an RTS at the end of the function. See Section 2.5.3. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-25...
Page 78: Interrupt Priority Levels
This example shows the PWMA Reload Interrupt Service Routine. Note that the PWM_CLEAR_ RELOAD_FLAG ioctl() command is used to clear the Reload Interrupt Flag (Bit 5) in the PWM Control Register and that this is the user’s responsibility. 2-26 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 79: Configuring Interrupts
The DSP56800E_Quick_Start tool hides these difficulties and implementation details described above and simplifies the configuration of the interrupt priority levels to the maximal extent (while keeping the generated code optimal). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-27...
Page 80: Installing Fast Interrupts
If there is another vector address to be used for the fast interrupt processing, instead of the default INT_VECTOR_ADDR_xx, the following macros can be defined in appconfig.h INTC_FIVA0_INIT fastint0ISR INTC_FIVA1_INIT fastint1ISR where fastint0ISR and fastint1ISR are the placeholders for the fast interrupt service routine names. 2-28 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 81: Enabling Interrupts
ITCN_INIT_GPRS and ITCN_INIT_IPR are used to enable interrupts. Example 2-35. Installing ISRs and enabling interrupts 1) appconfig.h file /***************************************************************************** * Freescale Semiconductor Inc. * (c) Copyright 2004 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ****************************************************************************** * File Name: appconfig.h...
Page 82 Both bytes enable R/W: Read / Write , PS/DS select: PS only Chip Select CS1: Base address: 0x0, Blocksize: 128K , Byte Enable: 128K: Lower byte enable R/W: Read / Write , PS/DS select: DS only 2-30 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 83 Pin 10: Function: ISB0 , PullUp: Enable , Pin 11: Function: ISB1 , PullUp: Enable , Pin 12: Function: ISB2 , PullUp: Enable , #define GPIO_D_PER_INIT 0x1FC1 End of autogenerated code ********************************************************************** ..*/ #endif FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-31...
Page 84 Core System Infrastructure 2) application code (main.c file) /***************************************************************************** * Freescale Semiconductor Inc. * (c) Copyright 2004 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ****************************************************************************** * FILE NAME: main.c * DESCRIPTION: Sample application demonstrating the use of external interrupt IRQA.
Page 85 /* configure IRQ mode */ ioctl(INTC, INTC_SELECT_EDGE_MODE, INTC_IRQA ); /* enable maskable interrupts in Status Register (SR), bits I1 and I0 */ archEnableInt(); while (1) /* keep GREEN flashing */ ioctl(GPIO_C, GPIO_TOGGLE_PIN, LED_GREEN); for(i=0; i<100; i++) archDelay(0xffff); FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-33...
Page 86: Advanced Topics
Target Description Model Code Boot Data Initial Constant Jumpers Location Data Data LDM_ExtRam Large Ext RAM 0x0000 Ext RAM Ext RAM JG3 off Standard Debug project with (0x0000) (0x2000) (0x2000) JG4 on External Memory 2-34 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 87: Targets Of The Mc56F8346Cb Project
J4 on External Memory SDM_xFlash Small pFlash 0x20000 Int xRAM xFlash xFlash J5 on Stand Alone application (0x0000) (0x0000) SDM_pFlash Small pFlash 0x20000 Int xRAM pFlash xFlash J5 on Stand Alone application (0x0000) (0x0000) FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-35...
Page 88: Targets Of The Mc56F8357Evm Project
0x0000 0x0000 0x0000 Software simulator of the (sim) (sim) (sim) processor core SDM_ExtRam Small Ext RAM 0x0000 Ext RAM Ext RAM JG4 off Standard Debug project with (0x0000) (0x2000) (0x2000) JG5 on External Memory 2-36 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 89: Targets Of The Mc56F8013Demo And Mc56F8014Demo Project
Jumpers Location Data Data SDM_pFlash Small pFlash 0x4000 Int xRAM pFlash Int xRAM Stand Alone application (0x4000) (0x0000) (before data) SDM_Simulator Small 0x4000 0x0000 before Software simulator of the (sim) (sim) data processor core FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-37...
Page 90: Targets Of The Mc56F8037Evm Project
LCF syntax, so the C-like #define statements do not cause the LCF syntax errors. On the other side, the #if 0 ... #endif block excludes the LCF part of the file from C compilation. 1. Prefix file is unconditionaly included at the begining of every compiled C file. 2-38 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 91: Inside Startup Code
Although it is not very common, the initial value of the Operation Mode Register (OMR) can be specified in appconfig.h using the OMR_INIT macro. The following startup.c statements define the default initial OMR value for the cases when the user had not defined the OMR_INIT in appconfig.h: #ifndef TARGET_OMR_INIT FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-39...
Page 92 By default the two values are 0xAAAA and 0x5555. If there is any reason to change the values, the user can define the macros CONFIG_INTRAM_CHECKVALUE1 and CONFIG_INTRAM_CHECKVALUE2 in the appconfig.h file. #ifndef CONFIG_INTRAM_CHECKVALUE1 #define CONFIG_INTRAM_CHECKVALUE1 0xaaaa #endif #ifndef CONFIG_INTRAM_CHECKVALUE2 #define CONFIG_INTRAM_CHECKVALUE2 0x5555 2-40 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 93: Startup Source Code
By defining the ARCH_VECTBL_ADDR macro in the appconfig.h configuration file, the VBA may be forced to a custom value. /* relocate vector table properly */ #ifdef ARCH_VECTBL_ADDR move.l ARCH_VECTBL_ADDR,A #else move.l #_Linterrupt_vectors_addr,A #endif asrr.l #7,A move.w A0,ArchIO.Intc.vba FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-41...
Page 94 #define OSCTL_TEMP (OCCS_OSCTL_INIT & 0x3fff) /* keep internal osc. enabled */ move.w #OSCTL_TEMP,ArchIO.Pll.osctl /* OSCTL,even if PLL not used */ #endif /* setup the PLL according to appconfig.h values */ #ifdef OCCS_PLLDB_INIT move.w OCCS_PLLDB_INIT,ArchIO.Pll.plldb /* PLLDB, even if PLL not used */ #endif 2-42 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 95 0x0040, ArchIO.PortB.per /* alternate external clock on GPIO_B5 */ #elif _OCCS_EXTSEL == 1 bfset 0x1000, ArchIO.Sim.sim_gpsb0 bfclr 0x0800, ArchIO.Sim.sim_gpsb0 bfset 0x0020, ArchIO.PortB.per /* external clock on XTAL (GPIO_D5)*/ #elif _OCCS_CLKMODE bfset 0x1000, ArchIO.Sim.sim_gpscd FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-43...
Page 96 As the last, the pending PLL interrupts are cleared. move.w OCCS_PLLCR_INIT,ArchIO.Pll.pllcr /* PLL locked: final PLL setup */ skip_pll_lock: move.w ArchIO.Pll.pllsr,x0 /* clear pending clkgen interrupts */ move.w x0,ArchIO.Pll.pllsr 2-44 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 97 /* enable CS2 on GPIO PD0 */ #endif #ifdef SEMI_CSTC2_INIT move.w SEMI_CSTC2_INIT, X:(R2+2) #endif #ifdef SEMI_CSBAR3_INIT move.w SEMI_CSBAR3_INIT, X:(R0+3) #endif #ifdef SEMI_CSOR3_INIT move.w SEMI_CSOR3_INIT, X:(R1+3) bfset 0x0002, ArchIO.PortD.per /* enable CS3 on GPIO PD1 */ FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-45...
Page 98 INTXRAM_CHECK_ENABLED macro is defined in appconfig.h, this feature is activated. The memory checking process consists of tree parts: • Complete memory fill (value 0xAAAA) & read + compare • Single write, read & compare for each memory location 2-46 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 99: Memory Checking Process
/* TEST1: read & compare */ beq <t1passed /* TEST1: OK ? */ debughlt t1passed: move.w y0,x:(r1) /* TEST2: write test2 */ move.w x:(r1+1),y1 /* read from incremented address (see TEST3) */ FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-47...
Page 100 /* skip if size is 0 */ move.l #>>_Lbss_start,r1 /* dest address */ move.w #0,x0 loop_clearbss: move.w C1,X:(R5) /* clear COP watchdog counter */ move.w D1,X:(R5) move.w x0,x:(r1)+ /* clear value at r1 */ 2-48 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 101 #>>_Ldata_RAM_addr,r1/* dest address -- xRAM data start */ r2,end_xrom2xram/* copy for r2 times */ move.w C1,X:(R5) /* clear COP watchdog counter */ move.w D1,X:(R5) move.w x:(r3)+,x0 /* fetch value at address r3 */ FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-49...
Page 102 /* in any flash-based target, do copy pram-variable initialization data (and ram-based code) from pFlash storage to destination in program-ram */ #ifdef TARGET_CODE_PFLASH move.l #>>_Ldatap_size,r2/* set data size */ tsta.l r2 beq <end_prom2pram move.l #>>_Ldatap_ROM_addr,r3/* src address -- pROM data start */ 2-50 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 103 Users should make these calls at the end of main if they use debugger IO */ move.w #0,r2 */ fflush ; flush file IO */ fflush_console ; flush console IO */ end of program; halt CPU */ debughlt stop FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-51...
Page 104 Core System Infrastructure 2-52 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 105: Directory Structure
• tools contains the Graphical Configuration Tool, its configuration files, device data sheets and peripheral user manuals which can be opened directly from the GCT. • user_manuals contains the DSP56800E_Quick_Start User’s Manual and other documentation. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 106: Sample Applications Directory
CodeWarrior private data files. Tools Directory The tools directory contains the Graphical Configuration Tool executable application, the needed .dll libraries and the help files. Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 107: Src Directory
This directory may be needed to be copied manually into other CodeWarrior versions present on the host computer or into the CodeWarrior versions installed after the DSP56800E_Quick_Start was installed. See the detailed guide in Section 1.2.2.1. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 108: User_Manuals Directory
The device specific subdirectory contains all needed support files for the proper memory, system and application configuration and initialization. User_manuals Directory The user_manuals directory contains this DSP56800E_Quick_Start User’s Manual as well as other relevant documentation. Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 109: Developing Software
— LinkerFiles - contains the target specific linker command files LDM_ExtRam.cmd, LDM_IntRam.cmd, LDM_xFlash, LDM_pFlash.cmd, SDM_ExtRam.cmd, SDM_pFlash.cmd, SDM_xFlash.cmd. — Lib - contains the CodeWarrior standard libraries. • Drivers — Peripherals - contains chip specific driver source files. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 110: On-Chip Peripheral Initialization
<name_of_driver>.h (e.g. intc.h - Interrupt Controller driver include file, pwm.h - Pulse Width Modulation driver include file, etc.). See Example 4-1 where this template for timer/counter, extracted from the include file qtimer.h, is shown. Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 111: On-Chip Drivers - Interface Description
The philosophy of all input/output operations resides in these three statements (commands). These commands provide better code portability between the processors from the same family, where the base addresses of the peripheral modules are different. Therefore it is preferred to use FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 112: Ioctl()
<name_of_driver>.h include file (e.g. intc.h - Interrupt Controller driver include file, pwm.h - Pulse Width Modulation driver include file, etc.) and, at the beginning of the file, there is a list of all implemented ioctl commands. Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 113: Read()
Mode_identifier parameter specifies the mode of operation, which can be BLOCKING, NON_BLOCKING. or BUFFERED. • Buffer_pointer and number_of_words parameters specifies the buffer pointer and the number of words which will be transmitted. See Section 5.15.3.40 and Section 5.16.3.39 where the write() function is described. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 114: Interrupts And Interrupt Service Routines
See Section 4.2 to find out how to initialize on-chip peripheral modules using the appconfig.h file and the respective ioctl xx_INIT command. See Section 2.5.2, “Configuring Interrupts,” for information on installing ISRs and defining the interrupt priorities through the appconfig.h file. Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 115 Example 4-3. appconfig.h from sample application /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * File Name: appconfig.h * Description: file for static configuration of the application...
Page 116 INTC_LEVEL1 PWM_A Configuration -------------------------------------------- PWM module operation: Disabled Prescaler: /8 , PWM clock period: 2 us PWM frequency: 7.62963 Hz , Period: 131.06801 ms PWM Deadtime: n/a PWM Reload Frequency: Every 10 opportunity Alignment: Center Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 117 Pin 0: Function: CS2 , PullUp: Enable , Pin 1: Function: GPIO , Direction: Input , PullUp: Enable , Interrupt: Disable, Int.Polarity: Active high , Pin 6: Function: TXD1 , PullUp: Enable , Pin 7: Function: RXD1 , PullUp: Enable , FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 118 Pin 10: Function: ISB0 , PullUp: Enable , Pin 11: Function: ISB1 , PullUp: Enable , Pin 12: Function: ISB2 , PullUp: Enable , #define GPIO_D_PER_INIT 0x1FC1 End of autogenerated code ********************************************************************** ..*/ #endif 4-10 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 119: On-Chip Drivers
The efficiency is not only the reason for an implementation as macros. The other advantage is an easy use within the interrupt service routine, where the unwanted overhead (i.e. jump/return to/from function plus context store/restore) is thus eliminated. Further, the consistent implementation of FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 120 0xf140,R0 bfclr #0xc0,X:(R0) bfclr #0xc0,X:0xf140 bfset #0x40,X:(R0) bfset #0x40,X:0xf140 Note that the generated code depends on the selected compiler optimizations and also on the rest of the source code and on the selected target. Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 121: Macro Expansion Process
PWM_A (&ArchIO.PwmA) //i.e. PWMA base& = module_ID = 0xf140 #define ioctlPWM_SET_MODULO( pPwmBase, param) \ (*(pPwmBase)->CounterModuloReg) = param Base& + displacement calculated by C preprocessor Generated assembly code: move.w #12543, X:0xf140 Figure 5-1. Macro Expansion Process FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 122 On-chip Drivers Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 123: Occs Driver
0xF0F0 0xF130 0xF2D0 5.1.2.1 OCCS frequency calculation For exact frequency formulas, please see the OCCS documentation in the Peripheral Reference Manual for each sub-family. Different Peripheral Manuals exist for MC56F83xx, MC56F801x, MC56F802x/3x and MC56F800x sub-families. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 124: Api Definition
OCCS_CORE_FREQ macro specifying the real core clock fre- quency if crystal owscillator is sell- ected as source of clock. The value is based on the other app- config.h symbols. Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 125: Api Specification
Note: inout parameters are typically input pointer variables in which the caller passes the address of a pre-allocated data structure to a function. The function stores its results within that data structure. The actual value of the inout pointer parameter is not changed. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 126: Occs Driver Arguments - Ioctl
OCCS_SET_POSTSCALER OCCS_CLOCK_OUT_DIVIDE_BY_1 / None Sets Postscaler value. OCCS_CLOCK_OUT_DIVIDE_BY_2 / OCCS_CLOCK_OUT_DIVIDE_BY_4 / OCCS_CLOCK_OUT_DIVIDE_BY_8 and on MC56F80xx additional: OCCS_CLOCK_OUT_DIVIDE_BY_16 / OCCS_CLOCK_OUT_DIVIDE_BY_32 and on MC56F800x additional: OCCS_CLOCK_OUT_DIVIDE_BY_64 / OCCS_CLOCK_OUT_DIVIDE_BY_128 / OCCS_CLOCK_OUT_DIVIDE_BY_256 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 127 MC56F83xx, STAT on OCCS_STATUS_LOCK_1 | MC56F80xx). OCCS_STATUS_LOCK_0 | OCCS_STATUS_POWER_DOWN | OCCS_STATUS_ZCLOCK and on MC56F800x additional: OCCS_STATUS_CRYSTAL_READY OCCS_CLEAR_FLAG OCCS_STATUS_LOCK_LOST_INT1 | None Clears selected flags in PLL OCCS_STATUS_LOCK_LOST_INT0 | Status Register (PLLSR on OCCS_STATUS_CLOCK_LOST MC56F83xx, STAT on MC56F80xx). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 128 OCCS_INTERNAL_RELAX_OSC / None Set the prescaler clock source. OCCS_SET_PRESCALER_CLOCK OCCS_CRYSTAL_OSC only on devices w/ internal relax.osc.: OCCS_ENABLE / OCCS_DISABLE None Enables or powers-down the OCCS_INTERNAL_RELAX_OSC_ relaxation oscillator. OPERATION on MC56F80xx additional: OCCS_STANDBY 5-10 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 129 Returns the namber of external MC56F800x: clock cycles that have been OCCS_READ_CLOCK_CHECK_ counted since last reset TARGET counter. only on MC56F800x: OCCS_32KHZ_CRYSTAL / none Selects the frequency range of OCCS_SELECT_FREQ_RANGE OCCS__1MHZ_TO_16MHZ_CRYSTAL the crystal oscillator FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-11...
Page 130: Api Specification
5.1.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the usage of the ioctl commands. 5-12 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 131: Occs_Init Ioctl Call Arguments
In the MC56F800E (HawkV2) release, the OCCS module is set up already during the startup code. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The OCCS_INIT ioctl command is implemented as a function call. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-13...
Page 132 Design/Implementation: The OCCS_SET_CORE_CLOCK ioctl command is implemented as a macro. Example 5-2. OCCS_SET_CORE_CLOCK ioctl(OCCS, OCCS_SET_CORE_CLOCK, OCCS_CLOCK_IN_DIVIDE_BY_1 | OCCS_CLOCK_OUT_DIVIDE_BY_1 | 19); This code sets the MC56F83xx core frequency to 80MHz (if external crystal frequency is 8MHz). 5-14 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 133 PLLDB on MC56F83xx, DIVBY on MC56F80xx Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The OCCS_SET_POSTSCALER ioctl command is implemented as a macro. Example 5-3. OCCS_SET_POSTSCALER ioctl(OCCS, OCCS_SET_POSTSCALER, OCCS_CLOCK_OUT_DIVIDE_BY_8); This code sets postscaler to divide by 8. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-15...
Page 134 Special Issues: Use this command only when the ZCLOCK Source is set to the prescaler output. This command is applicable only on MC56F83xx. Design/Implementation: The OCCS_SET_PRESCALER ioctl command is implemented as a macro. Example 5-4. OCCS_SET_PRESCALER ioctl(OCCS, OCCS_SET_PRESCALER, OCCS_CLOCK_IN_DIVIDE_BY_1); This code sets the prescaler to divide by 1. 5-16 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 135 Special Issues: Use this command only when the ZCLOCK Source is set to the prescaler output. This command is applicable only on MC56F83xx. Design/Implementation: The OCCS_SET_DIVIDE_BY ioctl command is implemented as a macro. Example 5-5. OCCS_SET_DIVIDE_BY ioctl(OCCS, OCCS_SET_DIVIDE_BY, 19); This code sets divide by value to 19. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-17...
Page 136 This code enables PLL Interrupt 1 and Loss of Clock Interrupt. It is also specified that PLL Interrupt 1 is sensitive to any edge change of bit LCK1 in the PLL Status Register (PLLSR on MC56F83xx, STAT on MC56F80xx). 5-18 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 137 Design/Implementation: The OCCS_INT_DISABLE ioctl command is implemented as a macro. Example 5-7. OCCS_INT_DISABLE ioctl(OCCS, OCCS_INT_DISABLE, OCCS_LOL1_INT | OCCS_LOL0_INT | OCCS_LOSS_OF_CLOCK_INT); This code disables all OCCS interrupts - PLL Interrupt 1, PLL Interrupt 0 and Loss of Clock Interrupt. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-19...
Page 138 OCCS_DISABLE. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The OCCS_LOCK_DETECTOR ioctl command is implemented as a macro. Example 5-8. OCCS_LOCK_DETECTOR ioctl(OCCS, OCCS_LOCK_DETECTOR, OCCS_ENABLE); This code enables lock detector. 5-20 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 139 Design/Implementation: The OCCS_TURN_OFF_CHARGE_PUMP ioctl command is implemented as a macro. Example 5-9. OCCS_TURN_OFF_CHARGE_PUMP ioctl(OCCS, OCCS_TURN_OFF_CHARGE_PUMP, NULL); This command sets the CHPMPTRI bit (Bit 6) in the PLL Control Register (PLLCR on MC56F83xx, CTRL on MC56F80xx). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-21...
Page 140 Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The OCCS_SET_ZCLOCK_SOURCE ioctl command is implemented as a macro. Example 5-10. OCCS_SET_ZCLOCK_SOURCE ioctl(OCCS, OCCS_SET_ZCLOCK_SOURCE, OCCS_PRESCALER_OUTPUT); This code selects the prescaler output as DSC core clock. 5-22 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 141 Special Issues: None. Design/Implementation: The OCCS_GET_ZCLOCK_SOURCE ioctl command is implemented as a macro. Example 5-11. OCCS_GET_ZCLOCK_SOURCE UWord16 temp; temp = ioctl(OCCS, OCCS_GET_ZCLOCK_SOURCE, NULL); This code stores the state of the ZSRC bits in variable temp. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-23...
Page 142 LOLI0 | LOCI | LCK1 | LCK0 | PLLPDN | COSC_RDY | ZCRCS is set (where | is an operator meaning logical OR). Range Issues: None. Special Issues: None. Design/Implementation: The OCCS_READ_FLAG ioctl command is implemented as a macro. 5-24 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 143 Example 5-12. OCCS_READ_FLAG while (!ioctl(OCCS, OCCS_READ_FLAG, OCCS_STATUS_LOCK_1)) This code waits until Loss of Lock 1 (LCK1) flag in the PLL Status Register (PLLSR) is set (until PLL is locked). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-25...
Page 144 Design/Implementation: The OCCS_CLEAR_FLAG ioctl command is implemented as a macro. Example 5-13. OCCS_CLEAR_FLAG ioctl(OCCS, OCCS_CLEAR_FLAG, OCCS_STATUS_LOCK_LOST_INT1); This code clears bit 15 (LOLI1) in the PLL Status Register (PLLSR on MC56F83xx, STAT on MC56F80xx) by writing one to this bit. 5-26 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 145 Note that for the EXTCLK external crystal frequency, the core clock frequency is calculated directly by the C preprocessor and is available as OCCS_CORE_CLOCK macro. Example 5-14. OCCS_GET_IPBUS_FREQ UWord32 IPBusFreq; IPBusFreq = ioctl(OCCS, OCCS_GET_IPBUS_FREQ, 8000000L); This code stores the current IPBus Clock frequency in variable IPBusFreq. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-27...
Page 146 Range Issues: None. Special Issues: None. Design/Implementation: The OCCS_SET_LORTP ioctl command is implemented as a macro. Example 5-15. OCCS_SET_LORTP ioctl(OCCS, OCCS_SET_LORTP, 4); This code sets the Loss of Reference Timer Period (LORTP) to value of 4. 5-28 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 147 Special Issues: None. Design/Implementation: The OCCS_WRITE_CONTROL_REG ioctl command is implemented as a macro. Example 5-16. OCCS_WRITE_CONTROL_REG ioctl(OCCS, OCCS_WRITE_CONTROL_REG, 0x0882); This code writes 0x0882 to the PLL Control Register (PLLCR on MC56F83xx, CTRL on MC56F80xx). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-29...
Page 148 Special Issues: None. Design/Implementation: The OCCS_WRITE_DIVIDE_BY_REG ioctl command is implemented as a macro. Example 5-17. OCCS_WRITE_DIVIDE_BY_REG ioctl(OCCS, OCCS_WRITE_DIVIDE_BY_REG, 0x0C0F); This code writes 0x0C0F to the PLL Divide-by Register (PLLDB on MC56F83xx, DIVBY on MC56F80xx). 5-30 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 149 Design/Implementation: The OCCS_WRITE_OSC_CONTROL_REG ioctl command is implemented as a macro. Example 5-18. OCCS_WRITE_OSC_CONTROL_REG ioctl(OCCS, OCCS_WRITE_OSC_CONTROL_REG, 0x0201); This code writes 0x0201 to the Oscillator Control Register (OSCTL) on the chip with the Relaxation Oscillator. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-31...
Page 150 Design/Implementation: The OCCS_READ_CONTROL_REG ioctl command is implemented as a macro. Example 5-19. OCCS_READ_CONTROL_REG UWord16 uRegVal; uRegVal = ioctl(OCCS, OCCS_READ_CONTROL_REG, NULL); This code stores the content of the PLL Control Register (PLLSR on MC56F83xx, STAT on MC56F80xx) in variable uRegVal. 5-32 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 151 Design/Implementation: The OCCS_READ_DIVIDE_BY_REG ioctl command is implemented as a macro. Example 5-20. OCCS_READ_DIVIDE_BY_REG UWord16 uRegVal; uRegVal = ioctl(OCCS, OCCS_READ_DIVIDE_BY_REG, NULL); This code stores the content of the PLL Divide-by Register (PLLDB on MC56F83xx, DIVBY on MC56F80xx) in variable uRegVal. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-33...
Page 152 Design/Implementation: The OCCS_READ_STATUS_REG ioctl command is implemented as a macro. Example 5-21. OCCS_READ_STATUS_REG UWord16 uRegVal; uRegVal = ioctl(OCCS, OCCS_READ_STATUS_REG, NULL); This code stores the content of the PLL Status Register (PLLSR on MC56F83xx, STAT on MC56F80xx) in variable uRegVal. 5-34 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 153 Design/Implementation: OCCS_READ_OSC_CONTROL_REG ioctl command implemented as a macro. Example 5-22. OCCS_READ_OSC_CONTROL_REG UWord16 uRegOscCtrl; uRegOscCtrl = ioctl(OCCS, OCCS_READ_OSC_CONTROL_REG, NULL); This code stores the content of the Oscillator Control Register (OSCTL) in variable uRegOscCtrl. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-35...
Page 154 Special Issues: This command is applicable only on MC56F83xx, MC56F802x/3x and MC56F800x. Design/Implementation: The OCCS_POWER_MODE ioctl command is implemented as a macro. Example 5-23. OCCS_POWER_MODE ioctl(OCCS, OCCS_POWER_MODE, OCCS_HIGH_POWER); This code sets low power mode when a crystal is used. 5-36 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 155 Special Issues: This command is applicable only on MC56F83xx and MC56F801x. Design/Implementation: The OCCS_SHUTDOWN ioctl command is implemented as a macro. Example 5-24. OCCS_SHUTDOWN ioctl(OCCS, OCCS_SHUTDOWN, 0xDEAD); This code writes 0xDEAD to the Shutdown Register (SHUTDOWN). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-37...
Page 156 Special Issues: This command is valid only when the Relaxation Oscillator is included on the chip. Design/Implementation: OCCS_SET_PRESCALER_CLOCK ioctl command implemented as a macro. Example 5-25. OCCS_SET_PRESCALER_CLOCK ioctl(OCCS, OCCS_SET_PRESCALER_CLOCK, OCCS_INTERNAL_RELAX_OSC); This code selects the Relaxation Oscillator as an input clock to the prescaler. 5-38 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 157 Special Issues: This command is valid only when the Relaxation Oscillator is included on the chip. Design/Implementation: The OCCS_INTERNAL_RELAX_OSC_OPERATION ioctl command is implemented as a macro. Example 5-26. OCCS_INTERNAL_RELAX_OSC_OPERATION ioctl(OCCS, OCCS_INTERNAL_RELAX_OSC_OPERATION, OCCS_ENABLE); This code enables the internal Relaxation Oscillator. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-39...
Page 158 Special Issues: This command is valid only when the Relaxation Oscillator is included on the chip. Design/Implementation: The OCCS_ADJUST_RELAX_OSC_FREQ ioctl command is implemented as a macro. Example 5-27. OCCS_ADJUST_RELAX_OSC_FREQ ioctl(OCCS, OCCS_ADJUST_RELAX_OSC_FREQ, 0x20F); This code adjusts the internal Relaxation Oscillator frequency by applying 0x20F as parameter value. 5-40 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 159 Special Issues: This command is valid only when the Relaxation Oscillator is included on the chip. Design/Implementation: OCCS_TRIM_RELAX_OSC_8MHZ ioctl command implemented as a macro. Example 5-28. OCCS_TRIM_RELAX_OSC_8MHZ ioctl(OCCS, OCCS_TRIM_RELAX_OSC_8MHZ, NULL); This code adjusts the internal Relaxation Oscillator frequency to 8MHz. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-41...
Page 160 Example 5-29. OCCS_DIRECT_CLOCK_MODE ioctl(OCCS, OCCS_SELECT_EXT_CLOCK_SOURCE, OCCS_CLKIN_OSC); ioctl(OCCS, OCCS_DIRECT_CLOCK_MODE, OCCS_ENABLE); This code selects direct clock source on the XTAL pin. Please note that the appropriate GPIO pin needs to be configured properly as well. 5-42 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 161 Special Issues: Selected clock source pins need to be further configured in appropriate GPIO modules. This command is applicable only on MC56F802x/3x and MC56F800x. Design/Implementation: The OCCS_SELECT_EXT_CLOCK_SOURCE ioctl command is implemented as a macro. Example 5-30. OCCS_SELECT_EXT_CLOCK_SOURCE ioctl(OCCS, OCCS_SELECT_EXT_CLOCK_SOURCE, OCCS_CLKIN_PRI); FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-43...
Page 162 This code selects direct clock source on primary CLKIN pin (typically GPIO_B6 on MC56F802x/3x). Please note that the appropriate GPIO pin needs to be configured properly as well. 5-44 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 163 OCCS_WPROTECT_PLL_SETTINGS ioctl command implemented as a macro. Example 5-31. OCCS_WPROTECT_PLL_SETTINGS ioctl(OCCS, OCCS_WPROTECT_PLL_SETTINGS, OCCS_ENABLE_PERMANENT); This code write-protects the PLL configuration bits. It will not be possible to disable this protection until the next reset occurs. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-45...
Page 164 Design/Implementation: The OCCS_WPROTECT_OSC_SETTINGS ioctl command is implemented as a macro. Example 5-32. OCCS_WPROTECT_OSC_SETTINGS ioctl(OCCS, OCCS_WPROTECT_OSC_SETTINGS, OCCS_DISABLE_PERMANENT); This code disables write-protection of the Oscillator configuration bits. It will not be possible to enable this protection until next the reset occurs. 5-46 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 165 Special Issues: This command is applicable only on MC56F802x/3x and MC56F800x. Design/Implementation: The OCCS_WPROTECT_CLK_SETTINGS ioctl command is implemented as a macro. Example 5-33. OCCS_WPROTECT_CLK_SETTINGS ioctl(OCCS, OCCS_WPROTECT_CLK_SETTINGS, OCCS_ENABLE); This code write-protects the Frequency configuration bits. It will be possible to disable this protection later. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-47...
Page 166 Special Issues: This command is applicable only on MC56F802x/3x and MC56F800x. Design/Implementation: The OCCS_SET_CLOCK_CHECK ioctl command is implemented as a macro. Example 5-34. OCCS_SET_CLOCK_CHECK ioctl(OCCS, OCCS_SET_CLOCK_CHECK, OCCS_ENABLE); This code enables clock checking function and resets counters REF_COUNT and TARGET_CNT. 5-48 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 167 Special Issues: This command is applicable only on MC56F802x/3x and MC56F800x. Design/Implementation: The OCCS_TEST_CLOCK_CHECK ioctl command is implemented as a macro. Example 5-35. OCCS_TEST_CLOCK_CHECK while (ioctl(OCCS, OCCS_TEST_CLOCK_CHECK, NULL)) This code waits until clock checking function is finished - bit CHK_ENA is cleared. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-49...
Page 168 Special Issues: This command is applicable only on MC56F802x/3x and MC56F800x. Design/Implementation: The OCCS_READ_CLOCK_CHECK_REFERENCE ioctl command is implemented as a macro. Example 5-36. OCCS_READ_CLOCK_CHECK_REFERENCE UWord16 reference = ioctl(OCCS, OCCS_READ_CLOCK_CHECK_REFERENCE, NULL); This code returns result of clock checking function for internal reference clock. 5-50 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 169 Special Issues: This command is applicable only on MC56F802x/3x and MC56F800x. Design/Implementation: The OCCS_READ_CLOCK_CHECK_TARGET ioctl command is implemented as a macro. Example 5-37. OCCS_READ_CLOCK_CHECK_TARGET UWord16 target = ioctl(OCCS, OCCS_READ_CLOCK_CHECK_TARGET, NULL); This code returns result of clock checking function for external clock. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-51...
Page 170 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The OCCS_SELECT_FREQ_RANGE ioctl command is implemented as a macro. Example 5-38. OCCS_SELECT_FREQ_RANGE ioctl(OCCS, OCCS_SELECT_FREQ_RANGE, OCCS_1MHZ_TO_16MHZ); This code sets the crystal oscillator range from 1MHZ to 16MHz. 5-52 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 171: Occs Driver Sample Application
LEDs. The debugging LEDs are driven by the PWM module, which is configured according to the pwm_demo application. OCCS driver application found e.g. {DSP56800E_Quick_Start Source}\..\sample_applications\MC56F8346EVM\occs_demo directory and consists of the application project occs_demo.mcp and the source code for the application main.c. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-53...
Page 172 Example 5-39. OCCS driver sample application - appconfig.h /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2007 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * File Name: appconfig.h * Description: file for static configuration of the application...
Page 173 #define INT_VECTOR_ADDR_21 occs_isr #define INT_PRIORITY_LEVEL_21 INTC_LEVEL0 #define INT_VECTOR_ADDR_78 pwm_reload_isr #define INT_PRIORITY_LEVEL_78 INTC_LEVEL0 PWM_A Configuration -------------------------------------------- PWM module operation: Enabled Prescaler: /8 , PWM clock period: 1 us PWM frequency: 15.25925 Hz , Period: 65.534 ms FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-55...
Page 174 Pin 10: Function: ISA2 , PullUp: Enable , #define GPIO_C_DDR_INIT 0x000F #define GPIO_C_PER_INIT 0x07F0 GPIO_D Configuration -------------------------------------------- Pin 0: Function: CS2 , PullUp: Enable , Pin 1: Function: GPIO , Direction: Input , PullUp: Enable , Interrupt: Disable, 5-56 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 175 Pin 10: Function: ISB0 , PullUp: Enable , Pin 11: Function: ISB1 , PullUp: Enable , Pin 12: Function: ISB2 , PullUp: Enable , #define GPIO_D_DDR_INIT 0x00C0 #define GPIO_D_PER_INIT 0x1F01 End of autogenerated code ********************************************************************** ..*/ #endif FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-57...
Page 176 Example 5-40. OCCS driver sample application - main.c /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2007 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * FILE NAME: main.c * DESCRIPTION: Sample application demonstrating usage of OCCS driver.
Page 177 /* configure Interrupt Controller (IPR) */ ioctl(INTC, INTC_INIT, NULL); /* enable loss-of-clock interrupt */ ioctl(OCCS, OCCS_CLEAR_FLAG, OCCS_STATUS_CLOCK_LOST); ioctl(OCCS, OCCS_INT_ENABLE, OCCS_LOSS_OF_CLOCK_INT); /* enable maskable interrupts in Status Register (SR), bits I1 and I0 */ archEnableInt(); while(1) ioctl(COP, COP_CLEAR_COUNTER, NULL); FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-59...
Page 178 GPIO_INIT, NULL); #endif #ifdef GPIO_B ioctl(GPIO_B, GPIO_INIT, NULL); #endif #ifdef GPIO_C ioctl(GPIO_C, GPIO_INIT, NULL); #endif #ifdef GPIO_D ioctl(GPIO_D, GPIO_INIT, NULL); #endif #ifdef GPIO_E ioctl(GPIO_E, GPIO_INIT, NULL); #endif #ifdef GPIO_F ioctl(GPIO_F, GPIO_INIT, NULL); #endif 5-60 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 179: Intc Driver
The following header files are needed in order to use the INTC device driver: Required Header File(s): #include “qs.h“ #include “intc.h” The following information may be found in the header file intc.h. Public Data Structure(s): none FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-61...
Page 180: Configuration Items
Initial values for the Fast Interrupt Vector Address Registers. These values installs the fast service routines for fast inter- INTC_FIVA1_INIT rupts 0 and 1. When not defined, the value of INT_VECTOR_ADDR_n where n=INTC_FIMx_INIT is used. 5-62 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 181: Api Specification
INTC regis- ters. INTC_INTERRUPTS INTC_ENABLE / None Globally enables or disables the inter- INTC_DISABLE rupts processed by the INTC module. Note that this is not equal as enabling interrupts in the processor core. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-63...
Page 182 IRQA and IRQB processor pins. INTC_SELECT_EDGE_MODE INTC_IRQA | None Selects interrupts for which to set fall- INTC_IRQB ing edge sensitive mode. INTC_SELECT_LEVEL_MODE INTC_IRQA | None Selects interrupts for which to set low INTC_IRQB level sensitive mode. 5-64 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 183: Detailed Api Specification
5.2.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the usage of the ioctl commands. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-65...
Page 184 Design/Implementation: The INTC_INIT ioctl command is implemented as a function call. Example 5-41. INTC_INIT ioctl(INTC, INTC_INIT, NULL); This code initializes the INTC module by the values defined in appconfig.h. The appconfig.h file can be edited manually or generated by the Graphical Configuration Tool. 5-66 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 185 Special Issues: Note that there are additional interrupt enable bits on the 56F8xxx core. You may access these bits with archEnableInt or archDisableInt macros. Design/Implementation: The INTC_INTERRUPTS ioctl command is implemented as a macro. Example 5-42. INTC_INTERRUPTS ioctl(INTC, INTC_INTERRUPTS, INTC_DISABLE); This code disables the interrupt processing. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-67...
Page 186 Use INTC_SET_IPL_n_RAW command if you wish to use a variable as the command parameter. Design/Implementation: The INTC_SET_IPL_n ioctl command is implemented as a macro. Example 5-43. INTC_SET_IPL_n ioctl(INTC, INTC_SET_IPL_34, INTC_LEVEL1); This code sets the interrupt priority level 1 for the interrupt number 34. 5-68 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 187 Design/Implementation: The INTC_SET_IPL_n_RAW ioctl command is implemented as a macro. Example 5-44. INTC_SET_IPL_n_RAW UWord16 ipl = ioctl(INTC, INTC_GET_IPL_34_RAW, NULL); ioctl(INTC, INTC_SET_IPL_34_RAW, ipl); This code saves and later restores the interrupt priority level for interrupt number 34. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-69...
Page 188 Design/Implementation: The INTC_GET_IPL_n_RAW ioctl command is implemented as a macro. Example 5-45. INTC_GET_IPL_n_RAW UWord16 ipl = ioctl(INTC, INTC_GET_IPL_34_RAW, NULL); ioctl(INTC, INTC_SET_IPL_34_RAW, ipl); This code saves and later restores the interrupt priority level for interrupt number 34. 5-70 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 189 INTC_SET_FASTINTx implementation contains compile-time validation of requested priority level. Design/Implementation: The INTC_SET_FASTINTx ioctl commands are implemented as macros. Example 5-46. INTC_SET_FASTINT0 ioctl(INTC, INTC_SET_FASTINT0, 34); This code sets interrupt #34 as the fast interrupt 0. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-71...
Page 190 Design/Implementation: The INTC_SET_FASTINTx_VEC ioctl commands are implemented as macros. Example 5-47. INTC_SET_FASTINT0_VEC ioctl(INTC, INTC_SET_FASTINT0_VEC, MyFastISR); This code sets the function named MyFastISR as the service routine for the fast interrupt 0. The correct prototype of the function is void MyFastISR(void); 5-72 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 191 Example 5-48. INTC_GET_PENDING_FLAG if(ioctl(INTC, INTC_GET_PENDING_FLAG, 34)) // interrupt 34 is pending - it is probably masked // or disabled, otherwise the ISR would be called This code tests whether the interrupt #34 is pending. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-73...
Page 192 Returns: ICTL Register value. Range Issues: None. Special Issues: None. Design/Implementation: The INTC_READ_CONTROL_REG ioctl command is implemented as a macro. Example 5-49. INTC_READ_CONTROL_REG UWord16 ictl = ioctl(INTC, INTC_READ_CONTROL_REG, NULL); This code reads the ITCL register. 5-74 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 193 Range Issues: None. Special Issues: None. Design/Implementation: The INTC_GET_INT_STATE ioctl command is implemented as a macro. Example 5-50. INTC_GET_INT_STATE if(ioctl(INTC, INTC_GET_INT_STATE, NULL)) // there is an interrupt to be processed This code tests the ICTL.INT bit. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-75...
Page 194 Design/Implementation: The INTC_GET_INT_LEVEL ioctl command is implemented as a macro. Example 5-51. INTC_GET_INT_LEVEL if(ioctl(INTC, INTC_GET_INT_LEVEL, NULL) > 1) // there is level2 of level3 interrupt being or // waiting to be processed This code tests the ICTL.IPIC bit filed. 5-76 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 195 Design/Implementation: The INTC_GET_INT_NUMBER ioctl command is implemented as a macro. Example 5-52. INTC_GET_INT_NUMBER if(ioctl(INTC, INTC_GET_INT_NUMBER, NULL) == 34) // interrupt #34 is just being or // waiting to be processed This code tests the ICTL.IPIC bit filed. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-77...
Page 196 Design/Implementation: The INTC_READ_IRQPINS ioctl command is implemented as a macro. Example 5-53. INTC_READ_IRQPINS if(ioctl(INTC, INTC_READ_IRQPINS, NULL) & INTC_IRQA) // the IRQA input pin is currently driven high This code tests the state of the IRQA processor pin. 5-78 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 197 Range Issues: None. Special Issues: None. Design/Implementation: The INTC_SELECT_EDGE_MODE ioctl command is implemented as a macro. Example 5-54. INTC_SELECT_EDGE_MODE ioctl(INTC, INTC_SELECT_EDGE_MODE, INTC_IRQA); This code sets the falling-edge sensitivity mode for the external interrupt IRQA. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-79...
Page 198 Range Issues: None. Special Issues: None. Design/Implementation: The INTC_SELECT_LEVEL_MODE ioctl command is implemented as a macro. Example 5-55. INTC_SELECT_LEVEL_MODE ioctl(INTC, INTC_SELECT_LEVEL_MODE, INTC_IRQB); This code sets the low-level sensitivity mode for the external interrupt IRQB. 5-80 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 199: Intc Driver Application
INTC driver application found e.g. {DSP56800E_Quick_Start Source}\..\sample_applications\MC56F8346EVM\irq_demo directory and consists of the application project irq_demo.mcp and the source code for the application main.c. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-81...
Page 200 Example 5-56. INTC driver application - appconfig.h /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * File Name: appconfig.h * Description: file for static configuration of the application...
Page 201 Pin 1: Function: GPIO , Direction: Input , PullUp: Enable , Interrupt: Disable, Int.Polarity: Active high , Pin 6: Function: TXD1 , PullUp: Enable , Pin 7: Function: RXD1 , PullUp: Enable , Pin 8: Function: PS/CS0 , PullUp: Enable , FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-83...
Page 202 Pin 10: Function: ISB0 , PullUp: Enable , Pin 11: Function: ISB1 , PullUp: Enable , Pin 12: Function: ISB2 , PullUp: Enable , #define GPIO_D_PER_INIT 0x1FC1 End of autogenerated code ********************************************************************** ..*/ #endif 5-84 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 203 Example 5-57. INTC driver application - main.c /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * FILE NAME: main.c * DESCRIPTION: Sample application demonstrating the use of external interrupt IRQA.
Page 204 (1) /* keep GREEN flashing */ ioctl(GPIO_C, GPIO_TOGGLE_PIN, LED_GREEN); for(i=0; i<100; i++) archDelay(0xffff); 5-86 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 205: Wintc Driver
The following header files are needed in order to use the WINTC device driver: Required Header File(s): #include “qs.h“ #include “wintc.h” The following information may be found in the header file wintc.h. Public Data Structure(s): none FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-87...
Page 206: Configuration Items
Initial value for the Vector Base Address Register. WINTC_IAR0_INIT UWord16 Initial value for the Interrut Assigment Register 0. WINTC_IAR1_INIT UWord16 Initial value for the Interrut Assigment Register 1. WINTC_IAR2_INIT UWord16 Initial value for the Interrut Assigment Register 2. 5-88 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 207: Api Specification
( item1 & item2 & item3 ) Table 5-65. ioctl commands pParam Return Description WINTC_INIT NULL None Applies the appconfig.h static configu- ration to the respective WNTC regis- ters. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-89...
Page 208 WINTC_SET_INT_EOnCE_ WINTC_ENABLE / None Enables/disables transmit register TRANSMIT_REGISTER_EMPTY WINTC_DISABLE empty interrupt. WINTC_SET_INT_EOnCE_ WINTC_ENABLE / None Enables/disables trace buffer inter- TRACE_BUFFER WINTC_DISABLE rupt. WINTC_SET_INT_EOnCE_ WINTC_ENABLE / None Enables/disables breakpoint unit 0 BREAKPOINT_UNIT0 WINTC_DISABLE interrupt. 5-90 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 209: Detailed Api Specification
5.3.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the usage of the ioctl commands. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-91...
Page 210 Design/Implementation: The WINTC_INIT ioctl command is implemented as a function call. Example 5-58. WINTC_INIT ioctl(WINTC, WINTC_INIT, NULL); This code initializes the WINTC module by the values defined in appconfig.h. The appconfig.h file can be edited manually or generated by the Graphical Configuration Tool. 5-92 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 211 Special Issues: Note that there are additional interrupt enable bits on the 56F8xxx core. You may access these bits with archEnableInt or archDisableInt macros. Design/Implementation: The WINTC_INTERRUPTS ioctl command is implemented as a macro. Example 5-59. WINTC_INTERRUPTS ioctl(WINTC, WINTC_INTERRUPTS, WINTC_DISABLE); This code disables the interrupt processing. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-93...
Page 212 Range Issues: None. Special Issues: None. Design/Implementation: The WINTC_GET_INT_STATE ioctl command is implemented as a macro. Example 5-60. WINTC_GET_INT_STATE if(ioctl(WINTC, WINTC_GET_INT_STATE, NULL)) // there is an interrupt to be processed This code tests the ICSR.INT_DIS bit. 5-94 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 213 Design/Implementation: The WINTC_GET_INT_LEVEL ioctl command is implemented as a macro. Example 5-61. WINTC_GET_INT_LEVEL if(ioctl(WINTC, WINTC_GET_INT_LEVEL, NULL) > 1) // there is level2 of level3 interrupt being or // waiting to be processed This code tests the ICSR.IPIC bit filed. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-95...
Page 214 Design/Implementation: The WINTC_GET_INT_NUMBER ioctl command is implemented as a macro. Example 5-62. WINTC_GET_INT_NUMBER if(ioctl(WINTC, WINTC_GET_INT_NUMBER, NULL) == 34) // interrupt #34 is just being or // waiting to be processed This code tests the ICSR.VAB bit filed. 5-96 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 215 Range Issues: UWord16 value must be in range of 10 to 44. Special Issues: None. Design/Implementation: WINTC_ASSIGN_USERx_VECTOR ioctl command implemented as a macro. Example 5-63. WINTC_ASSIGN_USERx_VECTOR ioctl(WINTC, WINTC_ASSIGN_USER1_VECTOR, 11) This code re-assigns the interrupt vector 11 to USER1 interrupt with interrupt priority level 1. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-97...
Page 216 Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The WINTC_SET_INT_EOnCE_STEP_COUNTER ioctl command is implemented as a macro. Example 5-64. WINTC_SET_INT_EOnCE_STEP_COUNTER ioctl(WINTC, WINTC_SET_INT_EOnCE_STEP_COUNTER, WINTC_ENABLE) This code enables the step counter interrupt. 5-98 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 217 / disables the receiver register full interrupt. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: WINTC_SET_INT_EOnCE_RECEIVER_REGISTER_FULL ioctl command is implemented as a macro. Example 5-65. WINTC_SET_INT_EOnCE_RECEIVER_REGISTER_FULL ioctl(WINTC, WINTC_SET_INT_EOnCE_RECEIVER_REGISTER_FULL, WINTC_ENABLE) This code enables the receiver register full interrupt. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-99...
Page 218 / disables the transmit register empty interrupt. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The WINTC_SET_INT_EOnCE_TRANSMIT_REGISTER_EMPTY ioctl command is implemented as a macro. Example 5-66. WINTC_SET_INT_EOnCE_TRANSMIT_REGISTER_EMPTY ioctl(WINTC, WINTC_SET_INT_EOnCE_TRANSMIT_REGISTER_EMPTY, WINTC_ENABLE) This code enables the transmit register empty interrupt. 5-100 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 219 Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The WINTC_SET_INT_EOnCE_TRACE_BUFFER ioctl command is implemented as a macro. Example 5-67. WINTC_SET_INT_EOnCE_TRACE_BUFFER ioctl(WINTC, WINTC_SET_INT_EOnCE_TRACE_BUFFER, WINTC_ENABLE) This code enables the trace buffer interrupt. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-101...
Page 220 0 interrupt. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: WINTC_SET_INT_EOnCE_BREAKPOINT_UNIT0 ioctl command is implemented as a macro. Example 5-68. WINTC_SET_INT_EOnCE_BREAKPOINT_UNIT0 ioctl(WINTC, WINTC_SET_INT_EOnCE_BREAKPOINT_UNIT0, WINTC_ENABLE) This code enables the breakpoint unit 0 interrupt. 5-102 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 221: Intc Driver Application
WINTC driver application found e.g. {DSP56800E_Quick_Start Source}\..\sample_applications\MC56F8006DEMO\gpio_demo directory and consists of the application project irq_demo.mcp and the source code for the application main.c. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-103...
Page 222 Example 5-69. WINTC driver application - appconfig.h /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * File Name: appconfig.h * Description: file for static configuration of the application...
Page 223 Pin 3: Function: GPIO , Direction: Input , PullUp: Disable , Interrupt: Enable , Int.Polarity: Active high , Pin 4: Function: GPIO , Direction: Input , PullUp: Enable , Interrupt: Disable, Int.Polarity: Active high , FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-105...
Page 224 Pin 6: Function: RXD , PullUp: Enable , Pin 7: Function: TXD , PullUp: Enable , #define GPIO_B_PUR_INIT 0xFFF3U #define GPIO_B_PER_INIT 0xFFC0U #define GPIO_B_IENR_INIT 0x000CU #define GPIO_B_IPOLR_INIT 0x0003U End of autogenerated code ********************************************************************** ..*/ #endif 5-106 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 225 Example 5-70. WINTC driver application - main.c /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2009 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * FILE NAME: main.c * DESCRIPTION: Sample application which shows how to simply toggle a GPIO LED pin and also how to handle interrupts from GPIO.
Page 226 /* Note: This code is targeted to all 56F8xxx-based evaluation boards. So we need to check what GPIO instances are actually implemented */ #ifdef GPIO_A ioctl(GPIO_A, GPIO_INIT, NULL); #endif #ifdef GPIO_B ioctl(GPIO_B, GPIO_INIT, NULL); #endif #ifdef GPIO_C ioctl(GPIO_C, GPIO_INIT, NULL); #endif #ifdef GPIO_D 5-108 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 227 GPIO_INIT, NULL); #endif #ifdef GPIO_E ioctl(GPIO_E, GPIO_INIT, NULL); #endif #ifdef GPIO_F ioctl(GPIO_F, GPIO_INIT, NULL); #endif FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-109...
Page 228 5-110 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 229: Cop Driver
The following header files are needed in order to use the COP device driver: Required Header File(s): #include "qs.h" #include "cop.h" The following information may be found in the header file cop.h. Public Data Structure(s): None FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-111...
Page 230: Configuration Items
Arguments: Table 5-79. COP Driver Arguments - ioctl pModuleBase COP module identifier. Use COP. Commands found in cop.h which are used to modify the COP module status and con- trol registers. See Table 5-80. 5-112 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 231 Configures COP device to run in COP_DISABLE WAIT mode (COP_ENABLE) or to stop in WAIT mode (COP_DISABLE). COP_WRITE_PROTECT NULL None When this command is issued all suc- cessive COP commands have no effect until RESET (except the COP_CLEAR_COUNTER). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-113...
Page 232: Detailed Api Specification
Sets COP clock prescaler COP_SET_CLOCK_PRESCALER COP_DIV16/ COP_DIV256/ COP_DIV1024 5.4.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the usage of the ioctl commands. 5-114 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 233 Example 5-71. COP_INIT ioctl(COP, COP_INIT, NULL); This code initializes the COP module by the values defined in appconfig.h. The appconfig.h file can be edited manually or generated by the Graphical Configuration Tool. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-115...
Page 234 Design/Implementation: The COP_DEVICE command is implemented as a macro. Example 5-72. COP_DEVICE /* configure desired COP parameters */ /* ... */ /* enable it */ ioctl(COP, COP_DEVICE, COP_ENABLE); This code enables the COP module. Before enabling, the COP configuration should be taken. 5-116 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 235 Design/Implementation: The COP_SET_TIMEOUT ioctl command is implemented as a macro. Example 5-73. COP_SET_TIMEOUT /* set COP timeout to cca 1 sec for 8 MHz external clock */ ioctl(COP, COP_SET_TIMEOUT, 7813); This code sets the COP timeout to cca 1 second. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-117...
Page 236 Returns: the Count Register (COPCTR) content. Range Issues: None. Special Issues: None. Design/Implementation: The COP_READ_COUNTER ioctl command is implemented as a macro. Example 5-74. COP_READ_COUNTER UWord16 cnt = ioctl(COP, COP_READ_COUNTER, NULL); This code reads the Count Register. 5-118 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 237 COP_CLEAR_COUNTER, NULL); This code clears the COP timer and prevents for generating a RESET. The command must be issued periodically with a period that is lower than the COP timeout period (see COP_SET_TIMEOUT). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-119...
Page 238 COP counter clearing service sequence (0x5555) to the COP Service Register. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The COP_CLEAR_COUNTER_PART1 ioctl command is implemented as a macro. Example 5-76. COP_CLEAR_COUNTER_PART1 ioctl(COP, COP_CLEAR_COUNTER_PART1, NULL); This code writes 0x5555 to the COP Service Register. 5-120 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 239 COP counter clearing service sequence (0xAAAA) to the COP Service Register Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The COP_CLEAR_COUNTER_PART2 ioctl command is implemented as a macro. Example 5-77. COP_CLEAR_COUNTER_PART2 ioctl(COP, COP_CLEAR_COUNTER_PART2, NULL); This code writes 0xAAAA to the COP Service Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-121...
Page 240 Returns: None. Range Issues: None Special Issues: None. Design/Implementation: The COP_RUN_IN_STOP command is implemented as a macro. Example 5-78. COP_RUN_IN_STOP ioctl(COP, COP_RUN_IN_STOP, COP_DISABLE); This code disables the COP module in STOP (power down) mode. 5-122 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 241 Range Issues: None Special Issues: None. Design/Implementation: The COP_RUN_IN_WAIT command is implemented as a macro. Example 5-79. COP_RUN_IN_WAIT ioctl(COP, COP_RUN_IN_WAIT, COP_ENABLE); This code enables the COP module to be active in WAIT (power down) mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-123...
Page 242 Design/Implementation: The COP_WRITE_PROTECT ioctl command is implemented as a macro. Example 5-80. COP_WRITE_PROTECT ioctl(COP, COP_WRITE_PROTECT, NULL); This code write protects all successive changes of the COP module, except for the COP_CLEAR_COUNTER command. Until RESET, change of the COP configuration is not possible. 5-124 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 243 Range Issues: None. Special Issues: This command is applicable only on MC56F802x/3x and MC56F800x. Design/Implementation: The COP_LOR_WATCHDOG ioctl command is implemented as a macro. Example 5-81. COP_LOR_WATCHDOG ioctl(COP, COP_LOR_WATCHDOG, COP_DISABLE); This code disables the loss-of-reference-clock watchdog. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-125...
Page 244 Special Issues: This command is applicable only on MC56F802x/3x or MC56F800x. Design/Implementation: The COP_SET_CLOCK_SOURCE ioctl command is implemented as a macro. Example 5-82. COP_SET_CLOCK_SOURCE ioctl(COP, COP_SET_CLOCK_SOURCE, COP_RLX_OSC); This code selects internal relaxation oscillator as the COP clock source. 5-126 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 245 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The COP_SET_CLOCK_PRESCALER ioctl command is implemented as a macro. Example 5-83. COP_SET_CLOCK_PRESCALER ioctl(COP, COP_SET_CLOCK_PRESCALER, COP_DIV1024); This code selects 1024 clock prescaler. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-127...
Page 246: Cop Driver Application
Example 5-84. COP Driver Application - appconfig.h /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2007 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * File Name: appconfig.h...
Page 247 #define SEMI_CSBAR1_INIT 0x0005 #define SEMI_CSBAR2_INIT 0x0005 #define SEMI_CSOR0_INIT 0x1FC3 #define SEMI_CSOR1_INIT 0x1BA3 #define SEMI_CSOR2_INIT 0x1DA3 INTC Configuration -------------------------------------------- All maskable interrupts disabled: No IRQ A trigger mode: Low-level sensitive IRQ B trigger mode: Low-level sensitive FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-129...
Page 248 Pin 10: Function: ISB0 , PullUp: Enable , Pin 11: Function: ISB1 , PullUp: Enable , Pin 12: Function: ISB2 , PullUp: Enable , #define GPIO_D_PER_INIT 0x1FC1 End of autogenerated code ********************************************************************** ..*/ #endif 5-130 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 249 Example 5-85. COP Driver Application - main.c /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2007 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * FILE NAME: main.c * DESCRIPTION: Sample application which demostrates how COP reset can be handled.
Page 250 SYS_CLEAR_RESET_SOURCE, SYS_ALL_RESETS); for(;;) ioctl(GPIO_LEDS, GPIO_TOGGLE_PIN, LED_Y); archDelay(0xffff); /* RED LED turned off */ ioctl(GPIO_LEDS, GPIO_CLEAR_PIN, LED_R | LED_Y); /* init COP module, see appconfig.h */ ioctl(COP, COP_INIT, NULL); /* let COP expire */ while(1) 5-132 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 251: Sys Driver
SEMI (EMI)- System Bus External Memory Interface Table 5-94. Module Base Address Module base address MC56F800x MC56F801x MC56F802x/3x MC56F83xx of / for SYS (SIM_BASE) 0xF240 0xF140 0xF100 0xF350 LVI (LVI_BASE) 0xF160 0xF140 0xF360 SEMI (SEMI_BASE) 0xF020 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-133...
Page 252: Api Definition
The initial values of the Chip Select Timing Control Registers (0-7). These values are written during the startup code. SEMI_BCR_INIT UWord16 The initial value of the Bus Control Register. This value is written during the startup code. 5-134 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 253 The initial value of the Peripheral Clock Rate Register. SIM_PCE_INIT Uword16 The initial values of the Peripheral Clock Enable Registers. SIM_SDR_INIT Uword16 The initial values of the Peripheral Stop Disable Registers. SIM_PROT_INIT UWord16 The initial value of the Protection Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-135...
Page 254: Api Specification
& intersection of items is allowed ( item1 & item2 & item3 ) Table 5-99. ioctl commands param Return Description SYS_INIT NULL None Initializes SYS (SIM and LVI) modules using the data from con- figuration file (appconfig.h). 5-136 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 255 Returns the content of the SIM MC56F802x/3x only: Software Control Register. SYS_READ_SW_CONTROL_REG n ( n =0..3) SYS_READ_LSH_JTAG_ID NULL UWord16 Reads the Least Significant Half of JTAG ID. SYS_READ_MSH_JTAG_ID NULL UWord16 Reads the Most Significant Half of JTAG ID. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-137...
Page 256 SYS_PWMB_PINS | SYS_PWMA0_PINS | SYS_PWMA1_PINS | SYS_DATA_PINS | SYS_CTRL_PINS | SYS_ADR_PINS | SYS_JTAG_PINS | SYS_TMRD_PINS | SYS_TMRC_PINS | SYS_TMRA_PINS MC56F83xx, MC56F801x and SYS_ENABLE/ None Enables or disables the CLKOUT MC56F802x/3x only: SYS_DISABLE processor pin. SYS_CLKOUT 5-138 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 257 Enables internal interconnection SYS_ENABLE_INTERNAL_ between timer and other periph- TMR_SIGNAL list of timer signals which can be eral modules. routed internally depends on the MC56F801x only: None Disables internal signal intercon- concrete device SYS_DISABLE_INTERNAL_ nection. TMR_SIGNAL FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-139...
Page 258 SYS_SET_FAULT2_SOURCE output signal or “PIN”. SYS_SET_DAC0SYNC_SOURCE SYS_SET_DAC1SYNC_SOURCE For example: general command format: SYS_SET_ isig _SOURCE SYS_DAC1SYNCSRC_PIT0 SYS_FAULT2SRC_PIN list of commands and possible parameters depends on the concrete device 5-140 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 259 SYS_B3PAD_TA3 SYS_SET_B7PAD_FUNCTION SYS_SET_B6PAD_FUNCTION SYS_B4PAD_TA0 SYS_SET_B5PAD_FUNCTION SYS_B4PAD_CLKO SYS_SET_B4PAD_FUNCTION SYS_B4PAD_SS1 SYS_SET_B3PAD_FUNCTION SYS_B4PAD_PSRC2 SYS_SET_B2PAD_FUNCTION SYS_B4PAD_TB0 SYS_SET_B1PAD_FUNCTION SYS_SET_B0PAD_FUNCTION SYS_SET_C12PAD_FUNCTION SYS_SET_C8PAD_FUNCTION SYS_SET_D5PAD_FUNCTION general command format: SYS_SET_ pad _FUNCTION list of commands and possible parameters depends on the concrete device FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-141...
Page 260 SYS_REDUCED_POWER and SYS_POWER_MODE_ PERMANENT flags. MC56F802x/3x and MC56F800x only: SYS_ENABLE / None Write-protects clock-related set- SYS_WPROTECT_CLOCK_SETTINGS SYS_DISABLE / tings configured by the following SYS_ENABLE_PERMANENT / commands: SYS_DISABLE_PERMANENT SYS_PERIPH_CLK_ENABLE SYS_ENABLE_IN_STOP SYS_HS_CLOCK_ENABLE 5-142 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 261 . interface SEMI_READ_BASEREG n ( n =0..7) NULL UWord16 Direct read access to the SEMI SEMI_READ_OPTIONREG n ( n =0..7) (register registers. SEMI_READ_CONTROLREG value) available on devices with external memory interface FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-143...
Page 262: Detailed Api Specification
5.5.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrates the usage of the ioctl commands. 5-144 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 263 Example 5-86. SYS_INIT ioctl(SYS, SYS_INIT, NULL); This code initializes the system support registers by the values defined in appconfig.h. The appconfig.h file can be edited manually or generated by the Graphical Configuration Tool. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-145...
Page 264 Special Issues: None. Design/Implementation: The SYS_STOP command is implemented as a macro. Example 5-87. SYS_STOP ioctl(SYS, SYS_STOP, SYS_DISABLE); /* ... */ ioctl(SYS, SYS_STOP, SYS_ENABLE); This code disables the STOP mode and then enables it again. 5-146 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 265 Range Issues: None. Special Issues: None. Design/Implementation: The SYS_STOP_PERMANENT_DISABLE command is implemented as a macro. Example 5-88. SYS_STOP_PERMANENT_DISABLE ioctl(SYS, SYS_STOP_PERMANENT_DISABLE, NULL); This code disables permanently the STOP mode. This state cannot be changed until reset. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-147...
Page 266 Special Issues: None. Design/Implementation: The SYS_WAIT command is implemented as a macro. Example 5-89. SYS_WAIT ioctl(SYS, SYS_WAIT, SYS_DISABLE); /* ... */ ioctl(SYS, SYS_WAIT, SYS_ENABLE); This code disables the WAIT mode and then enables it again. 5-148 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 267 Range Issues: None. Special Issues: None. Design/Implementation: The SYS_WAIT_PERMANENT_DISABLE command is implemented as a macro. Example 5-90. SYS_WAIT_PERMANENT_DISABLE ioctl(SYS, SYS_WAIT_PERMANENT_DISABLE, NULL); This code disables permanently the WAIT mode. This state cannot be changed until reset. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-149...
Page 268 Description: The SYS_SOFTWARE_RESET ioctl issues software reset immediately. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SYS_SOFTWARE_RESET command is implemented as a macro. Example 5-91. SYS_SOFTWARE_RESET ioctl(SYS, SYS_SOFTWARE_RESET, NULL); This code issues the software reset. 5-150 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 269 Special Issues: None. Design/Implementation: The SYS_ONCE command is implemented as a macro. Example 5-92. SYS_ONCE ioctl(SYS, SYS_ONCE, SYS_DISABLE); /* ... */ ioctl(SYS, SYS_ONCE, SYS_ENABLE); This code disables the OnCE module and then enables it again. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-151...
Page 270 Special Issues: This command is applicable only on MC56F83xx, MC56F801x and MC56F802x/3x. Design/Implementation: The SYS_WRITE_SW_CONTROL_REGn command is implemented as a macro. Example 5-93. SYS_WRITE_SW_CONTROL_REGn ioctl(SYS, SYS_WRITE_SW_CONTROL_REG2, 0x0000); This code writes 0x0000 to the SIM Software Control Register 2. 5-152 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 271 Special Issues: This command is applicable only on MC56F83xx, MC56F801x and MC56F802x/3x. Design/Implementation: The SYS_READ_SW_CONTROL_REGn command is implemented as a macro. Example 5-94. SYS_READ_SW_CONTROL_REGn UWord16 tmp = ioctl(SYS, SYS_READ_SW_CONTROL_REG0, NULL); This code reads the SIM Software Control Register 0. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-153...
Page 272 Range Issues: for the MC56F83xx and MC56F801x this reads 0x401D. For MC56F802x/3x this reads 0x801D Special Issues: None. Design/Implementation: The SYS_READ_LSH_JTAG_ID command is implemented as a macro. Example 5-95. SYS_READ_LSH_JTAG_ID UWord16 lID = ioctl(SYS, SYS_READ_LSH_JTAG_ID, NULL); This code reads the Least Significant Half of JTAG ID. 5-154 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 273 Range Issues: for the MC56F83xx this reads 0x01F4 and for MC56F80xx this reads 0x01F2. Special Issues: None. Design/Implementation: The SYS_READ_MSH_JTAG_ID command is implemented as a macro. Example 5-96. SYS_READ_LSH_JTAG_ID UWord16 mID = ioctl(SYS, SYS_READ_MSH_JTAG_ID, NULL); This code reads the Most Significant Half of JTAG ID. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-155...
Page 274 Special Issues: The reset source bits in the SIM Reset Status Register are “sticky” and are not cleared automatically appropriate reset apply. SYS_CLEAR_RESET_SOURCE to clear the reset status bits after you read it. Design/Implementation: The SYS_TEST_RESET_SOURCE command is implemented as a macro. 5-156 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 275 /* clear reset status bits for next use*/ ioctl (SYS, SYS_CLEAR_RESET_SOURCE, SYS_ALL_RESETS); This code tests whether the previous Reset was caused by the COP module. Then it clears the reset status bits so the next Reset source can be identified correctly. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-157...
Page 276 Another COP flag is for lost-of-reference-clock COP reset (SYS_COP_LOR_RESET). There are new Partial Power Down flag (SYS_PARTIAL_PD_RESET) and Low Voltage Detect Reset (SYS_LOW_VOLTAGE_RESET) Returns: None. Range Issues: None. Special Issues: Design/Implementation: The SYS_CLEAR_RESET_SOURCE command is implemented as a macro. 5-158 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 277 /* clear reset status bits for next use*/ ioctl (SYS, SYS_CLEAR_RESET_SOURCE, SYS_ALL_RESETS); This code tests whether the previous Reset was caused by the COP module. Then it clears the reset status bits so the next Reset source can be identified correctly. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-159...
Page 278 Design/Implementation: The SYS_PULL_UP_ENABLE command is implemented as a macro. Example 5-99. SYS_PULL_UP_ENABLE ioctl(SYS, SYS_PULL_UP_ENABLE, SYS_TMRA_PINS | SYS_ADR_PINS | SYS_DATA_PINS); This code enables pull-ups for timer A pins, address bus pins and data bus pins. 5-160 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 279 Design/Implementation: The SYS_PULL_UP_DISABLE command is implemented as a macro. Example 5-100. SYS_PULL_UP_DISABLE ioctl(SYS, SYS_PULL_UP_ENABLE, SYS_TMRA_PINS | SYS_ADR_PINS | SYS_DATA_PINS); This code disables pull-ups for timer A pins, address bus pins and data bus pins. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-161...
Page 280 Design/Implementation: The SYS_CLKOUT command is implemented as a macro. Example 5-101. SYS_CLKOUT ioctl(SYS, SYS_CLKOUT, SYS_DISABLE); /* ... */ ioctl(SYS, SYS_CLKOUT, SYS_ENABLE); This code disables (tri-states) the CLKOUT processor pin and then enables it again. 5-162 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 281 Example 5-102. SYS_CLKOUT_SELECT ioctl(SYS, SYS_CLKOUT_SELECT, SYS_CLKOUT_SYSCLK); /* ... */ ioctl(SYS, SYS_CLKOUT_SELECT, SYS_CLKOUT_OSC); This code first selects the (default) system core clock to be output on the CLKOUT pin. Then it replaces it by the oscillator clock. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-163...
Page 282 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The SYS_CLKOUT_ENABLE command is implemented as a macro. Example 5-103. SYS_CLKOUT_ENABLE ioctl(SYS, SYS_CLKOUT_ENABLE, SYS_CLKO_0 This code enables the CLKOUT 0 processor pin. 5-164 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 283 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The SYS_CLKOUT_DISABLE command is implemented as a macro. Example 5-104. SYS_CLKOUT_DISABLE ioctl(SYS, SYS_CLKOUT_DISABLE, SYS_CLKO_1 This code enables the CLKOUT 1 processor pin. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-165...
Page 284 SYS_SET_CLKOUT_0_SOURCE, SYS_CLKOUT_SYSCLK); /* ... */ ioctl(SYS, SYS_SET_CLKOUT_0_SOURCE, SYS_CLKOUT_COSC); This code first selects the (default) system core clock to be output on the CLKOUT 0 pin. Then it replaces it by the crystal oscillator clock. 5-166 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 285 SYS_SET_CLKOUT_1_SOURCE, SYS_CLKOUT_SYSCLK); /* ... */ ioctl(SYS, SYS_SET_CLKOUT_1_SOURCE, SYS_CLKOUT_COSC); This code first selects the (default) system core clock to be output on the CLKOUT 1 pin. Then it replaces it by the crystal oscillator clock. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-167...
Page 286 MC56F83xx, MC56F801x and MC56F802x/3x. Design/Implementation: The SYS_ACLK_ENABLE command is implemented as a macro. Example 5-107. SYS_ACLK_ENABLE ioctl(SYS, SYS_ACLK_ENABLE, SYS_ACLK_OSC); This code enables the oscillator clock to output pin. 5-168 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 287 MC56F83xx, MC56F801x and MC56F802x/3x. Design/Implementation: The SYS_ACLK_DISABLE command is implemented as a macro. Example 5-108. SYS_ACLK_DISABLE ioctl(SYS, SYS_ACLK_DISABLE, SYS_ACLK_OSC); This code reverts the A23 pin back to the original A23 functionality. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-169...
Page 288 56F800E family CPUs. Design/Implementation: The SYS_SET_PADS_FUNCTION command is implemented as a macro. Example 5-109. SYS_SET_PADS_FUNCTION ioctl(SYS, SYS_SET_PADS_FUNCTION, SYS_PADS_SPI1); This code sets the function of selected pads as SPI1. 5-170 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 289 SYS_SET_isig_SOURCE ioctl command for a more general replacement on MC56F802x/3x platform. Design/Implementation: The SYS_ENABLE_INTERNAL_TMR_SIGNAL command is implemented as a macro. Example 5-110. SYS_ENABLE_INTERNAL_TMR_SIGNAL ioctl(SYS, SYS_ENABLE_INTERNAL_TMR_SIGNAL, SYS_T3_PWMSYNC); This code enables the Timer channel 3 input to be sourced from PWM reload_sync signal. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-171...
Page 290 SYS_SET_isig_SOURCE ioctl command for a more general replacement on MC56F802x/3x platform. Design/Implementation: The SYS_DISABLE_INTERNAL_TMR_SIGNAL command is implemented as a macro. Example 5-111. SYS_DISABLE_INTERNAL_TMR_SIGNAL ioctl(SYS, SYS_DISABLE_INTERNAL_TMR_SIGNAL, SYS_T3_PWMSYNC); This code disables the Timer channel 3 input to be sourced from PWM reload_sync signal. 5-172 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 291 Range Issues: None. Special Issues: None. Design/Implementation: The SYS_PERIPH_CLK_ENABLE command is implemented as a macro. Example 5-112. SYS_PERIPH_CLK_ENABLE ioctl(SYS, SYS_PERIPH_CLK_ENABLE, SYS_PWMB_CLK | SYS_PWMA_CLK); This code enables clocks to the PWM A and PWM B peripheral modules. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-173...
Page 292 Range Issues: None. Special Issues: None. Design/Implementation: The SYS_PERIPH_CLK_DISABLE command is implemented as a macro. Example 5-113. SYS_PERIPH_CLK_DISABLE ioctl(SYS, SYS_PERIPH_CLK_DISABLE, SYS_ADCA_CLK | SYS_ADCB_CLK); This code disables clocks to the ADC A and ADC B peripheral modules. 5-174 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 293 Range Issues: See the User’s Manual for the details. Special Issues: None. Design/Implementation: The SYS_WRITE_IO_SHORT_ADDR_LOCATION_REG command is implemented as a macro. Example 5-114. SYS_WRITE_IO_SHORT_ADDR_LOCATION_REG ioctl(SYS, SYS_WRITE_IO_SHORT_ADDR_LOCATION_REG, 0x11111111); This code writes 0x11111111 to the I/O Short Address Location Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-175...
Page 294 Returns: content of the I/O Short Address Location Register as UWord32. Range Issues: None. Special Issues: None. Design/Implementation: The SYS_READ_IO_SHORT_ADDR_LOCATION_REG command is implemented as a macro. Example 5-115. SYS_READ_IO_SHORT_ADDR_LOCATION_REG UWord32 tmp = ioctl(SYS, SYS_READ_IO_SHORT_ADDR_LOCATION_REG, NULL); This code reads the I/O Short Address Location Register. 5-176 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 295 (MC56F80xx) Design/Implementation: The SYS_ENABLE_IN_STOP command is implemented as a macro. Example 5-116. SYS_ENABLE_IN_STOP ioctl(SYS, SYS_ENABLE_IN_STOP, SYS_T0_MOD | SYS_SCI_MOD); This code enables the Timer 0 and the SCI to run during the processor stop mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-177...
Page 296 Special Issues: This command is implemented only on devices with “run-in-stop” feature (MC56F80xx) Design/Implementation: The SYS_DISABLE_IN_STOP command is implemented as a macro. Example 5-117. SYS_DISABLE_IN_STOP ioctl(SYS, SYS_DISABLE_IN_STOP, SYS_SCI_MOD); This code configures the SCI peripheral clock to be stopped during the processor stop mode. 5-178 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 297 Description: The SYS_SET_isig_SOURCE ioctl command establishes internal routing of the selected signals. The signal is identified in the command name as “isig”. The source for the signal is selected by a proper parameter value. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-179...
Page 298 Special Issues: This commands are applicable only on MC56F802x/3x and MC56F800x.. Design/Implementation: The SYS_SET_isig_SOURCE command is implemented as a macro. Example 5-118. SYS_SET_isig_SOURCE ioctl(SYS, SYS_SET_FAULT1_SOURCE, SYS_FAULT1SRC_COUTA_A); This code selects that FAULT1 signal is sourced from the Analog Comparator A (CMP_A) asynchronous output. 5-180 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 299 SYS_SET_A6PAD_FUNCTION SYS_SET_A5PAD_FUNCTION SYS_SET_A4PAD_FUNCTION SYS_SET_B11PAD_FUNCTION SYS_SET_B10PAD_FUNCTION SYS_SET_B9PAD_FUNCTION SYS_SET_B8PAD_FUNCTION SYS_SET_B7PAD_FUNCTION SYS_SET_B6PAD_FUNCTION SYS_SET_B5PAD_FUNCTION SYS_SET_B4PAD_FUNCTION SYS_SET_B3PAD_FUNCTION SYS_SET_B2PAD_FUNCTION SYS_SET_B1PAD_FUNCTION SYS_SET_B0PAD_FUNCTION SYS_SET_C12PAD_FUNCTION SYS_SET_C8PAD_FUNCTION SYS_SET_D5PAD_FUNCTION On MC56F800x: SYS_SET_A6PAD_FUNCTION SYS_SET_A5PAD_FUNCTION SYS_SET_A4PAD_FUNCTION SYS_SET_A3PAD_FUNCTION SYS_SET_B7PAD_FUNCTION SYS_SET_B6PAD_FUNCTION SYS_SET_B5PAD_FUNCTION SYS_SET_B4PAD_FUNCTION SYS_SET_B3PAD_FUNCTION SYS_SET_B2PAD_FUNCTION SYS_SET_B1PAD_FUNCTION SYS_SET_B0PAD_FUNCTION SYS_SET_C6PAD_FUNCTION SYS_SET_C0PAD_FUNCTION FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-181...
Page 300 Special Issues: This commands are applicable only on MC56F802x/3x and MC56F800x.. Design/Implementation: The SYS_SET_pad_FUNCTION command is implemented as a macro. Example 5-119. SYS_SET_pad_FUNCTION ioctl(SYS, SYS_SET_B4PAD_FUNCTION, SYS_B4PAD_CLKO); This code selects that CLKOUT signal will be available as a peripheral function of the GPIO_B4 pin. 5-182 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 301 Special Issues: This command is implemented on devices only. MC56F80xx Design/Implementation: The SYS_HS_CLOCK_ENABLE command is implemented as a macro. Example 5-120. SYS_HS_CLOCK_ENABLE ioctl(SYS, SYS_HS_CLOCK_ENABLE, SYS_HS_PWM); This code enables the PWM clock to be sourced from HS_PERF clock. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-183...
Page 302 Special Issues: This command is implemented on devices only. MC56F80xx Design/Implementation: The SYS_HS_CLOCK_DISABLE command is implemented as a macro. Example 5-121. SYS_HS_CLOCK_DISABLE ioctl(SYS, SYS_HS_CLOCK_DISABLE, SYS_HS_PWM); This code reverts the PWM clock to be sourced from original peripheral clock again. 5-184 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 303 PLL, and putting the oscillator to stand-by mode). Design/Implementation: The SYS_SET_POWER_MODE command is implemented as a macro. Example 5-122. SYS_SET_POWER_MODE ... /* reduced power mode preparation */ ioctl(SYS, SYS_SET_POWER_MODE, SYS_REDUCED_POWER); This code finishes the sequence to enter the reduced-power (standby) mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-185...
Page 304 Design/Implementation: The SYS_GET_POWER_MODE command is implemented as a macro. Example 5-123. SYS_GET_POWER_MODE if(ioctl(SYS, SYS_GET_POWER_MODE, NULL) & SYS_POWER_MODE_PERMANENT)) /* power mode is set permanently until reset */ This code tests whether the power mode is write-protected. 5-186 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 305 Design/Implementation: The SYS_WPROTECT_CLOCK_SETTINGS command is implemented as a macro. Example 5-124. SYS_WPROTECT_CLOCK_SETTINGS ioctl(SYS, SYS_WPROTECT_CLOCK_SETTINGS, SYS_ENABLE_PERMANENT); This code write-protects the clock settings. It will not be possible to disable this protection until the next reset occurs. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-187...
Page 306 SYS_WPROTECT_SIGNALS_ROUTING command implemented as a macro. Example 5-125. SYS_WPROTECT_SIGNALS_ROUTING ioctl(SYS, SYS_WPROTECT_SIGNALS_ROUTING, SYS_DISABLE_PERMANENT); This code disables write-protection of the signal settings. It will not be possible to enable this protection until the next reset occurs. 5-188 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 307 /* clear interrupt flags */ ioctl(LVI, LVI_CLEAR_LOW_VOLTAGE_INT, LVI_27V_LEVEL); else /* supply voltage is OK (above 2.7 V) */ This code tests if the supply voltage dropped under 2.7 V any time after it was previously tested. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-189...
Page 308 /* clear interrupt flags */ ioctl(LVI, LVI_CLEAR_LOW_VOLTAGE_INT, LVI_27V_LEVEL); else /* supply voltage is OK (above 2.7 V) */ This code tests if the supply voltage dropped under 2.7 V any time after it was previously tested. 5-190 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 309 Design/Implementation: The LVI_CLEAR_LOW_VOLTAGE_INT command is implemented as a macro. Example 5-128. LVI_CLEAR_LOW_VOLTAGE_INT ioctl(LVI, LVI_CLEAR_LOW_VOLTAGE_INT, LVI_22V_LEVEL | LVI_27V_LEVEL); This code clears both low voltage interrupt flags. This command can be used for example in the LVI interrupt service routine. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-191...
Page 310 Special Issues: This commands are applicable only on MC56F83xx, MC56F801x and MC56F802x/3x. Design/Implementation: The LVI_INT_ENABLE command is implemented as a macro. Example 5-129. LVI_INT_ENABLE ioctl(LVI, LVI_INT_ENABLE, LVI_22V_LEVEL | LVI_27V_LEVEL); This code enables low voltage interrupts for both 2.2 V and 2.7 V levels. 5-192 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 311 Special Issues: This commands are applicable only on MC56F83xx, MC56F801x and MC56F802x/3x. Design/Implementation: The LVI_INT_DISABLE command is implemented as a macro. Example 5-130. LVI_INT_DISABLE ioctl(LVI, LVI_INT_DISABLE, LVI_22V_LEVEL | LVI_27V_LEVEL); This code disables low voltage interrupts for both voltage levels. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-193...
Page 312 Design/Implementation: The LVI_INT_SELECT command is implemented as a macro. Example 5-131. LVI_INT_SELECT ioctl(LVI, LVI_INT_SELECT, LVI_27V_LEVEL); This code enables the low voltage interrupt for 2.7V level and disables the low voltage interrupt for 2.2V level. 5-194 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 313 Range Issues: None. Special Issues: None. Design/Implementation: The SEMI_SET_DRIVE_BUS command is implemented as a macro. Example 5-132. SEMI_SET_DRIVE_BUS ioctl(SEMI, SEMI_SET_DRIVE_BUS, SEMI_DRIVEN); This code sets the external bus to be driven even when not accessed. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-195...
Page 314 Design/Implementation: The SEMI_WRITE_BASEREGn command is implemented as a macro. Example 5-133. SEMI_WRITE_BASEREGn ioctl(SEMI, SEMI_WRITE_BASEREG3, 0x100 | SEMI_CSBAR_BLKSZ_64K); This code selects the Chip Select #3 to be active for the 64K memory block starting at address 0x10000. 5-196 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 315 Example 5-134. SEMI_WRITE_OPTIONREGn ioctl(SEMI, SEMI_WRITE_OPTIONREG3, SEMI_CSOR_BYTEEN_BOTH | SEMI_CSOR_RW_RO | SEMI_CSOR_PSDS_PSONLY | 0xA); This code selects the memory bank identified by the Chip Select #3 to operate as 16bit read-only program memory with 10 wait states. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-197...
Page 316 Range Issues: None. Special Issues: None. Design/Implementation: The SEMI_WRITE_CONTROLREG command is implemented as a macro. Example 5-135. SEMI_WRITE_CONTROLREG ioctl(SEMI, SEMI_WRITE_CONTROLREG, 0x8000); This code writes sets the DRV bit of the SEMI Bus Control Register. 5-198 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 317 Range Issues: None. Special Issues: None. Design/Implementation: The SEMI_READ_BASEREGn command is implemented as a macro. Example 5-136. SEMI_READ_BASEREGn UWord16 br3 = ioctl(SEMI, SEMI_READ_BASEREG3, NULL); This code reads the SEMI Base Register for memory bank #3. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-199...
Page 318 Range Issues: None. Special Issues: None. Design/Implementation: The SEMI_READ_OPTIONREGn command is implemented as a macro. Example 5-137. SEMI_READ_OPTIONREGn UWord16 or3 = ioctl(SEMI, SEMI_READ_OPTIONREG3, NULL); This code reads the SEMI Option Register for memory bank #3. 5-200 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 319 Returns: content of the SEMI Bus Control Register as UWord16. Range Issues: None. Special Issues: None. Design/Implementation: The SEMI_READ_CONTROLREG command is implemented as a macro. Example 5-138. SEMI_READ_CONTROLREG UWord16 bcr = ioctl(SEMI, SEMI_READ_CONTROLREG, 0x8000); This code reads the SEMI Bus Control Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-201...
Page 320: Sys Driver Application
SYS and COP Drivers (Section 5.4). Example 5-139. SYS Driver Application - appconfig.h /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2007 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * File Name: appconfig.h...
Page 321 Minimal Delay before other CS access: 3 #define SEMI_CSBAR0_INIT 0x0005 #define SEMI_CSBAR1_INIT 0x0005 #define SEMI_CSBAR2_INIT 0x0005 #define SEMI_CSOR0_INIT 0x1FC3 #define SEMI_CSOR1_INIT 0x1BA3 #define SEMI_CSOR2_INIT 0x1DA3 INTC Configuration -------------------------------------------- All maskable interrupts disabled: No IRQ A trigger mode: Low-level sensitive FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-203...
Page 322 Pin 10: Function: ISB0 , PullUp: Enable , Pin 11: Function: ISB1 , PullUp: Enable , Pin 12: Function: ISB2 , PullUp: Enable , #define GPIO_D_DDR_INIT 0x00C0 #define GPIO_D_PER_INIT 0x1F01 End of autogenerated code ********************************************************************** ..*/ #endif 5-204 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 323 Example 5-140. SYS Driver Application - main.c /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2007 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * FILE NAME: main.c * DESCRIPTION: Demonstration application how to use SYS module...
Page 324 /* if Vcc drops below Power-up level (1.8V) then recover will occur by RESET */ ioctl(OCCS, OCCS_SET_ZCLOCK_SOURCE, OCCS_POSTSCALER_OUTPUT); /* power outputs should be put to previous state */ /* and also peripherals should be set to state for normal operation */ 5-206 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 325 GPIO_INIT, NULL); #endif #ifdef GPIO_B ioctl(GPIO_B, GPIO_INIT, NULL); #endif #ifdef GPIO_C ioctl(GPIO_C, GPIO_INIT, NULL); #endif #ifdef GPIO_D ioctl(GPIO_D, GPIO_INIT, NULL); #endif #ifdef GPIO_E ioctl(GPIO_E, GPIO_INIT, NULL); #endif #ifdef GPIO_F ioctl(GPIO_F, GPIO_INIT, NULL); #endif FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-207...
Page 326 5-208 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 327: Pmc Driver
The following header files are needed in order to use the PMC device driver: Required Header File(s): #include "qs.h" #include "pmc.h" The following information may be found in the header file pmc.h. Public Data Structure(s): None FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-209...
Page 328: Configuration Items
PMC module identifier. Use PMC. Commands found in pmc.h which are used to modify the PMC module status and control registers. See Table 5-156. param, pParam in, inout Used to pass the relevant data to ioctl function call. 5-210 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 329 PMC_SET_BANDGAP_ PMC_ENABLE / None Enables or disables an internal BUFFER PMC_DISABLE buffer for bandgap bandgap voltage reference. PMC_SET_LOW_VOLTAGE_ NULL None Enables low voltage detector. DETECTOR_ENABLE PMC_SET_LOW_VOLTAGE_ NULL None Disables low voltage detector. DETECTOR_DISABLE FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-211...
Page 330: Detailed Api Specification
Ttim Bits the factory trimvalue which is stored in procesor mem- ory. 5.6.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the usage of the ioctl commands. 5-212 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 331 Example 5-141. PMC_INIT ioctl(PMC, PMC_INIT, NULL); This code initializes the PMC modules by the values defined in appconfig.h. The appconfig.h file can be edited manually or generated by the Graphical Configuration Tool. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-213...
Page 332 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PMC_CLEAR_FLAGS command is implemented as a macro. Example 5-142. PMC_CLEAR_FLAGS ioctl(PMC, PMC_CLEAR_FLAGS, PMC_FLAG_LOW_VOLT | PMC_FLAG_RESET); This code clears the Low Voltage interrupt flag and the Power On Reset status flag. 5-214 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 333 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PMC_TEST_FLAGS command is implemented as a macro. Example 5-143. PMC_TEST_FLAGS ioctl(PMC, PMC_TEST_FLAGS, PMC_FLAG_LOW_VOLT | PMC_FLAG_RESET); This code clears the Low Voltage interrupt flag and the Power On Reset status flag. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-215...
Page 334 Status and Control Register. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The PMC_SET_INT_ENABLE ioctl command is implemented as a macro. Example 5-144. PMC_SET_INT_ENABLE ioctl(PMC, PMC_SET_INT_ENABLE, PMC_INT_LOW_VOLT); This code enables the Low Voltage Detect interrupt. 5-216 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 335 Range Issues: None. Special Issues: This command is applicable only on MC56F800x.. Design/Implementation: The PMC_SET_INT_DISABLE ioctl command is implemented as a macro. Example 5-145. PMC_SET_INT_DISABLE ioctl(PMC, PMC_SET_INT_DISABLE, PMC_INT_OUT_REG); This code disables the Out of Regulation interrupt. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-217...
Page 336 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PMC_SET_LOW_VOLTAGE_RESET command is implemented as a macro. Example 5-146. PMC_SET_LOW_VOLTAGE_RESET ioctl(PMC, PMC_SET_LOW_VOLTAGE_RESET, PMC_ENABLE) This code enables the Low Voltage Hardware Reset. 5-218 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 337 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PMC_SET_PARTIAL_POWER_DOWN command is implemented as a macro. Example 5-147. PMC_SET_PARTIAL_POWER_DOWN ioctl(PMC, PMC_SET_PARTIAL_POWER_DOWN, PMC_DISABLE) This code disables to enter the DSP controller into the Partial Power Down mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-219...
Page 338 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: PMC_SET_LOW_POWER_REGULATOR_WAIT_MODES command is implemented as a macro. Example 5-148. PMC_SET_LOW_POWER_REGULATOR_WAIT_MODES ioctl(PMC, PMC_SET_LOW_POWER_REGULATOR_WAIT_MODES, PMC_ENTER) This code requests the low-power run and the low-power wait modes. 5-220 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 339 Design/Implementation: The PMC_TEST_LOW_POWER_REGULATOR_STATUS command is implemented as a macro. Example 5-149. PMC_TEST_LOW_POWER_REGULATOR_STATUS if (ioctl(PMC, PMC_TEST_LOW_POWER_REGULATOR_STATUS, NULL)) This code tests, if the voltage regulator entered into standby for the low-power run or low-power wait mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-221...
Page 340 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PMC_SET_LOW_POWER_WAKEUP_INTERRUPT command is implemented as a macro. Example 5-150. PMC_SET_LOW_POWER_WAKEUP_INTERRUPT ioctl(PMC, PMC_SET_LOW_POWER_WAKEUP_INTERRUPT, PMC_DISABLE) This code disables the voltage regulator exits standby when any activate MCU interrupt occures. 5-222 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 341 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PMC_SET_BANDGAP_BUFFER command is implemented as a macro. Example 5-151. PMC_SET_BANDGAP_BUFFER ioctl(PMC, PMC_SET_BANDGAP_BUFFER, PMC_ENABLE) This code enables the buffer for the bandgap voltage reference. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-223...
Page 342 This command writes into the Low-Voltage Detect Enable (LVDE) bit of the PMC Status and Control Register. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: PMC_SET_LOW_VOLTAGE_DETECTOR_ENABLE ioctl command is implemented as a macro. Example 5-152. PMC_SET_LOW_VOLTAGE_DETECTOR_ENABLE ioctl(PMC, PMC_SET_LOW_VOLTAGE_DETECTOR_ENABLE, NULL); This code enables the Low-Voltage Detector. 5-224 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 343 This command writes into the Low-Voltage Detect Enable (LVDE) bit of the PMC Status and Control Register. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: PMC_SET_LOW_VOLTAGE_DETECTOR_DISABLE ioctl command is implemented as a macro. Example 5-153. PMC_SET_LOW_VOLTAGE_DETECTOR_DISABLE ioctl(PMC, PMC_SET_LOW_VOLTAGE_DETECTOR_DISABLE, NULL); This code disables the Low-Voltage Detector. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-225...
Page 344 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PMC_SET_LOW_VOLTAGE_DETECTOR_LEVEL command is implemented as a macro. Example 5-154. PMC_SET_LOW_VOLTAGE_DETECTOR_LEVEL ioctl(PMC, PMC_SET_LOW_VOLTAGE_DETECTOR_LEVEL, PMC_LOW_VOLT_SEL_VLDL) This code selects the Low-Voltage detector trip point to the VLDL value (1.86V). 5-226 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 345 Design/Implementation: The PMC_SET_WPROTECTION command is implemented as a macro. Example 5-155. PMC_SET_WPROTECTION ioctl(PMC, PMC_SET_WPROTECTION, SYS_DISABLE_PERMANENT); This code disables write-protection of the PMC settings. It will not be possible to enable this protection until the next reset occurs. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-227...
Page 346 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PMC_SET_1KHZ_OSC command is implemented as a macro. Example 5-156. PMC_SET_1KHZ_OSC ioctl(PMC, PMC_SET_1KHZ_OSC, PMC_DISABLE) This code disables the 1kHz low power oscillator. 5-228 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 347 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PMC_SET_1KHZ_OSC_TRIM command is implemented as a macro. Example 5-157. PMC_SET_1KHZ_OSC_TRIM ioctl(PMC, PMC_SET_1KHZ_OSC_TRIM, PMC_1KHZ_TRIM_CENTER) This code disables the 1kHz oscillator adjust settings. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-229...
Page 348 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: PMC_SET_1KHZ_OSC_FACTORY_TRIM command implemented as a macro. Example 5-158. PMC_SET_1KHZ_OSC_FACTORY_TRIM ioctl(PMC, PMC_SET_1KHZ_OSC_FACTORY_TRIM, NULL) This code adjusts the raw frequency to 1kHz by the factory trim value stored in the processor flash memory. 5-230 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 349 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PMC_SET_LVD_TRIM command is implemented as a macro. Example 5-159. PMC_SET_LVD_TRIM ioctl(PMC, PMC_SET_LVD_TRIM, PMC_LVD_TRIM_p1) This code sets trim increment to +1. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-231...
Page 350 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PMC_SET_LVD_FACTORY_TRIM command is implemented as a macro. Example 5-160. PMC_SET_LVD_FACTORY_TRIM ioctl(PMC, PMC_SET_LVD_FACTORY_TRIM, NULL) This code sets the Trim Increment by the factory trim value stored in the processor flash memory. 5-232 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 351: Pmc Driver Applications
Otehr LEDS indicating the state of application: - GREEN LED -> flashing while in the main loop - YELLOW LED -> execution stuck in the LVI ISR - RED LED -> toggle led every execution LVI ISR FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-233...
Page 352 5-234 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 353: Flexcan Driver
Global network time, synchronized by a specific message • Maskable interrupts • Low power Sleep mode, with programmable Wake Up on bus activity The following sections describe the FlexCAN driver software which provides the low level API to the FlexCAN hardware. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-235...
Page 354: Quick Reference
The PROPSEG field of the FCCTL0 contains the length of the PROP_SEG part in tq units 5-236 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 355: Flexcan Message Identifiers
“dummy” Substitute Remote Request (SRR) bit in extended 29 bit ID messages. The SRR is always transmitted as one. For extended ID messages, 18 ID bits added and a new RTR bit are appended after IDE bit. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-237...
Page 356 (plus the MSB to identify extended identifiers) and use the conversion functions described above implicitly (e.g. FCAN_SET_RXGMASK or FCANMB_SET_ID commands ). The ioctl commands 1. An exception is the FCANMB_GET_ID command, which is implemented as a optimized assembly function in fcan.c . 5-238 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 357: Api Definition
Receive Data Global Mask Regis- Reset value used. ters (high and low part). FCAN_RX14MASKL_INIT UWord16 Initial value of the FlexCAN Register not initialized. FCAN_RX14MASKH_INIT Receive Data Buffer 14 Mask Reset value used. Registers (high and low part). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-239...
Page 358: Api Specification
Arguments: Table 5-179. FlexCAN Driver Arguments - ioctl pModuleBase FlexCAN module identifier. Use FCAN and FCAN2. Note that FCAN2 is available only on 56F8367. Command names found in fcan.h. See Table 5-180. 5-240 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 359 FCAN_INT_ENABLE FCAN_BUSOFF_INT | None Enable interrupts. FCAN_ERROR_INT | FCAN_WAKEUP_INT FCAN_INT_DISABLE FCAN_BUSOFF_INT | None Disable interrupts. FCAN_ERROR_INT | FCAN_WAKEUP_INT FCAN_LOOPBACK_MODE FCAN_ENABLE/ None Enable/disable test loopback FCAN_DISABLE mode. FCAN_TIMER_SYNC_MODE FCAN_ENABLE/ None Enable/disable Timer Sync FCAN_DISABLE mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-241...
Page 360 Beware that the error bits are self-cleared after read. FCAN_SET_MAXMB UWord16 number 0 .. 15 None Set maximum number of MB used (pParam+1). FCAN_CLEAR_BOFF_INT NULL None Clear BusOff interrupt status. FCAN_CLEAR_ERR_INT NULL None Clear Error interrupt status. 5-242 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 361 FCAN_SET_RX15MASK 32bit mask value None Set MB15 RX mask, the FCAN_SET_RX15MASK_V when MSB (bit31) is set, the mask is passed mask is rebuilt to suit treated as for Extended ID the register bit-scheme. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-243...
Page 362 Read RX error counter. FCAN_GET_TX_ERR_COUNT NULL UWord16 Read TX error counter. FCAN_GET_MB_MODULE MB index 0..15 FCAN_MB* Get pointer to MB module. The returned value can be used in subsequent ioctl calls using the FCANMB_xxx commands. 5-244 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 363 Write the raw ID value to the given MB. FCANMB_SET_RTR FCAN_ON/ None Set/Clear RTR bits in given FCAN_OFF MB. Can be used after the ID is written to MB. FCANMB_SET_LEN UWord16 number 0-8 None Set length field of the MB. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-245...
Page 364: Detailed Api Specification
FCAN_MB0...FCAN_MB15 (and FCAN2_MB0...FCAN2_MB15 on 56F8367)or the pointer value returned by the FCAN_GET_MB_MODULE command. 5.7.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the usage of the ioctl commands. 5-246 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 365 0x0000 for normal operation. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_INIT ioctl command is implemented as a function call. Example 5-161. FCAN_INIT ioctl(FCAN, FCAN_INIT, NULL); This code calls the driver initialization function. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-247...
Page 366 This command writes directly into the STOP bit of the FCMCR register. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_STOP_MODE ioctl command is implemented as a macro. Example 5-162. FCAN_STOP_MODE ioctl(FCAN, FCAN_STOP_MODE, FCAN_ENABLE); This code enters the low-power sleep mode. 5-248 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 367 Design/Implementation: The FCAN_DEBUG_MODE ioctl command is implemented as a macro. Example 5-163. FCAN_DEBUG_MODE ioctl(FCAN, FCAN_DEBUG_MODE, FCAN_ENABLE); while(! ioctl(FCAN, FCAN_TEST_DEBUG, NULL)) ; /* wait for debug mode */ This code enters the debug mode and waits until it is acknowledged. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-249...
Page 368 Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_SOFT_RESET ioctl command is implemented as a macro. Example 5-164. FCAN_SOFT_RESET ioctl(FCAN, FCAN_SOFT_RESET, NULL); This code activates the soft reset state of the FlexCAN module. 5-250 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 369 Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_SELF_WAKEUP_MODE ioctl command is implemented as a macro. Example 5-165. FCAN_SELF_WAKEUP_MODE ioctl(FCAN, FCAN_SELF_WAKEUP_MODE, FCAN_ENABLE); This code enables the self-wake up of the FlexCAN module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-251...
Page 370 Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_AUTO_PWRSAVE_MODE ioctl command is implemented as a macro. Example 5-166. FCAN_AUTO_PWRSAVE_MODE ioctl(FCAN, FCAN_AUTO_PWRSAVE_MODE, FCAN_ENABLE); This code enables the auto power save feature of the FlexCAN module. 5-252 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 371 Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_TEST_READY ioctl command is implemented as a macro. Example 5-167. FCAN_TEST_READY if ( ioctl(FCAN, FCAN_TEST_READY, NULL) ) This code test whether the FlexCAN module is ready. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-253...
Page 372 Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_TEST_DEBUG ioctl command is implemented as a macro. Example 5-168. FCAN_TEST_DEBUG if( ioctl(FCAN, FCAN_TEST_DEBUG, NULL) ) This command tests whether the module is in debug mode. 5-254 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 373 Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_TEST_STOP ioctl command is implemented as a macro. Example 5-169. FCAN_TEST_STOP if( ioctl(FCAN, FCAN_TEST_STOP, NULL) ) This command tests whether the module is in stop mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-255...
Page 374 Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_INT_ENABLE ioctl command is implemented as a macro. Example 5-170. FCAN_INT_ENABLE ioctl(FCAN, FCAN_INT_ENABLE, FCAN_ERROR_INT); This code enables the error interrupt to be signalled to the MCU core. 5-256 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 375 Special Issues: None. Design/Implementation: The FCAN_INT_DISABLE ioctl command is implemented as a macro. Example 5-171. FCAN_INT_DISABLE ioctl(FCAN, FCAN_INT_DISABLE, FCAN_ERROR_INT | FCAN_WAKEUP_INT); This code disables the wake-up and error interrupts to be signalled to the MCU core. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-257...
Page 376 Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_LOOPBACK_MODE ioctl command is implemented as a macro. Example 5-172. FCAN_LOOPBACK_MODE ioctl(FCAN, FCAN_LOOPBACK_MODE, FCAN_DISABLE); This code disables the internal loopback mode of the FlexCAN module. 5-258 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 377 Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_TIMER_SYNC_MODE ioctl command is implemented as a macro. Example 5-173. FCAN_TIMER_SYNC_MODE ioctl(FCAN, FCAN_TIMER_SYNC_MODE, FCAN_DISABLE); This code disables the timer synchronization feature of the FlexCAN module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-259...
Page 378 Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_LISTEN_ONLY_MODE ioctl command is implemented as a macro. Example 5-174. FCAN_LISTEN_ONLY_MODE ioctl(FCAN, FCAN_LISTEN_ONLY_MODE, FCAN_DISABLE); This code disables the listen-only mode of the FlexCAN module. 5-260 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 379 Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_SET_TX_FIRST_SCHEME ioctl command is implemented as a macro. Example 5-175. FCAN_SET_TX_FIRST_SCHEME ioctl(FCAN, FCAN_SET_TX_FIRST_SCHEME, FCAN_LOWEST_ID); This code sets enables the lowest ID frames to be transmitted first. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-261...
Page 380 This command directly accesses the SAMP bit of the FCCTL0 register. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_SET_SAMPLING ioctl command is implemented as a macro. Example 5-176. FCAN_SET_SAMPLING ioctl(FCAN, FCAN_SET_SAMPLING, FCAN_3SAMPS_PER_BIT); This code selects the three-samples-per-bit sampling mode. 5-262 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 381 This code selects the clock divisor to 8. In the case the 8 MHz external oscillator is attached to the MCU, the serial clock will run at 1 MHz and one time quantum will be equal to 1 us. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 382 FCCTL0 and FCCTL1 registers. Section 5.7.2.1 contains more information about this topic. Design/Implementation: The FCAN_SET_RJW ioctl command is implemented as a macro. Example 5-178. FCAN_SET_RJW ioctl(FCAN, FCAN_SET_RJW, FCAN_RJW_1); This code sets the Re-synchronization Jump Width parameter to 1. 5-264 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 383 FCCTL0 and FCCTL1 registers. Section 5.7.2.1 contains more information about this topic. Design/Implementation: The FCAN_SET_PROP_SEG ioctl command is implemented as a macro. Example 5-179. FCAN_SET_PROP_SEG ioctl(FCAN, FCAN_SET_PROP_SEG, FCAN_PROPSEG_4); This code sets the propagation segment to 4. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-265...
Page 384 FCCTL0 and FCCTL1 registers. Section 5.7.2.1 contains more information about this topic. Design/Implementation: The FCAN_SET_PHASE_SEG1 ioctl command is implemented as a macro. Example 5-180. FCAN_SET_PHASE_SEG1, FCAN_SET_PHASE_SEG2 ioctl(FCAN, FCAN_SET_PHASE_SEG1, FCAN_PSEG_4); This code sets the Phase Buffer Segment 1 to 4. 5-266 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 385 Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_UNLOCK_ALL_MB ioctl command is implemented as a macro. Example 5-181. FCAN_UNLOCK_ALL_MB ioctl (FCAN, FCAN_UNLOCK_ALL_MB, NULL); This code unlocks any MB currently locked. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-267...
Page 386 Range Issues: Numerical values 0 to 15 are allowed only. Special Issues: None. Design/Implementation: The FCAN_SET_MAXMB ioctl command is implemented as a macro. Example 5-182. FCAN_SET_MAXMB ioctl(FCAN, FCAN_SET_MAXMB, 5); This code sets the number of MB in use to 6. 5-268 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 387 Special Issues: Some of the bits in the FCSTATUS register are self-cleared after read. Design/Implementation: FCAN_READ_ERR_AND_STATUS ioctl command implemented as a macro. Example 5-183. FCAN_READ_ERR_AND_STATUS UWord16 status = ioctl(FCAN, FCAN_READ_ERR_AND_STATUS, NULL); if ( status & FCAN_STATUS_FCS_BUSOFF ) This code tests the bus-off condition. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-269...
Page 388 Special Issues: The Error and Status Register must be read before clearing the flag. Design/Implementation: The FCAN_CLEAR_BOFF_INT ioctl command is implemented as a macro. Example 5-184. FCAN_CLEAR_BOFF_INT UWord16 status = ioctl(FCAN, FCAN_READ_ERR_AND_STATUS, NULL); ioctl(FCAN, FCAN_CLEAR_BOFF_INT, NULL); This code clears the “Bus Off” interrupt flag. 5-270 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 389 Special Issues: The Error and Status Register must be read before clearing the flag. Design/Implementation: The FCAN_CLEAR_ERR_INT ioctl command is implemented as a macro. Example 5-185. FCAN_CLEAR_ERR_INT UWord16 status = ioctl(FCAN, FCAN_READ_ERR_AND_STATUS, NULL); ioctl(FCAN, FCAN_CLEAR_ERR_INT, NULL); This code clears the Error interrupt flag. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-271...
Page 390 Special Issues: The Error and Status Register must be read before clearing the flag. Design/Implementation: The FCAN_CLEAR_WAKE_INT ioctl command is implemented as a macro. Example 5-186. FCAN_CLEAR_WAKE_INT UWord16 status = ioctl(FCAN, FCAN_READ_ERR_AND_STATUS, NULL); ioctl(FCAN, FCAN_CLEAR_WAKE_INT, NULL); This code clears the Wake Up interrupt flag. 5-272 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 391 Design/Implementation: The FCAN_CLEAR_INT ioctl command is implemented as a macro. Example 5-187. FCAN_CLEAR_INT UWord16 status = ioctl(FCAN, FCAN_READ_ERR_AND_STATUS, NULL); ioctl(FCAN, FCAN_CLEAR_INT, FCAN_STATUS_BOFF_INT | FCAN_STATUS_ERR_INT); This code clears the “Bus Off” and Error interrupt flags. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-273...
Page 392 Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_MBINT_ENABLE ioctl command is implemented as a macro. Example 5-188. FCAN_MBINT_ENABLE ioctl(FCAN, FCAN_MBINT_ENABLE, FCAN_MBINT_0 | FCAN_MBINT_1); This code enables interrupts for Message Buffers 0 and 1. 5-274 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 393 Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_MBINT_DISABLE ioctl command is implemented as a macro. Example 5-189. FCAN_MBINT_DISABLE ioctl(FCAN, FCAN_MBINT_DISABLE, FCAN_MBINT_15 | FCAN_MBINT_0); This code disables interrupts for Message Buffers 0 and 15. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-275...
Page 394 UWord16 mbInt = ioctl(FCAN, FCAN_READ_MBINT_FLAGS, NULL); if(mbInt & FCAN_MBINT_3) This code reads and stores the list of Message Buffers for which the reception or transmission finished. The MB3 bit is then tested in the returned value. 5-276 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 395 UWord16 mbInt = ioctl(FCAN, FCAN_READ_MBINT_FLAGS, NULL); ... // process Message Buffers identified in mbInt ioctl(FCAN, FCAN_CLEAR_MBINT_FLAGS, 0xffff); This code first reads the interrupt sources, and then clears all the flags previously read as one. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-277...
Page 396 Design/Implementation: The FCAN_SET_RXGMASK ioctl command is implemented as a macro. The FCAN_SET_RXGMASK_V ioctl command is implemented as a function call. Example 5-192. FCAN_SET_RXGMASK ioctl(FCAN, FCAN_SET_RXGMASK, 0xff); This code sets the global receiver mask to 0xff. 5-278 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 397 Special Issues: See FlexCAN documentation for the details about mask registers format. Design/Implementation: The FCAN_SET_RXGMASK_RAW ioctl command is implemented as a macro. Example 5-193. FCAN_SET_RXGMASK_RAW ioctl(FCAN, FCAN_SET_RXGMASK_RAW, 0xff << 21); This code sets the global receiver mask to 0xff. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-279...
Page 398 Both the FCAN_SET_RX14MASK_V and FCAN_SET_RX15MASK_V ioctl commands are implemented as a function call. Example 5-194. FCAN_SET_RX14MASK, FCAN_SET_RX15MASK ioctl(FCAN, FCAN_SET_RX14MASK, 0x0f); This code sets the receiver mask of Message Buffer 14 to 0x0f. 5-280 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 399 Special Issues: See FlexCAN documentation for the details about mask registers format. Design/Implementation: The FCAN_SET_RX14MASK_RAW and FCAN_SET_RX15MASK_RAW ioctl commands are implemented as a macro. Example 5-195. FCAN_SET_RX14MASK_RAW, FCAN_SET_RX15MASK_RAW ioctl(FCAN, FCAN_SET_RX14MASK_RAW, 0xff << 21); This code sets the receiver mask of Message Buffer 14 to 0xff. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-281...
Page 400 Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_GET_RX_ERR_COUNT ioctl command is implemented as a macro. Example 5-196. FCAN_GET_RX_ERR_COUNT UWord16 rxErr; rxErr = ioctl(FCAN, FCAN_GET_RX_ERR_COUNT, NULL); This code reads the value of FlexCAN RX error counter. 5-282 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 401 Range Issues: None. Special Issues: None. Design/Implementation: The FCAN_GET_TX_ERR_COUNT ioctl command is implemented as a macro. Example 5-197. FCAN_GET_TX_ERR_COUNT UWord16 txErr; txErr = ioctl(FCAN, FCAN_GET_TX_ERR_COUNT, NULL); This code reads the value of FlexCAN TX error counter. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-283...
Page 402 Range Issues: The ioctl parameter identifies the Message Buffer index. Valid range is 0...15. Special Issues: None. Design/Implementation: The FCAN_GET_MB_MODULE ioctl command is implemented as a macro. Example 5-198. FCAN_GET_MB_MODULE FCAN_MB* pmb; pmb = ioctl(FCAN, FCAN_GET_MB_MODULE, 5); This code retrieves pointer to Message Buffer module number 5. 5-284 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 403 Design/Implementation: The FCANMB_GET_ID ioctl command is implemented as a function call. The function does not change any registers except the function return value register. Example 5-199. FCANMB_GET_ID UWord32 id; id = ioctl(FCAN_MB5, FCANMB_GET_ID, NULL); This code retrieves frame Id of MB5. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-285...
Page 404 Range Issues: None. Special Issues: None. Design/Implementation: The FCANMB_GET_ID_RAW ioctl command is implemented as a macro. Example 5-200. FCANMB_GET_ID_RAW UWord32 id; id = ioctl(FCAN_MB5, FCANMB_GET_ID_RAW, NULL); This code retrieves raw frame Id of MB5. 5-286 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 405 FCAN_GET_MB_MODULE command. Special Issues: None. Design/Implementation: The FCANMB_GET_LEN ioctl command is implemented as a macro. Example 5-201. FCANMB_GET_LEN UWord16 len; len = ioctl(FCAN_MB5, FCANMB_GET_LEN, NULL); This code retrieves the length of the message in MB5. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-287...
Page 406 Design/Implementation: The FCANMB_GET_DATAPTR ioctl command is implemented as a macro. Example 5-202. FCANMB_GET_DATAPTR UWord16 len; UWord16* pdata len = ioctl(FCAN_MB5, FCANMB_GET_LEN, NULL); pdata = ioctl(FCAN_MB5, FCANMB_GET_DATAPTR, NULL); This code retrieves the length and pointer to data part of the frame in MB5. 5-288 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 407 UWord16 code = ioctl(FCAN_MB5, FCANMB_GET_CODE, NULL); if(code == FCAN_MB_CODE_RXFULL || code == FCAN_MB_CODE_RXOVERRUN) ... // read out the data ioctl(FCAN, FCAN_UNLOCK_ALL_MB, NULL); // unlock MB This code tests the status code of the MB5. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-289...
Page 408 Special Issues: None. Design/Implementation: The FCANMB_GET_TIMESTAMP ioctl command is implemented as a macro. Example 5-204. FCANMB_GET_TIMESTAMP UWord16 ts; ts = ioctl(FCAN_MB5, FCANMB_GET_TIMESTAMP, NULL); This code retrieves the time stamp of the message received in MB5. 5-290 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 409 Special Issues: None. Design/Implementation: The FCANMB_GET_TIMESTAMP8 ioctl command is implemented as a macro. Example 5-205. FCANMB_GET_TIMESTAMP8 UWord16 ts; ts = ioctl(FCAN_MB5, FCANMB_GET_TIMESTAMP8, NULL); This code retrieves the time stamp of the message received in MB5. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-291...
Page 410 Range Issues: The parameter contains the message id for which the following range apply: Standard identifiers (MSB=0) are limited to 11 bits so the valid range is 0...0x7ff. Extended identifiers (MSB=1) are limited to 29 bits and the valid range is 0x8000000... 0x9fffffff. 5-292 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 411 Design/Implementation: The FCANMB_SET_ID ioctl command is implemented as a macro. Example 5-206. FCANMB_SET_ID ioctl(FCAN_MB5, FCANMB_SET_ID, 0x123 | FCAN_ID_EXT | FCAN_ID_RTR); This code sets the message identifier of the MB5 to Extended ID 0x123. It also sets the RTR bit. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-293...
Page 412 This function call saves the contents of the CPU registers, so it can be called from interrupt service routines. Example 5-207. FCANMB_SET_ID_V UWord32 id = 0x123 | FCAN_ID_EXT; ioctl(FCAN_MB5, FCANMB_SET_ID_V, id); This code sets the message identifier of the MB5 to Extended ID 0x123. 5-294 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 413 Special Issues: None. Design/Implementation: The FCANMB_SET_ID_RAW ioctl command is implemented as a macro. Example 5-208. FCANMB_SET_ID_RAW ioctl(FCAN_MB5, FCANMB_SET_ID_RAW, 0x11 << 21); This code sets the message identifier of the MB5 to 0x11. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-295...
Page 414 Design/Implementation: The FCANMB_SET_RTR ioctl command is implemented as a macro. Example 5-209. FCANMB_SET_RTR ioctl(FCAN_MB5, FCANMB_SET_LEN, 0); ioctl(FCAN_MB5, FCANMB_SET_ID, 0x11); ioctl(FCAN_MB5, FCANMB_SET_RTR, FCAN_ON); This code prepares the transmission of the Remote Transmit Request of the id 0x11 from the MB5. 5-296 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 415 Design/Implementation: The FCANMB_SET_LEN ioctl command is implemented as a macro. Example 5-210. FCANMB_SET_LEN ioctl(FCAN_MB5, FCANMB_SET_LEN, 4); This code sets the message length of the MB5 to four. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-297...
Page 416 FCANMB_SET_CODE, FCAN_MB_CODE_TXVOID); pd = ioctl(FCAN_MB5, FCANMB_GET_DATAPTR, NULL); pd[0] = 0x1234; ioctl(FCAN_MB5, FCANMB_SET_LEN, 2); ioctl(FCAN_MB5, FCANMB_SET_ID, 0x12 | FCAN_ID_EXT); ioctl(FCAN_MB5, FCANMB_SET_CODE, FCAN_MB_CODE_TXONCE); This code transmits a two-byte message with extended identifier 0x12 from MB5. 5-298 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 417: Flexcan Driver Sample Application
3. The MB 10 is used to demonstrate RTR automatic responses (ID: 0x66) application found e.g. {DSP56800E_Quick_Start Source}\..sample_applications\MC56F8346EVM\fcan_demo directory and consists of the application project fcan_demo.mcp, source code for the application main.c and configuration file appconfig.h. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-299...
Page 418 Example 5-212. FlexCAN driver sample application appconfig.h /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * File Name: appconfig.h * Description: file for static configuration of the application...
Page 419 MB interrupts: MB0 : No , MB1 : No , MB2 : No , MB3 : No MB4 : No , MB5 : No , MB6 : No , MB7 : No MB8 : No , MB9 : No , MB10: No , MB11: No FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-301...
Page 420 #define FCAN_MCR_INIT 0x0400 #define FCAN_CTL0_INIT 0xC000 #define FCAN_CTL1_INIT 0x0B1B #define FCAN_RXGMASKL_INIT 0xFFFE #define FCAN_RXGMASKH_INIT 0xFFEF #define FCAN_RX14MASKL_INIT 0xFFFE #define FCAN_RX14MASKH_INIT 0xFFEF #define FCAN_RX15MASKL_INIT 0xFFFE #define FCAN_RX15MASKH_INIT 0xFFEF End of autogenerated code ********************************************************************** ..*/ #endif 5-302 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 421 Example 5-213. FlexCAN driver sample application main.c /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * FILE NAME: main.c * DESCRIPTION: FlexCAN low-level driver demo application 1.
Page 422 GPIO_TOGGLE_PIN, BIT_2); /* unlock MB */ ioctl(FCAN, FCAN_UNLOCK_ALL_MB, NULL); /* note that MB remains configured as RX with the original ID /* acknowledge any MB interrupt */ ioctl(FCAN, FCAN_CLEAR_MBINT_FLAGS, 0xffff); #pragma interrupt off 5-304 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 423 = 0xCCDD; pdata[2] = 0xEE00; /* endless loop */ while(1) /* transmit MB 5 (if ready) */ if(ioctl(FCAN_MB5, FCANMB_GET_CODE, NULL) == FCAN_MB_CODE_TXVOID) ioctl(FCAN_MB5, FCANMB_SET_CODE, FCAN_MB_CODE_TXONCE); /* wait a while */ for(i=0; i<100; i++) archDelay(0xffff); FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-305...
Page 424 5-306 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 425: Gpio Driver
0xF330 Port F (PortF_BASE) 0xF220 0xF340 0xF340 5.8.2.1 API Definition The following header files are needed in order to use the GPIO device driver: Required Header File(s): #include "qs.h" #include "gpio.h" Public Data Structure(s): FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-307...
Page 426: Configuration Items
GPIO_ x _DRIVE_INIT Drive Strength Register. MC56F800x only: UWord16 Represents contents of the GPIO GPIO_ x _IFE_INIT Input Filter Register. MC56F800x only: UWord16 Represents contents of the GPIO GPIO_ x _SLEW_INIT Slew Rate Register. 5-308 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 427: Api Specification
& intersection of items is allowed ( item1 & item2 & item3 ) Table 5-236. ioctl commands pParam Return Description GPIO_INIT None None Initializes selected GPIO port by data from configuration file (app- config.h). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-309...
Page 428 GPIO_CLEAR_PIN BIT_0 | BIT_1 | None Clears the selected GPIO pins ... | BIT_15 of the port. GPIO_TOGGLE_PIN BIT_0 | BIT_1 | None Toggles the selected GPIO pins ... | BIT_15 of the port. 5-310 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 429: Detailed Api Specification
Disables slew rate on selected GPIO_SET_LOW_SLEW_RATE_DISABLE ... | BIT_15 GPIO pins 5.8.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the ioctl commands usage. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-311...
Page 430 Section 5.8.2.2. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The GPIO_INIT ioctl command is implemented as a function call. Example 5-214. GPIO_INIT ioctl( GPIO_B, GPIO_INIT, NULL); This code initializes the GPIO Port B. 5-312 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 431 GPIO registers in appconfig.h, but only for those which are needed. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The GPIO_INIT_ALL ioctl command is implemented as a function call. Example 5-215. GPIO_INIT_ALL ioctl( GPIO, GPIO_INIT_ALL, NULL); This code initializes all GPIO Ports. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-313...
Page 432 Design/Implementation: The GPIO_SETAS_GPIO ioctl command is implemented as a macro. Example 5-216. GPIO_SETAS_GPIO ioctl( GPIO_B, GPIO_SETAS_GPIO, BIT_0 | BIT_1 | BIT_2); This code sets pins 0, 1 and 2 on Port B as GPIO pins. 5-314 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 433 Design/Implementation: The GPIO_SETAS_PERIPHERAL ioctl command is implemented as a macro. Example 5-217. GPIO_SETAS_PERIPHERAL ioctl( GPIO_B, GPIO_SETAS_PERIPHERAL, BIT_0 | BIT_1 | BIT_2); This code assigns pins 0, 1 and 2 on Port B to a peripheral. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-315...
Page 434 Design/Implementation: The GPIO_SETAS_INPUT ioctl command is implemented as a macro. Example 5-218. GPIO_SETAS_INPUT ioctl( GPIO_B, GPIO_SETAS_INPUT, BIT_0 | BIT_1 | BIT_2); This code sets pins 0, 1 and 2 on Port B as input pins. 5-316 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 435 Design/Implementation: The GPIO_SETAS_OUTPUT ioctl command is implemented as a macro. Example 5-219. GPIO_SETAS_OUTPUT ioctl( GPIO_B, GPIO_SETAS_OUTPUT, BIT_0 | BIT_1 | BIT_2); This code sets pins 0, 1 and 2 on Port B as output pins. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-317...
Page 436 Design/Implementation: The GPIO_INT_DISABLE ioctl command is implemented as a macro. Example 5-220. GPIO_INT_DISABLE ioctl( GPIO_B, GPIO_INT_DISABLE, BIT_1); This code disables the interrupt request generated by pin 1 on Port B. 5-318 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 437 Design/Implementation: The GPIO_INT_ENABLE ioctl command is implemented as a macro. Example 5-221. GPIO_INT_ENABLE ioctl( GPIO_B, GPIO_INT_ENABLE, BIT_1); This code enables an interrupt request generated by pin 1 on Port B. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-319...
Page 438 Design/Implementation: The GPIO_PULLUP_DISABLE ioctl command is implemented as a macro. Example 5-222. GPIO_PULLUP_DISABLE ioctl( GPIO_B, GPIO_PULLUP_DISABLE, BIT_0 | BIT_1 | BIT_2); This code disables pull-up on the pins 0, 1, 2 on Port B. 5-320 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 439 Design/Implementation: The GPIO_PULLUP_ENABLE ioctl command is implemented as a macro. Example 5-223. GPIO_PULLUP_ENABLE ioctl( GPIO_B, GPIO_PULLUP_ENABLE, BIT_0 | BIT_1 | BIT_2); This code enables pull-up on the pins 0, 1, 2 on Port B. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-321...
Page 440 MC56F83xx, MC56F801x and MC56F802x/3x. Design/Implementation: GPIO_CLEAR_SW_INT_PENDING ioctl command implemented as a macro. Example 5-224. GPIO_CLEAR_SW_INT_PENDING ioctl( GPIO_B, GPIO_CLEAR_SW_INT_PENDING, BIT_1); This code disables an interrupt request generated by pin 1 on Port B. 5-322 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 441 MC56F83xx, MC56F801x and MC56F802x/3x. Design/Implementation: The GPIO_SW_INT_ASSERT ioctl command is implemented as a macro. Example 5-225. GPIO_SW_INT_ASSERT ioctl( GPIO_B, GPIO_SW_INT_ASSERT, BIT_1); This code enables an interrupt request generated by pin 1 on Port B. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-323...
Page 442 Range Issues: None. Special Issues: None. Design/Implementation: The GPIO_INT_DETECTION_ACTIVE_HIGH ioctl command is implemented as a macro. Example 5-226. GPIO_INT_DETECTION_ACTIVE_HIGH ioctl( GPIO_B, GPIO_INT_DETECTION_ACTIVE_HIGH, BIT_1); This code sets pin 1 on Port B to be active high. 5-324 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 443 Range Issues: None. Special Issues: None. Design/Implementation: The GPIO_INT_DETECTION_ACTIVE_LOW ioctl command is implemented as a macro. Example 5-227. GPIO_INT_DETECTION_ACTIVE_LOW ioctl( GPIO_B, GPIO_INT_DETECTION_ACTIVE_LOW, BIT_1); This code sets pin 1 on Port B to be active low. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-325...
Page 444 This code clears the interrupt request flags from the GPIO Port B, pin 5. UWord16 intFlags; intFlags = ioctl( GPIO_A, READ_INT_PENDING_REG, NULL ); ioctl( GPIO_B, GPIO_CLEAR_INT_PENDING, intFlags); This code clears the appropriate interrupt request flags from the GPIO Port B. 5-326 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 445 Design/Implementation: The GPIO_SET_PIN ioctl command is implemented as a macro. Example 5-229. GPIO_SET_PIN ioctl( GPIO_B, GPIO_SET_PIN, BIT_0 | BIT_1 | BIT_2); This code sets pins 0, 1 and 2 on the GPIO, Port B. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-327...
Page 446 Design/Implementation: The GPIO_CLEAR_PIN ioctl command is implemented as a macro. Example 5-230. GPIO_CLEAR_PIN ioctl( GPIO_B, GPIO_CLEAR_PIN, BIT_0 | BIT_1 | BIT_2); This code clears pins 0, 1 and 2 on the GPIO, Port B. 5-328 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 447 Design/Implementation: The GPIO_TOGGLE_PIN ioctl command is implemented as a macro. Example 5-231. GPIO_TOGGLE_PIN ioctl( GPIO_B, GPIO_TOGGLE_PIN, BIT_0 | BIT_1 | BIT_2); This code toggles pins 0, 1 and 2 on the GPIO, Port B. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-329...
Page 448 Returns: None. Special Issues: None. Design/Implementation: The GPIO_READ_DATA ioctl command is implemented as a macro. Example 5-232. GPIO_READ_DATA tmp = ioctl( GPIO_B, GPIO_READ_DATA, NULL); This code reads from GPIO Port B into a variable tmp. 5-330 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 449 Special Issues: The GPIO pins must be set as GPIO output pins (See Section 5.8.3.3, Section 5.8.3.6). Design/Implementation: The GPIO_WRITE_DATA ioctl command is implemented as a macro. Example 5-233. GPIO_WRITE_DATA ioctl( GPIO_B, GPIO_WRITE_DATA, 0x0047); This code writes the value 0x0047 into the GPIO Port B. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-331...
Page 450 Special Issues: None. Design/Implementation: GPIO_READ_INT_PENDING_REG ioctl command implemented as a macro. Example 5-234. GPIO_READ_INT_PENDING_REG UWord16 tmp; tmp = ioctl( GPIO_B, GPIO_READ_INT_PENDING_REG, NULL); This code reads the GPIO Port B Interrupt Pending Register into a variable tmp. 5-332 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 451 Example 5-235. GPIO_GET_INT_PENDING_FLAG UWord16 tmp; tmp = ioctl( GPIO_B, GPIO_GET_INT_PENDING_FLAG, BIT_0 | BIT_1); This code reads the GPIO Port B pin/bit 0 and 1 interrupt pending flags into a variable tmp. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-333...
Page 452 Example 5-236. GPIO_TEST_INT_PENDING UWord16 tmp; tmp = ioctl( GPIO_B, GPIO_TEST_INT_PENDING, BIT_0 | BIT_1); This code tests the GPIO Port B pin/bit 0 and 1 interrupt pending flags and writes the result into a variable tmp. 5-334 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 453 Design/Implementation: The GPIO_SETAS_PUSHPULL ioctl command is implemented as a macro. Example 5-237. GPIO_SETAS_PUSHPULL ioctl( GPIO_B, GPIO_SETAS_PUSHPULL, BIT_0 | BIT_1 | BIT_2); This code sets the output driver of pins 0, 1 and 2 on Port B to push-pull mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-335...
Page 454 Design/Implementation: The GPIO_SETAS_OPENDRAIN ioctl command is implemented as a macro. Example 5-238. GPIO_SETAS_OPENDRAIN ioctl( GPIO_B, GPIO_SETAS_OPENDRAIN, BIT_0 | BIT_1 | BIT_2); This code sets the output driver of pins 0, 1 and 2 on Port B to open drain mode. 5-336 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 455 Design/Implementation: The GPIO_READ_RAW_DATA ioctl command is implemented as a macro. Example 5-239. GPIO_READ_RAW_DATA UWord16 tmp; tmp = ioctl( GPIO_B, GPIO_READ_RAW_DATA, NULL); This code reads logic state of all pins from GPIO Port B into a variable tmp. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-337...
Page 456 Design/Implementation: The GPIO_SET_HIGH_DRIVE_STRENGTH ioctl command is implemented as a macro. Example 5-240. GPIO_SET_HIGH_DRIVE_STRENGTH ioctl( GPIO_A, GPIO_SET_HIGH_DRIVE_STRENGTH, BIT_0 | BIT_1 | BIT_2); This code sets high drive strength on pins 0, 1 and 2 on the GPIO, Port A. 5-338 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 457 Design/Implementation: The GPIO_SET_LOW_DRIVE_STRENGTH ioctl command is implemented as a macro. Example 5-241. GPIO_SET_LOW_DRIVE_STRENGTH ioctl( GPIO_A, GPIO_SET_LOW_DRIVE_STRENGTH, BIT_0 | BIT_2 ); This code sets low drive strength on pins 0 and 2 on the GPIO, Port A. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-339...
Page 458 Design/Implementation: The GPIO_SET_LOW_PASS_FILTER_ENABLE ioctl command is implemented as a macro. Example 5-242. GPIO_SET_LOW_PASS_FILTER_ENABLE ioctl( GPIO_A, GPIO_SET_LOW_PASS_FILTER_ENABLE, BIT_1 | BIT_3 ); This code sets low pass input filter on pins 1 and 3 on the GPIO, Port A. 5-340 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 459 Design/Implementation: The GPIO_SET_LOW_PASS_FILTER_DISABLE ioctl command is implemented as a macro. Example 5-243. GPIO_SET_LOW_PASS_FILTER_DISABLE ioctl( GPIO_A, GPIO_SET_LOW_PASS_FILTER_DISABLE, BIT_1 | BIT_3 ); This code disables low pass input filter on pins 1 and 3 on the GPIO, Port A. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-341...
Page 460 Design/Implementation: The GPIO_SET_SLEW_RATE_FILTER_ENABLE ioctl command is implemented as a macro. Example 5-244. GPIO_SET_SLEW_RATE_FILTER_ENABLE ioctl( GPIO_A, GPIO_SET_SLEW_RATE_FILTER_ENABLE, BIT_1 | BIT_3 ); This code sets slew rate mode on pins 1 and 3 on the GPIO, Port A. 5-342 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 461 Design/Implementation: The GPIO_SET_SLEW_RATE_FILTER_DISABLE ioctl command is implemented as a macro. Example 5-245. GPIO_SET_SLEW_RATE_FILTER_DISABLE ioctl( GPIO_A, GPIO_SET_SLEW_RATE_FILTER_DISABLE, BIT_1 | BIT_3 ); This code disables slew rate mode on pins 1 and 3 on the GPIO, Port A. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-343...
Page 462: Gpio Driver Application
GPIO Port E pins 5-6 Example 5-246. GPIO Driver Application - appconfig.h /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * File Name: appconfig.h...
Page 463 PS/DS select: Disable , Write Wait States: 23, Read Wait States: 23 #define SEMI_CSBAR0_INIT 0x0005 #define SEMI_CSBAR1_INIT 0x0005 #define SEMI_CSBAR2_INIT 0x0005 #define SEMI_CSOR0_INIT 0x1FC3 #define SEMI_CSOR1_INIT 0x1BA3 #define SEMI_CSOR2_INIT 0x1DA3 #define SIM_GPS_INIT 0x0000 INTC Configuration FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-345...
Page 464 Int.Polarity: Active high , Pin 11: Function: GPIO , Direction: Input , PullUp: Disable , Interrupt: Disable, Int.Polarity: Active high , #define GPIO_E_DDR_INIT 0x0040 #define GPIO_E_PER_INIT 0x009F #define GPIO_E_IENR_INIT 0x0020 End of autogenerated code ********************************************************************** ..*/ #endif 5-346 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 465 Example 5-247. GPIO Driver Application - main.c /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * FILE NAME: main.c * DESCRIPTION: Sample application which shows how to generate interrupt...
Page 466 INTC_INIT, NULL); /* enable interrupts in SR */ archEnableInt(); /* toggle yellow LED1 */ ioctl(GPIO_C, GPIO_TOGGLE_PIN, BIT_1 ); while(1) for(i=0; i<500000; i++) asm(nop); /* toggles LED0 and LED1 */ ioctl(GPIO_C, GPIO_TOGGLE_PIN, BIT_0 | BIT_1); 5-348 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 467: Adc Driver (Mc56F83Xx,Mc56F801X,Mc56F802X/3X)
The following header files are needed in order to use the ADC device driver: Required Header File(s): #include "qs.h" #include "adc.h" The following information may be found in the header file adc.h. Public Data Structure(s): /* array of 8 result samples */ typedef UWord16 adc_tBuff[8]; FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-349...
Page 468: Configuration Items
Initial value of the ADC_ x High Limit Register 2 ADC_ x _ADHLMT3_INIT UWord16 Initial value of the ADC_ x High Limit Register 3 ADC_ x _ADHLMT4_INIT UWord16 Initial value of the ADC_ x High Limit Register 4 5-350 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 469 Initial value of the ADC_ x Offset Register 6 ADC_ x _ADOFS7_INIT UWord16 Initial value of the ADC_ x Offset Register 7 ADC_ x _CAL_INIT UWord16 Initial value of the ADC_ x Calibration Register FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-351...
Page 470: Api Specification
/ only one of the specified items is allowed | combination of items is allowed ( item1 | item2 | item3 ) & intersection of items is allowed ( item1 & item2 & item3 ) 5-352 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 471 ADC_AN4_AN5_DIFF | ADC_AN6_AN7_DIFF different notation on MC56F80xx: ADC_ANAx_ANAy_zzz ADC_ANBx_ANBy_zzz ADC_SET_SCAN_MODE ADC_SCAN_ONCE_SEQUENTIAL / None Configures conversion ADC_SCAN_ONCE_SIMULTANEOUS / sequence mode. It deter- ADC_SCAN_LOOP_SEQUENTIAL / mines how conversion ADC_SCAN_LOOP_SIMULTANEOUS / sequence is carried out. ADC_SCAN_TRIG_SEQUENTIAL / ADC_SCAN_TRIG_SIMULTANEOUS FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-353...
Page 472 CNTRL ADC_Sx_ZC_POSITIVE_NEGATIVE / detection logic for each ADC_Sx_ZC_NEGATIVE_POSITIVE / sample independently. ADC_Sx_ZC_ANY_CROSS Each sample can be set to x ... sample number (0-7) - must be 1 of 4 modes. unique for each constant 5-354 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 473 ADC_LOW_LIMIT | parameter are enabled. ADC_HIGH_LIMIT additional bits on MC56F80xx: ADC_END_OF_SCAN_CONVERTER_0| ADC_END_OF_SCAN_CONVERTER_1 ADC_READ_SAMPLE UWord16 Word16 Reads one sample result (sample number 0-7) at a time. The sample number is determined by param. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-355...
Page 474 UWord16 Reads the Limit Status (sample number 0-7) Register LLSx bit (“Low Limit Sample x flag”). ADC_GET_LIMIT_STATUS_HLS UWord16 UWord16 Reads the Limit Status (sample number 0-7) Register HLSx bit (“High Limit Sample x flag”). 5-356 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 475 BITS ADC_LLSx or ADC_HLSx bits. Limit Status Register. ADC_LLS_ALL or ADC_HLS_ALL may also be specified. ADC_CLEAR_ZERO_CROSS_ UWord16 None Clears the Zero Crossing STATUS_ZCS (sample number 0-7) Status Register ZCSx bit (“Zero Crossing x bit”). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-357...
Page 476 ADC_POWER_UP ADC_CONVERTER_0 | None Forces to power up indi- ADC_CONVERTER_1 | vidual ADC converters and ADC_VOLTAGE_REF the voltage reference. ADC_POWER_SAVE_MODE ADC_ON / ADC_OFF None Controls ADC power sav- ings mode. 5-358 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 477: Detailed Api Specification
ADC_ANA7_NORMAL / ADC_ANA7_FROM_DAC0 / ) / ( ADC_ANB7_NORMAL / ADC_ANB7_FROM_DAC1 / 5.9.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrates the ioctl commands usage. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-359...
Page 478 Design/Implementation: The ADC_INIT ioctl command is implemented as a function call. Example 5-248. ADC_INIT ioctl(ADC_A, ADC_INIT, NULL); This code initializes the ADC module by values defined in appconfig.h. The appconfig.h file can be edited manually or modified by the Graphical Configuration Tool. 5-360 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 479 In such a case it is necessary to wait for the end of a current scan cycle or to issue the ioctl(ADC_x, ADC_STOP, ADC_ON) command followed by the ioctl(ADC_x, ADC_STOP, ADC_OFF) command, which suspends the current scan cycle. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-361...
Page 480 It is useful to cancel an ADC operation when, for example, loop scan modes are selected or, when an ADC re-configuration is needed and the state of the ADC is not known. 5-362 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 481 /* sets ADC scan conversion start by SYNC input */ ioctl(ADC_A, ADC_SYNC, ADC_ON); /* ... */ /* test SAMPLE ready flags to read conversion results */ /* ... */ This code sets up the ADC for hardware conversion start. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-363...
Page 482 Design/Implementation: The ADC_SIMULT command is implemented as a macro. Example 5-252. ADC_SIMULT /* sets ADC independent parallel scan mode */ ioctl(ADC, ADC_SIMULT, ADC_OFF); This code resets the SIMULT bit in the ADC Control Register 2 to enable the independent parallel scan mode. 5-364 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 483 /* sets ADC clock 5MHz if IPclock=40MHz, DivisorValue = 40/(2*5)-1 = 3 */ ioctl(ADC_A, ADC_SET_DIVISOR, 3); This code sets up the ADC clock to maximum 5MHz for the fastest ADC operation on MC56F83xx devices. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-365...
Page 484 [9:6] of the ADC Control Register 2. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The ADC_SET_CHANNEL_CONFIG command is implemented as a macro. Example 5-254. ADC_SET_CHANNEL_CONFIG /* sets ADC inputs: AN0-AN1:differential, AN2-AN3:single ended, AN4-AN5:single ended, AN6-AN7 differential */ 5-366 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 485 ADC_SET_CHANNEL_CONFIG, ADC_AN0_AN1_DIFF | \ ADC_AN2_AN3_SE | ADC_AN4_AN5_SE | ADC_AN6_AN7_DIFF); This code sets up the ADC input to the desired measurement configuration. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-367...
Page 486 Design/Implementation: The ADC_SET_SCAN_MODE command is implemented as a macro. Example 5-255. ADC_SET_SCAN_MODE /* sets ADC scan to “Triggered Sequential Mode” */ ioctl(ADC_A, ADC_SET_SCAN_MODE, ADC_SCAN_TRIG_SEQUENTIAL This code sets up the ADC_A input to the desired scan mode. 5-368 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 487 /* maps ADC inputs to samples: */ /* AN6 -> S7, AN7 -> S6 */ ioctl(ADC_A, ADC_SET_LIST_SAMPLE7, ADC_CH6); ioctl(ADC_A, ADC_SET_LIST_SAMPLE6, ADC_CH7); This code sets up the ADC physical inputs to map to the desired SAMPLE channels. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-369...
Page 488 /* setups ADC for scanning of the SAMPLE0-SAMPLE4 provided that ADC is not in parallel mode */ ioctl(ADC_A, ADC_WRITE_SAMPLE_DISABLE, 5); /* the same code using parameters */ ioctl(ADC_A, ADC_WRITE_SAMPLE_DISABLE, ADC_SAMPLE5); This code sets up the scan sequence of the length of 5 samples. 5-370 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 489 /* SAMPLE7 - positive to negative change */ ioctl(ADC_A, ADC_WRITE_ZERO_CROSS_CNTRL, ADC_S0_ZC_POSITIVE_NEGATIVE | ADC_S1_ZC_DISABLE | ADC_S2_ZC_NEGATIVE_POSITIVE | ADC_S3_ZC_ANY_CROSS | ADC_S4_ZC_NEGATIVE_POSITIVE | ADC_S5_ZC_DISABLE | ADC_S6_ZC_ANY_CROSS | ADC_S7_ZC_POSITIVE_NEGATIVE); This code sets up the ADC_A zero crossing logic to the desired configuration. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-371...
Page 490 Design/Implementation: The ADC_ZERO_CROSS_CHx command is implemented as a macro. Example 5-259. ADC_ZERO_CROSS_CH x /* setup ADC zero crossing detection for SAMPLE5: */ /* SAMPLE5 - zero crossing disabled */ ioctl(ADC_A, ADC_ZERO_CROSS_CH5, ADC_ZC_DISABLE); This code disables the ADC_A zero crossing logic for SAMPLE5. 5-372 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 491 /* enable ADC end of scan interrupt */ ioctl(ADC_A, ADC_END_OF_SCAN_INT, ADC_ENABLE); /* ... */ /* disable ADC end of scan interrupt */ ioctl(ADC_A, ADC_END_OF_SCAN_INT, ADC_DISABLE); This code switches on/off the ADC_A end of scan interrupt. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-373...
Page 492 Example 5-261. ADC_ZERO_CROSS_INT /* enable ADC zero crossing interrupt */ ioctl(ADC_A, ADC_ZERO_CROSS_INT, ADC_ENABLE); /* ... */ /* disable ADC zero crossing interrupt */ /ioctl(ADC_A, ADC_ZERO_CROSS_INT, ADC_DISABLE); This code switches on/off the ADC_A zero crossing interrupt. 5-374 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 493 Example 5-262. ADC_LOW_LIMIT_INT /* enable ADC low limit interrupt */ ioctl(ADC_A, ADC_LOW_LIMIT_INT, ADC_ENABLE); /* ... */ /* disable ADC low limit interrupt */ /ioctl(ADC_A, ADC_LOW_LIMIT_INT, ADC_DISABLE); This code switches on/off the ADC_A low limit interrupt. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-375...
Page 494 Example 5-263. ADC_HIGH_LIMIT_INT /* enable ADC high limit interrupt */ ioctl(ADC_A, ADC_HIGH_LIMIT_INT, ADC_ENABLE); /* ... */ /* disable ADC high limit interrupt */ /ioctl(ADC_A, ADC_HIGH_LIMIT_INT, ADC_DISABLE); This code switches on/off the ADC_A high limit interrupt. 5-376 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 495 This code enables the ADC A high limit interrupt. /* enable ADC high limit interrupt and end of scan interrupt */ ioctl(ADC_B, ADC_INT_ENABLE, ADC_HIGH_LIMIT | ADC_END_OF_SCAN); This code enables the ADC B high limit and end of scan interrupts. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-377...
Page 496 This code disables the ADC A high limit interrupt. /* disable ADC high limit interrupt and end of scan interrupt */ ioctl(ADC_B, ADC_INT_DISABLE, ADC_HIGH_LIMIT | ADC_END_OF_SCAN); This code disables the ADC B high limit and end of scan interrupts. 5-378 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 497 Special Issues: The ADC_END_OF_SCAN_CONVERTER_1 is applicable only on the MC56F80xx device when operating in non-simultaneous mode. Design/Implementation: The ADC_TEST_INT_ENABLED command is implemented as a macro. Example 5-266. ADC_TEST_INT_ENABLED if(ioctl(ADC_A, ADC_TEST_INT_ENABLED, ADC_HIGH_LIMIT)) This code tests if the High-Limit interrupt is enabled. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-379...
Page 498 Special Issues: None. Design/Implementation: The ADC_READ_SAMPLE command is implemented as a macro. Example 5-267. ADC_READ_SAMPLE Word16 R3; /* read SAMPLE3 result */ R3 = ioctl(ADC_A, ADC_READ_SAMPLE, 3); This code reads the ADC_A SAMPLE3 result. 5-380 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 499 /* all sample results are in ResBuffer array */ This code reads all eight samples from result registers and places them to result buffer ResBuffer (it is an array with a length of eight words). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-381...
Page 500 /* test bits LLMTI, HLMTI (low and high limit flags for all samples) */ if (Status & (ADC_LLMTI | ADC_HLMTI)) /* at least one of LLMTI,HLMTI bits is set */ /* result is out of desired range */ /* ... */ 5-382 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 501 This code reads the whole ADC Status Register and tests if any result went beyond low or high limits. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-383...
Page 502 /* at least one flag is set - result is out of desired range */ /* ... */} This code reads the whole ADC Limit Status register and tests independently if the results went beyond low or high limits. 5-384 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 503 /* zero crossing occurred for at least one of the samples */ /* ... */ This code reads the whole ADC Zero Crossing Status Register and tests if a zero crossing occurred for any of samples 0, 2, 6. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-385...
Page 504 /* “scan conversion” is still in progress */ /* ... */ else /* conversion finished */ /* ... */ This code tests the status register, bit CIP/CIP0 and shows the use of the command as a Boolean expression. 5-386 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 505 /* ... */ else /* scan cycle has not been completed yet */ /* ... */ This code tests the ADC Status Register, bit EOSI/EOSI0 and shows the use of the command as a Boolean expression. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-387...
Page 506 /* zero crossing occurred (for any sample) */ /* ... */ else /* no zero crossing occurred */ /* ... */ This code tests the ADC Status Register, bit ZCI and shows the use of the command as a Boolean expression. 5-388 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 507 /* ... */ else /* all samples were higher than low limits */ /* ... */ This code tests the ADC Status Register, bit LLMTI and shows the use of the command as a Boolean expression. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-389...
Page 508 /* ... */ else /* all samples were lower than high limits */ /* ... */ This code tests the ADC Status Register, bit HLMTI and shows the use of the command as a Boolean expression. 5-390 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 509 (ioctl(ADC_A, ADC_GET_STATUS_RDY, 3)) /* SAMPLE3 is ready to read */ S = ioctl(ADC_A, ADC_READ_SAMPLE, 3); This code tests the ADC Status Register, bit RDY3 and reads SAMPLE3 if ready (if conversion for this sample ended). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-391...
Page 510 /* SAMPLE0 result is below low limit */ else /* SAMPLE0 result is above low limit */ This code tests the ADC Limit Status Register, bit LLS0 and shows the use of the command as a Boolean expression. 5-392 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 511 /* SAMPLE6 result is above high limit */ else /* SAMPLE6 result is below low limit */ This code tests the ADC Limit Status Register, bit HLS1 and shows the use of the command as a Boolean expression. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-393...
Page 512 /* zero crossing occurred for SAMPLE2 */ else /* no zero crossing for SAMPLE2 */ This code tests the ADC Limit Status Register, bit ZCS2 and shows the use of the command as a Boolean expression. 5-394 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 513 Example 5-281. ADC_CLEAR_STATUS_EOSI /* clear status register EOSI/EOSI0 bit */ ioctl(ADC_A, ADC_CLEAR_STATUS_EOSI, NULL); This code clears the ADC Status Register, bit EOSI. This bit is not cleared automatically when an interrupt service routine is entered. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-395...
Page 514 Example 5-282. ADC_CLEAR_STATUS_LLMTI /* clear status register LLMTI bit */ ioctl(ADC_A, ADC_CLEAR_STATUS_LLMTI, NULL); This code clears the ADC Status Register, bit LLMTI. This bit is not cleared automatically when an interrupt service routine is entered. 5-396 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 515 Example 5-283. ADC_CLEAR_STATUS_HLMTI /* clear status register HLMTI bit */ ioctl(ADC_A, ADC_CLEAR_STATUS_HLMTI, NULL); This code clears the ADC Status Register, bit HLMTI. This bit is not cleared automatically when an interrupt service routine is entered. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-397...
Page 516 Example 5-284. ADC_CLEAR_STATUS_ZCI /* clear status register ZCI bit */ ioctl(ADC_A, ADC_CLEAR_STATUS_ZCI, NULL); This code clears the ADC Status Register, bit ZCI. This bit is not cleared automatically when an interrupt service routine is entered. 5-398 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 517 Design/Implementation: The ADC_CLEAR_LIMIT_STATUS_LLS command is implemented as a macro. Example 5-285. ADC_CLEAR_LIMIT_STATUS_LLS /* clear limit status register LLS4 bit (low limit flag for sample 4) */ ioctl(ADC_A, ADC_CLEAR_LIMIT_STATUS_LLS, 4); This code clears the ADC Limit Status Register, bit LLS4. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-399...
Page 518 Design/Implementation: The ADC_CLEAR_LIMIT_STATUS_HLS command is implemented as a macro. Example 5-286. ADC_CLEAR_LIMIT_STATUS_HLS /* clear limit status register HLS5 bit (high limit flag for sample 5) */ ioctl(ADC_A, ADC_CLEAR_LIMIT_STATUS_LLS, 5); This code clears the ADC Limit Status Register, bit HLS5. 5-400 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 519 Range Issues: Sample x number: 0-7 Special Issues: None. Design/Implementation: The ADC_CLEAR_LIMIT_STATUS_BITS command is implemented as a macro. Example 5-287. ADC_CLEAR_LIMIT_STATUS_BITS ioctl(ADC_A, ADC_CLEAR_LIMIT_STATUS_LLS, ADC_LLS_ALL); This code clears the all low-limit status bits in the ADC Limit Status Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-401...
Page 520 Example 5-288. ADC_CLEAR_ZERO_CROSS_STATUS_ZCS /* clear zero crossing status register ZCS1 bit (zero crossing flag for sample 1) */ ioctl(ADC_A, ADC_CLEAR_ZERO_CROSS_STATUS_ZCS, 1); This code clears the ADC Zero Crossing Status Register, bit ZCS1. 5-402 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 521 This code writes an offset values for SAMPLE0, 3. These values are subtracted from the respective conversion result prior to writing to the result register. This way, the output coding can be controlled or it is possible to correct the system offset of the whole ADC chain. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-403...
Page 522 This code writes a low limit values for SAMPLE0,6. These values are used to check the desired threshold. Values in result registers are not changed with this checking, only low limit flags are set (LLSx). 5-404 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 523 This code writes a high limit values for SAMPLE1,2. These values are used to check the desired threshold. Values in result registers are not changed with this checking, only high limit flags are set (HLSx). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-405...
Page 524 R5 = ioctl(ADC_A, ADC_READ_LOW_LIMIT, 5); This code reads the ADC low limit for SAMPLE5. This is useful, for example, to update a register value relatively to its previous value, without any additional memory storage. 5-406 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 525 R2 = ioctl(ADC_A, ADC_READ_HIGH_LIMIT, 2); This code reads the ADC high limit for SAMPLE2. This is useful, for example, to update a register value relatively to its previous value, without any additional memory storage. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-407...
Page 526 /* read low limit for SAMPLE1 */ R1 = ioctl(ADC_A, ADC_READ_OFFSET, 1); This code reads the ADC offset for SAMPLE1. This is useful, for example, to update a register value relatively to its previous value, without any additional memory storage. 5-408 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 527 Example 5-295. ADC_POWER_DOWN ioctl(ADC_A, ADC_POWER_DOWN, ADC_VOLTAGE_REF); This code forces to power down the ADC A voltage reference. ioctl(ADC_B, ADC_POWER_DOWN, ADC_CONVERTER_0 | ADC_CONVERTER_1); This code forces to power down the ADC B converter 0 and converter 1. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-409...
Page 528 Example 5-296. ADC_POWER_UP ioctl(ADC_A, ADC_POWER_UP, ADC_VOLTAGE_REF); This code forces to power up the ADC A voltage reference. ioctl(ADC_B, ADC_POWER_UP, ADC_CONVERTER_0 | ADC_CONVERTER_1); This code forces to power up the ADC B converter 0 and converter 1. 5-410 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 529 Example 5-297. ADC_POWER_SAVE_MODE ioctl(ADC_A, ADC_POWER_SAVE_MODE, ADC_ON); This code activates the power savings mode on the ADC A module. ioctl(ADC_B, ADC_POWER_SAVE_MODE, ADC_OFF); This code deactivates the power savings mode on the ADC B module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-411...
Page 530 Range Issues: param must be within <0x000, 0x003f>. Special Issues: None. Design/Implementation: The ADC_SET_POWER_UP_DELAY ioctl command is implemented as a macro. Example 5-298. ADC_SET_POWER_UP_DELAY ioctl(ADC_A, ADC_SET_POWER_UP_DELAY, 0x000f); This code sets power up delay to 15 ADC clocks. 5-412 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 531 This code stores the ADC A voltage reference power status to variable pwrStatus. pwrStatus = ioctl(ADC_B, ADC_GET_POWER_STATUS, ADC_CONVERTER_0 | ADC_CONVERTER_1); This code stores the ADC B converter 0 power status and converter 1 power status to variable pwrStatus. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-413...
Page 532 Special Issues: None. Design/Implementation: ADC_READ_POWER_CONTROL_REG command implemented as a macro. Example 5-300. ADC_READ_POWER_CONTROL_REG UWord16 cntrl; cntrl = ioctl(ADC_A, ADC_READ_POWER_CONTROL_REG, NULL); This code stores the content of the ADC Power Control Register to variable cntrl. 5-414 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 533 ADC_CALIB_ENABLE, ADC_CONVERTER_0); This code enables calibration of the ADC A converter 0. ioctl(ADC_B, ADC_CALIB_ENABLE, ADC_CONVERTER_0 | ADC_CONVERTER_1); Enter the calibration mode of the ADC B converter 0 and converter 1 using this code. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-415...
Page 534 Design/Implementation: The ADC_CALIB_DISABLE command is implemented as a macro. Example 5-302. ADC_CALIB_DISABLE ioctl(ADC_A, ADC_CALIB_DISABLE, ADC_CONVERTER_0 | ADC_CONVERTER_1); This code disables calibration of the ADC A converter 0. and 1 - starts ADC normal operation. 5-416 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 535 Special Issues: This command is available on on the MC56F83xx devices. Design/Implementation: ADC_SET_CONVERTER0_CALIB_REF command implemented as a macro. Example 5-303. ADC_SET_CONVERTER0_CALIB_REF ioctl(ADC_A, ADC_SET_CONVERTER0_CALIB_REF, ADC_VCAL_H); This code selects V (=0.75 V ) as the calibration reference for the ADC A converter 0. CAL_H REFH FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-417...
Page 536 Special Issues: This command is available on on the MC56F83xx devices. Design/Implementation: ADC_SET_CONVERTER1_CALIB_REF command implemented as a macro. Example 5-304. ADC_SET_CONVERTER1_CALIB_REF ioctl(ADC_A, ADC_SET_CONVERTER1_CALIB_REF, ADC_VCAL_L); This code selects V (=0.25 V ) as the calibration reference for the ADC A converter 1. CAL_L REFH 5-418 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 537 ADC_POWER_SAVE_MODE ioctl command). Design/Implementation: The ADC_AUTO_POWER_DOWN command is implemented as a macro. Example 5-305. ADC_AUTO_POWER_DOWN ioctl(ADC, ADC_AUTO_POWER_DOWN, ADC_ON); This code activates the Auto Power Down power saving mode on the ADC module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-419...
Page 538 This command is applicable only on MC56F80xx. Design/Implementation: The ADC_AUTO_STANDBY command is implemented as a macro. Example 5-306. ADC_AUTO_STANDBY ioctl(ADC, ADC_AUTO_STANDBY, ADC_ON); This code activates the Auto Standby power saving mode on the ADC module. 5-420 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 539 Design/Implementation: The ADC_SET_VREFL_SOURCE command is implemented as a macro. Example 5-307. ADC_SET_VREFL_SOURCE ioctl(ADC, ADC_SET_VREFL_SOURCE, ADC_VREF_SRC_EXTERNAL); This code sets the ANB2 pin as input of the VREFLO reference input (pin must be configured as peripheral in the GPIO module). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-421...
Page 540 Special Issues: This command is applicable only on MC56F80xx. Design/Implementation: The ADC_SET_VREFH_SOURCE command is implemented as a macro. Example 5-308. ADC_SET_VREFH_SOURCE ioctl(ADC, ADC_SET_VREFH_SOURCE, ADC_VREF_SRC_INTERNAL); This code interconnects the internal VDDA voltage to the VREFH reference input. 5-422 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 541 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The ADC_SET_VREFH0_SOURCE command is implemented as a macro. Example 5-309. ADC_SET_VREFH0_SOURCE ioctl(ADC, ADC_SET_VREFH0_SOURCE, ADC_VREF_SRC_INTERNAL); This code interconnects the internal VDDA voltage to the VREFH reference input of the ADC sub-converter 0. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-423...
Page 542 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The ADC_SET_VREFL0_SOURCE command is implemented as a macro. Example 5-310. ADC_SET_VREFL0_SOURCE ioctl(ADC, ADC_SET_VREFL0_SOURCE, ADC_VREF_SRC_INTERNAL); This code interconnects the internal VSSA voltage to the VREFLO reference input of the ADC sub-converter 0. 5-424 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 543 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The ADC_SET_VREFH1_SOURCE command is implemented as a macro. Example 5-311. ADC_SET_VREFH1_SOURCE ioctl(ADC, ADC_SET_VREFH1_SOURCE, ADC_VREF_SRC_INTERNAL); This code interconnects the internal VDDA voltage to the VREFH reference input of the ADC sub-converter 1. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-425...
Page 544 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The ADC_SET_VREFL1_SOURCE command is implemented as a macro. Example 5-312. ADC_SET_VREFL1_SOURCE ioctl(ADC, ADC_SET_VREFL1_SOURCE, ADC_VREF_SRC_INTERNAL); This code interconnects the internal VSSA voltage to the VREFLO reference input of the ADC sub-converter 1. 5-426 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 545 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The ADC_SET_CALIB_SOURCE command is implemented as a macro. Example 5-313. ADC_SET_CALIB_SOURCE ioctl(ADC, ADC_SET_CALIB_SOURCE, ADC_ANA7_NORMAL | ADC_ANB7_NORMAL); This code sets-up a normal routing of both ANA7 and ANB7 input signals. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-427...
Page 546: Adc Driver Application
- software ADC conversion start, stop, results reading with polling interface - hardware ADC conversion start, interrupt driven interface driver applications found e.g. {DSP56800E_Quick_Start Source}\..\sample_applications\MC56F8346EVM\adc_demo. It consists of the application project adc_demo.mcp and the source code for the application main.c. 5-428 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 547 Example 5-314. ADC Driver Application - appconfig.h /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2007 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * File Name: appconfig.h * Description: file for static configuration of the application...
Page 548 Pin 11: Function: ISB1 , PullUp: Enable , Pin 12: Function: ISB2 , PullUp: Enable , #define GPIO_D_PER_INIT 0x1FC1 ADC_A Configuration -------------------------------------------- Clock frequency: 5 MHz Trigger source: Software start Channel Configuration: AN0-AN1: Single ended , AN2-AN3: Single ended 5-430 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 549 ********************************************************************** ..*/ #endif Example 5-315. ADC Driver Application - main.c /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2007 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * FILE NAME: main.c * DESCRIPTION: Demo program for ADC driver...
Page 550 /* read all samples (8) to buffer */ ioctl(ADC_A, ADC_READ_ALL_SAMPLES, adc_Buff); /* results are in adc_Buff set breakpoint to line below and see adc_Buff for results */ while(1) /* keep watchdog clear (if enabled) */ ioctl(COP, COP_CLEAR_COUNTER, NULL); 5-432 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 551: Adc Driver (Mc56F800X)
The following header files are needed in order to use the ADC device driver: Required Header File(s): #include "qs.h" #include "adc.h" The following information may be found in the header file adc.h. Public Data Structure(s): FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-433...
Page 552: Configuration Items
UWord16 ioctl(const int *pModuleBase, void cmd, void* pParam); Description: The ioctl call “changes” the ADC device modes or accesses the ADC register(s). The third ioctl parameter is either a value or a pointer, depending on the type of cmd. 5-434 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 553 VATE/ VDDCORE/ VDDAREG/ VREF/ TEM- PERATURE/ 0_PGA0/ 1_PGA1) Note: The ADC_0_PGA0 channel can be used only at the ADC 0 converter and the ADC_1_PGA1 channel can be used only at the ADC 1 converter. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-435...
Page 554 B. ADC_SET_LOW_POWER_ ADC_HIGH_SPEED / None selects low or high power mode. CONF ADC_LOW_SPEED ADC_SET_DIVIDER ADC_CLOCK_DIVIDER_1/ None selects clock divider. ADC_CLOCK_DIVIDER_2/ ADC_CLOCK_DIVIDER_4/ ADC_CLOCK_DIVIDER_8 ADC_SET_SAMPLE_TIME ADC_SHORT_TIME / None Selects long or short sample time. ADC_LONG_TIME 5-436 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 555: Detailed Api Specification
ADC_CLOCK_SEL_BUS_ DIV2 / ADC_CLOCK_SEL_ ALTCLK / ADC_CLOCK_SEL_ ADATCK 5.10.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the usage of the ioctl commands. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-437...
Page 556 Example 5-316. ADC_INIT ioctl(ADC0, ADC_INIT, NULL); This code initializes the ADC 0 module by the values defined in appconfig.h. The appconfig.h file can be edited manually or generated by the Graphical Configuration Tool. 5-438 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 557 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The ADC_SET_CONVERSION_MODE_A command is implemented as a macro. Example 5-317. ADC_SET_CONVERSION_MODE_A ioctl(ADC0, ADC_SET_CONVERSION_MODE_A,ADC_CONVERSION_SINGLE); This code sets the ADC 0 to single conversion at result A. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-439...
Page 558 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The ADC_SET_CONVERSION_MODE_B command is implemented as a macro. Example 5-318. ADC_SET_CONVERSION_MODE_B ioctl(ADC0, ADC_SET_CONVERSION_MODE_B,ADC_CONVERSION_CONTINUOUS); This code sets the ADC 0 to single conversion at result B. 5-440 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 559 Design/Implementation: The ADC_SET_INPUT_CHANNEL_A command is implemented as a macro. Example 5-319. ADC_SET_INPUT_CHANNEL_A ioctl(ADC0, ADC_SET_CONVERSION_TRIGGER, ADC_TRIGGER_SW); ioctl(ADC0, ADC_SET_INPUT_CHANNEL_A, ADC_AD7); This code sets the ADC0 module to software trigger mode, sets input channel to 7 and initialize ADC conversion. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-441...
Page 560 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The ADC_SET_INPUT_CHANNEL_B command is implemented as a macro. Example 5-320. ADC_SET_INPUT_CHANNEL_B ioctl(ADC0, ADC_SET_INPUT_CHANNEL_B, ADC_0_PGA0); This code sets input channel to the Programable Gain Amplifier output 5-442 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 561 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: ADC_TEST_CONVERSION_COMPLETE_A command implemented as a macro. Example 5-321. ADC_TEST_CONVERSION_COMPLETE_A if (ioctl(ADC0, ADC_TEST_CONVERSION_COMPLETE_A, NULL)) This code tests if the ADC0 module has finished coversion. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-443...
Page 562 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: ADC_TEST_CONVERSION_COMPLETE_B command implemented as a macro. Example 5-322. ADC_TEST_CONVERSION_COMPLETE_B if (ioctl(ADC0, ADC_TEST_CONVERSION_COMPLETE_B, NULL)) This code tests if the ADC0 module has finished coversion. 5-444 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 563 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The ADC_TEST_CONVERSION_ACTIVE command is implemented as a macro. Example 5-323. ADC_TEST_CONVERSION_ACTIVE if (ioctl(ADC0, ADC_TEST_CONVERSION_ACTIVE, NULL)) This code tests if the ADC0 module conversion is performing. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-445...
Page 564 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The ADC_SET_TRIGGER_MODE command is implemented as a macro. Example 5-324. ADC_SET_TRIGGER_MODE ioctl(ADC0, ADC_SET_TRIGGER_MODE,ADC_TRIGGER_SW); ioctl(ADC0, ADC_SET_INPUT_CHANNEL_A,ADC_AD9); This code sets the ADC 0 module to Software Trigger mode and initiates conversion. 5-446 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 565 Status and Control Register 2. Returns: None. Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: ADC_SET_CONVERSION_CLOCK_OUT command implemented as a macro. Example 5-325. ADC_SET_CONVERSION_CLOCK_OUT ioctl(ADC0, ADC_SET_CONVERSION_CLOCK_OUT,ADC_DISABLE); This code disables the continuous clock output. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-447...
Page 566 Design/Implementation: The ADC_SET_VOLTAGE_REFERENCE command is implemented as a macro. Example 5-326. ADC_SET_VOLTAGE_REFERENCE ioctl(PMC, PMC_SET_BANDGAP_BUFFER, PMC_ENABLE); ioctl(ADC0, ADC_SET_VOLTAGE_REFERENCE, ADC_SOURCE_BANDGAP); This code enables the bandgap reference buffer and selects bandgap reference as the ADC voltage reference. 5-448 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 567 Special Issues: None. Design/Implementation: The ADC_READ_SAMPLE_A command is implemented as a macro. Example 5-327. ADC_READ_SAMPLE_A Word16 R; /* read SAMPLE A result */ R = ioctl(ADC0, ADC_READ_SAMPLE_A, NULL); This code reads the ADC0 SAMPLE result A. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-449...
Page 568 Special Issues: None. Design/Implementation: The ADC_READ_SAMPLE_B command is implemented as a macro. Example 5-328. ADC_READ_SAMPLE_B Word16 R; /* read SAMPLE A result */ R = ioctl(ADC0, ADC_READ_SAMPLE_B, NULL); This code reads the ADC0 SAMPLE result B. 5-450 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 569 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The ADC_SET_DIVIDER command is implemented as a macro. Example 5-329. ADC_SET_DIVIDER ioctl(ADC0, ADC_SET_DIVIDER, ADC_CLOCK_1); This code selects the divide ratio to 1. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-451...
Page 570 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The ADC_SET_SAMPLE_TIME command is implemented as a macro. Example 5-330. ADC_SET_SAMPLE_TIME ioctl(ADC0, ADC_SET_SAMPLE_TIME, ADC_SHORT_TIME); This code selects short sample time at the ADC 0 module. 5-452 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 571 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The ADC_SET_RESOLUTION command is implemented as a macro. Example 5-331. ADC_SET_RESOLUTION ioctl(ADC0, ADC_SET_RESOLUTION, ADC_12BIT); This code selects to the 12bits conversion mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-453...
Page 572 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The ADC_SET_CLOCK_INPUT command is implemented as a macro. Example 5-332. ADC_SET_CLOCK_INPUT ioctl(ADC0, ADC_SET_CLOCK_INPUT, ADC_ADACK); This code enables asynchronous clock generator and select its outpus as ADC module clock source. 5-454 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 573: Adc Driver Applications
LED diode PWM5 indicates that the main loop is working correctly. LED diode PWM4 indicates that the PWM module is reloading correctly. LED diode PWM3 indicates that the ADC module is convering correctly. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-455...
Page 574 5-456 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 575: Pga Driver
The following header files are needed in order to use the PGA device driver: Required Header File(s): #include "qs.h" #include "pga.h" The following information may be found in the header file pga.h. Public Data Structure(s): FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-457...
Page 576: Configuration Items
The third ioctl parameter is either a value or a pointer, depending on the type of cmd. Arguments: Table 5-363. PGA Driver Arguments - ioctl pModuleBase The PGA module identifier. Use PGA0 or PGA1.. 5-458 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 577 Sets Low or High power mode. PGA_HIGH_POWER PGA_ENABLE_MODULE NULL None Enables the PGA module. PGA_DISABLE_MODULE NULL None Disables the PGA module. PGA_SET_SH_BYPASS PGA_ENABLE / None Enables or disables Sample and PGA_DISABLE hold amplifier bypass. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-459...
Page 578: Detailed Api Specification
UWord16 Reads and returns startup complete COMPLETE flag. 5.11.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the usage of the ioctl commands. 5-460 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 579 Example 5-333. PGA_INIT ioctl(PGA0, PGA_INIT, NULL); This code initializes the PGA 0 module by the values defined in appconfig.h. The appconfig.h file can be edited manually or generated by the Graphical Configuration Tool. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-461...
Page 580 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_SET_TRIGGER_MODE command is implemented as a macro. Example 5-334. PGA_SET_TRIGGER_MODE ioctl(PGA0, PGA_SET_TRIGGER_MODE,PGA_TRIGGER_SW); ioctl(PGA0, PGA_SET_SW_TRIGGER,NULL); This code sets the PGA 0 module to Software Trigger mode and initiates conversion. 5-462 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 581 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_SET_GAIN command is implemented as a macro. Example 5-335. PGA_SET_GAIN ioctl(PGA0, PGA_SET_GAIN,PGA_GAIN_32X); This code sets the amplifier gain to 32 at the PGA 0 module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-463...
Page 582 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_SET_GAIN_SH command is implemented as a macro. Example 5-336. PGA_SET_GAIN_SH ioctl(PGA, PGA_SET_GAIN_SH,PGA_GAIN_1X); This code sets amplifier gain to 1 at the sample and hold stage of PGA 0 module. 5-464 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 583 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_SET_GAIN_DIFF command is implemented as a macro. Example 5-337. PGA_SET_GAIN_DIFF ioctl(PGA0, PGA_SET_GAIN_DIFF,PGA_GAIN_3X); This code sets amplifier gain to 3 at the differential stage. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-465...
Page 584 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_SET_GAIN_DIFF_2 command is implemented as a macro. Example 5-338. PGA_SET_GAIN_DIFF_2 ioctl(PGA0, PGA_SET_GAIN_DIFF_2,PGA_GAIN_4X); This code sets amplifier gain to 4 at the differential-to-single-ended stage. 5-466 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 585 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_SET_POWER_MODE command is implemented as a macro. Example 5-339. PGA_SET_POWER_MODE ioctl(PGA0, PGA_SET_POWER_MODE,PGA_HIGH_POWER); This code sets the PGA 0 module to high power mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-467...
Page 586 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_ENABLE_MODULE command is implemented as a macro. Example 5-340. PGA_ENABLE_MODULE ioctl(PGA0, PGA_ENABLE_MODULE, NULL); while(!ioctl(PGA0,PGA_TEST_STARTUP_COMPLETE,NULL)) This code enables the PGA 0 and wait to module initialization complete. 5-468 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 587 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_DISABLE_MODULE command is implemented as a macro. Example 5-341. PGA_DISABLE_MODULE ioctl(PGA0, PGA_DISABLE_MODULE, NULL); This code disables the PGA 0 module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-469...
Page 588 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_SET_SH_BYPASS command is implemented as a macro. Example 5-342. PGA_SET_SH_BYPASS ioctl(PGA0, PGA_SET_SH_BYPASS,PGA_DISABLE); This code disables bypass at the S/H stage. 5-470 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 589 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_SET_CALIBRATION_MODE command is implemented as a macro. Example 5-343. PGA_SET_CALIBRATION_MODE ioctl(PGA0, PGA_SET_CALIBRATION_MODE,PGA_DISABLE); This code sets the PGA 0 module to the mission mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-471...
Page 590 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_SET_CHARGE_PUMP_DIV command is implemented as a macro. Example 5-344. PGA_SET_CHARGE_PUMP_DIV ioctl(PGA0, PGA_SET_CHARGE_PUMP_DIV,0); This code sets the PGA 0 module to the mission mode. 5-472 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 591 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_SET_SW_TRIGGER command is implemented as a macro. Example 5-345. PGA_SET_SW_TRIGGER ioctl(PGA, PGA_SET_SW_TRIGGER, NULL); This code activates the PGA 0 module software trigger. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-473...
Page 592 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_SET_DIVIDER command is implemented as a macro. Example 5-346. PGA_SET_DIVIDER ioctl(PGA0, PGA_SET_DIVIDER, PGA_CLOCK_DIVIDER_8); This code sets the PGA 0 clock divider to 8. 5-474 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 593 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_SET_CLK_GS command is implemented as a macro. Example 5-347. PGA_SET_CLK_GS ioctl(PGA0, PGA_SET_CLK_GS,2); This code sets the number of PGA gain clock pulses per conversion to 2. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-475...
Page 594 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_TEST_RUNNING command is implemented as a macro. Example 5-348. PGA_TEST_RUNNING if (ioctl(PGA, PGA_TEST_RUNNING, NULL)) This code tests if the PGA module is performing a coversion. 5-476 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 595 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PGA_TEST_STARTUP_COMPLETE command is implemented as a macro. Example 5-349. PGA_TEST_STARTUP_COMPLETE if (ioctl(PGA, PGA_TEST_STARTUP_COMPLETE, NULL)) This code tests if the PGA module is enabled and has completed its startup sequence. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-477...
Page 596: Pga Driver Applications
LED diode PWM5 indicates that the main loop is working correctly. LED diode PWM4 indicates that the PWM module is reloading correctly. LED diode PWM3 indicates that the ADC module is convering correctly. 5-478 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 597: Pdb Driver
The following header files are needed in order to use the PDB device driver: Required Header File(s): #include "qs.h" #include "pdb.h" The following information may be found in the header file pdb.h. Public Data Structure(s): None FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-479...
Page 598: Configuration Items
Description: The ioctl call “changes” the PDB device modes or accesses the PDB register(s). The third ioctl parameter is either a value or a pointer, depending on the type of cmd. Arguments: Table 5-384. PDB Driver Arguments - ioctl pModuleBase PDB module identifier. Use PDB. 5-480 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 599 PDB_TRIGGER_A _PULSE_OUT PDB_SET_TRIGGER_B_OUT PDB_TRIGGER_B None Selects PDB trigger B output. _BYPASS / PDB_TRIGGER_B _DELAY_B / PDB_TRIGGER_B _DELAY_AB / PDB_TRIGGER_B _PULSE_OUT PDB_SET_CONTINUOUS_ PDB_ENABLE/ None Enables/disables continuous mode. MODE PDB_DISABLE PDB_SET_SW_TRIGGER NULL None Activates SW trigger. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-481...
Page 600: Detailed Api Specification
PDB_READ_COUNTER_REG NULL UWord16 Reads PDB immediate counter value. 5.12.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the usage of the ioctl commands. 5-482 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 601 Example 5-350. PDB_INIT ioctl(PDB, PDB_INIT, NULL); This code initializes the PDB module by the values defined in appconfig.h. The appconfig.h file can be edited manually or generated by the Graphical Configuration Tool. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-483...
Page 602 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PDB_SET_PRESCALER command is implemented as a macro. Example 5-351. PDB_SET_PRESCALER ioctl(PDB, PDB_SET_PRESCALER,PDB_CLOCK_DIVIDER_16); This code sets clock source prescaler to 16. 5-484 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 603 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PDB_SET_TRIGGER_A_OUT command is implemented as a macro. Example 5-352. PDB_SET_TRIGGER_A_OUT ioctl(PDB, PDB_SET_TRIGGER_A_OUT,PDB_TRIGGER_A_PULSE_OUT); This code sets the Trigger A Output to the Trigger Pulsed Output Operation. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-485...
Page 604 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PDB_SET_TRIGGER_B_OUT command is implemented as a macro. Example 5-353. PDB_SET_TRIGGER_B_OUT ioctl(PDB, PDB_SET_TRIGGER_B_OUT,PDB_TRIGGER_B_DELAY_AB); This code sets the Trigger B Output to the Ping-Pong Operation. 5-486 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 605 Returns: None. Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PDB_SET_CONTINUOUS_MODE command is implemented as a macro. Example 5-354. PDB_SET_CONTINUOUS_MODE ioctl(PDB, PDB_SET_CONTINUOUS_MODE, PDB_ENABLE); This code enables continuous mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-487...
Page 606 Returns: None. Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PDB_SET_SW_TRIGGER command is implemented as a macro. Example 5-355. PDB_SET_SW_TRIGGER ioctl(PDB, PDB_SET_SW_TRIGGER, NULL); This code activates software trigger. 5-488 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 607 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PDB_SET_INPUT_TRIGGER command is implemented as a macro. Example 5-356. PDB_SET_INPUT_TRIGGER ioctl(PDB, PDB_SET_INPUT_TRIGGER, PDB_TRIG_T0); This code sets timer 0 as the trigger source. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-489...
Page 608 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PDB_SET_TRIGGER_A_ENABLE command is implemented as a macro. Example 5-357. PDB_SET_TRIGGER_A_ENABLE ioctl(PDB, PDB_SET_TRIGGER_A_ENABLE, NULL); This code enables the PDB Trigger A output. 5-490 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 609 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PDB_SET_TRIGGER_A_DISABLE command is implemented as a macro. Example 5-358. PDB_SET_TRIGGER_A_DISABLE ioctl(PDB, PDB_SET_TRIGGER_A_DISABLE, NULL); This code disables the PDB Trigger A output. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-491...
Page 610 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PDB_SET_TRIGGER_B_ENABLE command is implemented as a macro. Example 5-359. PDB_SET_TRIGGER_B_ENABLE ioctl(PDB, PDB_SET_TRIGGER_B_ENABLE, NULL); This code enables the PDB Trigger B output. 5-492 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 611 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PDB_SET_TRIGGER_B_DISABLE command is implemented as a macro. Example 5-360. PDB_SET_TRIGGER_B_DISABLE ioctl(PDB, PDB_SET_TRIGGER_B_DISABLE, NULL); This code disables the PDB Trigger B output. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-493...
Page 612 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PDB_WRITE_DELAYA command is implemented as a macro. Example 5-361. PDB_WRITE_DELAYA ioctl(PDB, PDB_WRITE_DELAYA, 200); This code configures PDB module to generate Trigger A pulse after 200 counter clocks. 5-494 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 613 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PDB_WRITE_DELAYA command is implemented as a macro. Example 5-362. PDB_WRITE_DELAYA ioctl(PDB, PDB_WRITE_DELAYA, 400); This code configures PDB module to generate Trigger B pulse after 400 counter clocks. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-495...
Page 614 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PDB_WRITE_MOD command is implemented as a macro. Example 5-363. PDB_WRITE_MOD ioctl(PDB, PDB_WRITE_MOD, 30000); This code configures PDB module to end cycle after 30000 clocks. 5-496 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 615 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PDB_READ_COUNTER_REG command is implemented as a macro. Example 5-364. PDB_READ_COUNTER_REG UWord16 count; count = ioctl(PDB, PDB_READ_COUNTER_REG, NULL); This code reads the immediate counter value of PDB. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-497...
Page 616: Pdb Driver Applications
LED diode PWM5 indicates that the main loop is working correctly. LED diode PWM4 indicates that the PWM module is reloading correctly. LED diode PWM3 indicates that in the PDB module is delayA and delayB working correctly. 5-498 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 617: Quadrature Decoder Driver
Decoder #0 (Decoder0_BASE) 0xF180 0xF180 Decoder #1 (Decoder1_BASE) 0xF190 5.13.2.1 API Definition The following header files are needed in order to use the Quadrature Decoder device driver: Required Header File(s): #include “qs.h” #include “decoder.h” FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-499...
Page 618 Int16 scaleDiffPosCoef; UInt16 scalePosCoef; Int16 normDiffPosCoef; Int16 normPosCoef; }decoder_sEncScale; typedef struct UWord16 Index : 1; UWord16 PhaseB : 1; UWord16 PhaseA : 1; UWord16 Reserved : 13; }decoder_sEncSignals; typedef union decoder_sEncSignals EncSignals; UWord16 Value; }decoder_uEncSignals; 5-500 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 619 Table 5-404. decoder_sEncSignals Data Structure Members Member Type Description Index UWord16 : 1 A bit reflecting the state of the Encoder Index Sig- nal. PhaseB UWord16 : 1 A bit reflecting the state of the Encoder PhaseB Signal. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-501...
Page 620: Configuration Items
Note: inout parameters are typically input pointer variables in which the caller passes the address of a pre-allocated data structure to a function. The function stores its results within that data structure. The actual value of the inout pointer parameter is not changed. 5-502 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 621 DEC_HOME | None Disables the selected Quadrature DEC_INDEX | Decoder interrupts. DEC_WDTIMEOUT DEC_HOME_INT DEC_ENABLE / None Interrupt enable or disable for DEC_INDEX_PULSE_INT DEC_DISABLE individual interrupt sources. DEC_WATCHDOG_INT The same operation possible with DEC_INT_ENABLE / DISABLE FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-503...
Page 622 Sets the Filter Interval Register with the desired value. DEC_WRITE_WATCHDOG_TIMEOUT UWord16 None Sets the Watchdog Time-out Reg- ister with the desired value. DEC_READ_POSITION_DIFFERENCE NULL Word16 Returns the content of the Posi- tion Difference Counter Register. 5-504 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 623 Returns the content of the Control Register. DEC_CALCULATE_SCALE_COEF decoder_sEncScale* None Calculates the scaling coefficients needed for the correct functional- ity of DEC_GET_SCALED_POSITION DEC_GET_SCALED_POSITION _DIFFERENCE commands (i.e. this command must be executed before the execution of the above mentioned commands). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-505...
Page 624: Detailed Api Specification
Note - Causes to copy all Quadrature Decoder counter registers’ contents to their corresponding hold registers. 5.13.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the ioctl commands usage. 5-506 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 625 DEC_0, DEC_INIT, NULL ); This code initializes Quadrature Decoder 0 module with the initialization values from appconfig.h. ioctl( DEC_1, DEC_INIT, NULL ); This code initializes Quadrature Decoder 1 module with the initialization values from appconfig.h. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-507...
Page 626 DEC_0, DEC_INT_ENABLE, DEC_INDEX ); This code enables the Quadrature Decoder 0 Index Pulse interrupt. ioctl( DEC_1, DEC_INT_ENABLE, DEC_INDEX | DEC_WDTIMEOUT ); This code enables the Quadrature Decoder 1 Index Pulse and Watchdog Timeout interrupts. 5-508 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 627 DEC_0, DEC_INT_DISABLE, DEC_HOME ); This code disables the Quadrature Decoder 0 Home Signal interrupt. ioctl( DEC_1, DEC_INT_DISABLE, DEC_INDEX | DEC_WDTIMEOUT ); This code disables the Quadrature Decoder 1 Index Pulse and Watchdog Timeout interrupts. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-509...
Page 628 Range Issues: None. Special Issues: None. Design/Implementation: The DEC_INT_REQUEST_CLEAR ioctl command is implemented as a macro. Example 5-368. DEC_INT_REQUEST_CLEAR ioctl( DEC_0, DEC_INT_REQUEST_CLEAR, DEC_INDEX ); This code clears the Quadrature Decoder 0 Index Pulse interrupt request flag. 5-510 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 629 Range Issues: None. Special Issues: None. Design/Implementation: The DEC_CLEAR_HOME_INT_REQUEST ioctl command is implemented as a macro. Example 5-369. DEC_CLEAR_HOME_INT_REQUEST ioctl( DEC_0, DEC_CLEAR_HOME_INT_REQUEST, NULL ); This code clears the Quadrature Decoder 0 HOME signal interrupt request flag. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-511...
Page 630 Range Issues: None. Special Issues: None. Design/Implementation: The DEC_CLEAR_INDEX_PULSE_INT_REQUEST ioctl command is implemented as a macro. Example 5-370. DEC_CLEAR_INDEX_PULSE_INT_REQUEST ioctl( DEC_0, DEC_CLEAR_INDEX_PULSE_INT_REQUEST, NULL ); This code clears the Quadrature Decoder 0 INDEX pulse interrupt request flag. 5-512 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 631 Range Issues: None. Special Issues: None. Design/Implementation: The DEC_CLEAR_WATCHDOG_INT_REQUEST ioctl command is implemented as a macro. Example 5-371. DEC_CLEAR_WATCHDOG_INT_REQUEST ioctl( DEC_0, DEC_CLEAR_WATCHDOG_INT_REQUEST, NULL ); This code clears the Quadrature Decoder 0 watchdog time-out interrupt request flag. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-513...
Page 632 This code enables initialization of the Quadrature Decoder 0 position counter by the HOME signal. ioctl( DEC_1, DEC_HOME_TRIGGERED_INIT, DEC_DISABLE ); This code disables initialization of the Quadrature Decoder 1 position counter by the HOME signal. 5-514 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 633 This code sets the positive going edge of the HOME signal to initialize the Quadrature Decoder 0 position counters. ioctl( DEC_1, DEC_HOME_EDGE, DEC_NEGATIVE ); This code sets the negative going edge of the HOME signal to initialize the Quadrature Decoder 1 position counters. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-515...
Page 634 Special Issues: Use of this ioctl command may unintentionally result in clearing an interrupt flag. Design/Implementation: The DEC_SOFTWARE_TRIGGERED_INIT ioctl command is implemented as a macro. Example 5-374. DEC_SOFTWARE_TRIGGERED_INIT ioctl( DEC_0, DEC_SOFTWARE_TRIGGERED_INIT, NULL ); This code initializes the Quadrature Decoder 0 position counters. 5-516 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 635 Design/Implementation: The DEC_DIRECTION_COUNTING_ENABLE ioctl command is implemented as a macro. Example 5-375. DEC_DIRECTION_COUNTING_ENABLE ioctl( DEC_0, DEC_DIRECTION_COUNTING_ENABLE, DEC_REVERSE ); This code reverses the direction of counting of quadrature signals for the Quadrature Decoder 0 module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-517...
Page 636 Example 5-376. DEC_SINGLE_PHASE_COUNT ioctl( DEC_0, DEC_SINGLE_PHASE_COUNT, DEC_ENABLE ); This code bypasses the Quadrature Decoder 0 logic. ioctl( DEC_1, DEC_SINGLE_PHASE_COUNT, DEC_DISABLE ); This code sets the Quadrature Decoder 1 to use the standard logic. 5-518 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 637 DEC_0, DEC_INDEX_TRIGGERED_INIT, DEC_ENABLE ); This code enables initialization of Quadrature Decoder 0 position counter by the INDEX pulse. ioctl( DEC_1, DEC_INDEX_TRIGGERED_INIT, DEC_DISABLE ); This code disables initialization of Quadrature Decoder 1 position counter by the INDEX pulse. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-519...
Page 638 This code causes the positive going edge of the HOME signal to initialize the Quadrature Decoder 0 position counters. ioctl( DEC_1, DEC_INDEX_EDGE, DEC_NEGATIVE ); This code causes the negative going edge of the HOME signal to initialize the Quadrature Decoder 1 position counters. 5-520 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 639 Design/Implementation: The DEC_WATCHDOG ioctl command is implemented as a macro. Example 5-379. DEC_WATCHDOG ioctl( DEC_0, DEC_WATCHDOG, DEC_ENABLE ); This code enables the Quadrature Decoder 0 watchdog timer. ioctl( DEC_1, DEC_WATCHDOG, DEC_DISABLE ); This code disables the Quadrature Decoder 1 watchdog timer. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-521...
Page 640 Special Issues: Use of this ioctl command may unintentionally result in clearing an interrupt flag. Design/Implementation: The DEC_SWITCH_MATRIX ioctl command is implemented as a macro. Example 5-380. DEC_SWITCH_MATRIX ioctl(DEC_0, DEC_SWITCH_MATRIX, DEC_MODE_1); This code sets Mode1 for the Quadrature Decoder 0 module operation. 5-522 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 641 DEC_0, DEC_WRITE_FILTER, filterValue ); This code writes new a value to the Quadrature Decoder 0 Filter Interval Register. ioctl( DEC_1, DEC_WRITE_FILTER, 0x007f ); This code writes 0x007f to the Quadrature Decoder 1 Filter Interval Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-523...
Page 642 DEC_0, DEC_WRITE_WATCHDOG_TIMEOUT, timeOutValue ); This code writes a new value to the Quadrature Decoder 0 Watchdog Time-out Register. ioctl( DEC_1, DEC_WRITE_WATCHDOG_TIMEOUT, 0x007f ); This code writes 0x007f to the Quadrature Decoder 1 Watchdog Time-out Register. 5-524 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 643 This code stores the content of the Quadrature Decoder 0 Position Difference Counter Register to variable posDiff. posDiff = ioctl( DEC_1, DEC_READ_POSITION_DIFFERENCE, NULL ); This code stores the content of the Quadrature Decoder 1 Position Difference Counter Register to variable posDiff. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-525...
Page 644 This code stores the content of the Quadrature Decoder 0 Revolution Counter Register to variable revNum. revNum = ioctl( DEC_1, DEC_READ_REVOLUTION, NULL ); This code stores the content of the Quadrature Decoder 1 Revolution Counter Register to variable revNum. 5-526 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 645 DEC_0, DEC_WRITE_REVOLUTION, revNum ); This code writes a new value to the Quadrature Decoder 0 Revolution Counter Register. ioctl( DEC_1, DEC_WRITE_REVOLUTION, 0x0fff ); This code writes 0x0fff to the Quadrature Decoder 1 Revolution Counter Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-527...
Page 646 This code stores the content of the Quadrature Decoder 0 Position Counter Registers to variable positionReg32. ioctl( DEC_1, DEC_READ_POSITION, &positionReg32 ); This code stores the content of the Quadrature Decoder 1 Position Counter Registers to variable positionReg32. 5-528 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 647 DEC_0, DEC_WRITE_POSITION, position ); This code writes a new value to the Quadrature Decoder 0 Position Counter Registers. ioctl( DEC_1, DEC_WRITE_POSITION, 0x0123ffff ); This code writes 0x0123ffff to the Quadrature Decoder 1 Position Counter Registers. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-529...
Page 648 DEC_0, DEC_WRITE_INIT_STATE, position ); This code writes a new value to the Quadrature Decoder 0 Initialization Registers. ioctl( DEC_1, DEC_WRITE_INIT_STATE, 0x0123ffff ); This code writes 0x0123ffff to the Quadrature Decoder 1 Initialization Registers. 5-530 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 649 Design/Implementation: The DEC_READ_MONITOR_REG ioctl command is implemented as a macro. Example 5-389. DEC_READ_MONITOR_REG UWord16 monitor; monitor = ioctl( DEC_0, DEC_READ_MONITOR_REG, NULL ); This code stores the content of the Quadrature Decoder 0 Input Monitor Register to variable monitor. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-531...
Page 650 = ioctl( DEC_0, DEC_GET_RAW_ENCSIGNALS, NULL ); This code stores the raw version of the INDEX, PHASEB and PHASEA encoder signals from the Quadrature Decoder 0 Input Monitor Register to variable encSignals. 5-532 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 651 = ioctl( DEC_0, DEC_GET_FILTERED_ENCSIGNALS,\ NULL ); This code stores the filtered version of the INDEX, PHASEB and PHASEA encoder signals from the Quadrature Decoder 0 Input Monitor Register to variable encSignals. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-533...
Page 652 DEC_1, DEC_READ_HOLD_DATA_REGS, &holdDataRegs ); This code holds and stores the content of the Quadrature Decoder 1 Position Counter Registers, the Position Difference Register and the Revolution Counter Register to the holdDataRegs structure members. 5-534 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 653 Design/Implementation: The DEC_READ_MONITOR_REG ioctl command is implemented as a macro. Example 5-393. DEC_READ_MONITOR_REG UWord16 cntrl; cntrl = ioctl( DEC_0, DEC_READ_MONITOR_REG, NULL ); This code stores the content of the Quadrature Decoder 0 Control Register to the variable cntrl. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-535...
Page 654 = 1024; /* Encoder pulses per revolution */ decEncScale.RevolutionScale = 1; /* range +/-2PI to be represented by 16bit value */ ioctl( DEC_0, DEC_CALCULATE_SCALE_COEF, &decEncScale ); This code precalculates the scaling coefficients, based on specified parameters, for the subsequent usage. 5-536 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 655 /* suppose: Revolution Reg=0x0125 and Position Regs=0x00000800 */ absPos = ioctl(DEC_0,DEC_GET_SCALED_POSITION,&decEncScale); /* absPos=0x0125.7fff, i.e. result represents 125.5 revolutions */ This code illustrates the usage of the DEC_GET_SCALED_POSITION command for the Quadrature Decoder 0 by one example. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-537...
Page 656 /* suppose: Position Difference Reg=2048 */ relPos = ioctl(DEC_0,DEC_GET_SCALED_POSITION_DIFFERENCE, \ &decEncScale); /* relPos=0x3fff, i.e. result represents 0.5 revolutions */ This code illustrates the usage of the DEC_GET_SCALED_POSITION_DIFFERENCE command for the Quadrature Decoder 0 by one example. 5-538 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 657 Range Issues: None. Special Issues: None. Design/Implementation: The DEC_HOME_INT ioctl command is implemented as a macro. Example 5-397. DEC_HOME_INT ioctl( DEC_0, DEC_HOME_INT, DEC_ENABLE ); This code enables the Quadrature Decoder 0 HOME signal interrupt. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-539...
Page 658 Example 5-398. DEC_INDEX_PULSE_INT ioctl( DEC_0, DEC_INDEX_PULSE_INT, DEC_ENABLE ); This code enables the Quadrature Decoder 0 INDEX pulse interrupt. ioctl( DEC_1, DEC_INDEX_PULSE_INT, DEC_DISABLE ); This code disables the Quadrature Decoder 1 INDEX pulse interrupt. 5-540 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 659 Example 5-399. DEC_WATCHDOG_INT ioctl( DEC_0, DEC_WATCHDOG_INT, DEC_ENABLE ); This code enables the Quadrature Decoder 0 watchdog time-out interrupt. ioctl( DEC_1, DEC_WATCHDOG_INT, DEC_DISABLE ); This code disables the Quadrature Decoder 1 watchdog time-out interrupt. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-541...
Page 660: Quadrature Decoder Driver Application
JG5/ 2-3, 5-6, 8-9 MC56F8346CB with LMIDC yellow LED Secondary JG5/ 2-3, 5-6, 8-9 MC56F8357EVM with LMIDC red LED Secondary JG5/ 2-3, 5-6, 8-9 MC56F8367EVM with LMIDC red LED Secondary JG5/ 2-3, 5-6, 8-9 5-542 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 661 Example 5-400. Quadrature Decoder Driver Application - appconfig.h /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * File Name: appconfig.h * Description: file for static configuration of the application...
Page 662 Bypass Quadrature Decoder Logic: No Watchdog timeout: 16.667 ms Filter interval period: 66.667 ms Interrupts: Home pulse: Disabled Index pulse: Disabled Watchdog timeout: Disabled #define DEC_0_DECCR_INIT 0x0000 #define DEC_0_FIR_INIT 0x0003 End of autogenerated code ********************************************************************** ..*/ #endif 5-544 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 663 Example 5-401. Quadrature Decoder Driver Application - main.c /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * FILE NAME: main.c * DESCRIPTION: Sample application demonstrating the use of Quadrature Decoder driver Each new revolution is indicated by toggling the state of the red LED;...
Page 664 /* configure Interrupt Controller (IPR) */ ioctl(INTC, INTC_INIT, NULL); /* enable maskable interrupts in Status Register (SR), bits I1 and I0 */ archEnableInt(); while(1) /* read periodically Position Register (L,U) */ ioctl( DEC_0, DEC_READ_POSITION, &PositionReg32 ); return; 5-546 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 665: Pwm Driver
PWM Frequency = 1 / PWM Period 5.14.2.1.3 Deadtime Calculation deadtime = (PWM Deadtime Reg. * PWM Clock Period) - 1 IP Bus Clock (the one IP Bus Clock is not subtracted when PWM Prescaler is 1) FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-547...
Page 666: Api Definition
Word16 pwmChannel_3_Value; Word16 pwmChannel_4_Value; Word16 pwmChannel_5_Value; }pwm_sIndependentValues; typedef struct pwm_tPWMSignalMask SoftwareControlled; pwm_tPWMSignalMask OutputControl; }pwm_sOutputControl; typedef struct Word16 DutyCycle; UWord16 Vlmode; }pwm_sUpdateValueSetVlmode; typedef UWord16 pwm_tPWMChannelSwap; typedef struct pwm_tPWMSignalMask Mask; pwm_tPWMChannelSwap Swap; }pwm_sChannelControl; typedef UWord16 pwm_tPWMSignalMask; 5-548 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 667 A data value representing a duty cycle or the desired value of the corresponding PWM Value register. pwmChannel_5_Value Word16 A data value representing a duty cycle or the desired value of the corresponding PWM Value register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-549...
Page 668: Configuration Items
Initial value of the PWM Fault Control Register. PWM_x_PMOUT_INIT UWord16 Initial value of the PWM Output Control Reg- ister. PWM_x_PWMCM_INIT UWord16 Initial value of the PWM Counter Modulo Register. PWM_x_PWMVAL0_INIT UWord16 Initial value of the PWM Value Register 0. 5-550 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 669 Contents of the PWM Filter Registers 0-3. MC56F800x PWM_x_FFILT0_INIT PWM_x_FFILT1_INIT PWM_x_FFILT2_INIT PWM_x_FFILT3_INIT Note - PWM_x should be replaced by PWM_A for the PWM A module and PWM_B for the PWM B module or by the PWM on MC56F80xx. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-551...
Page 670: Api Specification
( item1 | item2 | item3 ) & intersection of items is allowed ( item1 & item2 & item3 ) Table 5-453. ioctl commands param Return Description PWM_INIT NULL None Initializes PWM module by data from configuration file (appconfig.h). 5-552 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 671 Sets the manual fault clear- PWM_FAULT_2 / PWM_FAULT_3 ing of FAULTx pin fault. PWM_CLEAR_FAULT_FLAG PWM_FAULT_0 / PWM_FAULT_1 / None Clears corresponding PWM_FAULT_2 / PWM_FAULT_3 FAULTx Pin Flag. PWM_OUTPUT_PAD PWM_ENABLE / PWM_DISABLE None Output Pad enable or dis- able. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-553...
Page 672 (INDISMAP1 register). PWM_WRITE_DISABLE_MAPPING_ UWord16 None Determines which PWM pins REG2 are disabled by the fault detection decoder (INDISMAP2 register). PWM_SET_ALIGNMENT PWM_EDGE / PWM_CENTER None Determines whether all PWM channels will use edge- or center-aligned waveforms. 5-554 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 673 This command should be used in the independent mode. In complementary mode the masked channels are set to 0% duty cycle and the corresponding comple- mentary channels are there- fore set to 100% duty cycle. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-555...
Page 674 Port Register. PWM_GET_CURRENT_STATUS_ NULL UWord16 Returns values of the three INPUTS current status inputs. PWM_GET_FAULT_INPUTS NULL UWord16 Returns values of the four fault inputs. PWM_GET_FAULT_INPUT_0 NULL UWord16 Returns value of the fault input 0. 5-556 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 675 Word16 None Recalculates the input value of duty cycle (in percentage) with respect to the PWM modulus and writes the resulting value to the PWM Value Register 4. The LDOK bit is set afterwards. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-557...
Page 676 100% duty cycle. PWM_DEBUG_OPERATION PWM_STOP / PWM_RUN None Enables or disables PWM operation during debug mode. PWM_WAIT_OPERATION PWM_STOP / PWM_RUN None Enables or disables PWM operation during WAIT mode. 5-558 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 677 PWM_SET_ACTIVE_LOW_FAULTS MC56F802x/3x and only on NULL None Disables SYNC input/output MC56F800x feature, reverts pin to PWM_DISABLE_SYNC FAULT2 operation. MC56F802x/3x and only on NULL None Enables SYNC signal output MC56F800x on FAULT2 pin. PWM_ENABLE_SYNC_OUT FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-559...
Page 678: Detailed Api Specification
Note - ensure that this ioctl call cannot be interrupted. 5.14.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the usage of the ioctl commands. 5-560 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 679 PWM_INIT, NULL); This code initializes the PWM A module by the initialization values taken from appconfig.h. ioctl(PWM_B, PWM_INIT, NULL); This code initializes the PWM B module by the initialization values taken from appconfig.h. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-561...
Page 680 Special Issues: Use of this ioctl command may unintentionally result in clearing an interrupt flag. Design/Implementation: PWM_SET_RELOAD_FREQUENCY ioctl command implemented as a macro. Example 5-403. PWM_SET_RELOAD_FREQUENCY ioctl(PWM_A, SET_RELOAD_FREQUENCY, PWM_RELOAD_OPPORTUNITY_2); This code sets the PWM A load frequency to every 2 PWM opportunities. 5-562 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 681 Design/Implementation: The PWM_HALF_CYCLE_RELOAD ioctl command is implemented as a macro. Example 5-404. PWM_HALF_CYCLE_RELOAD ioctl(PWM_A, PWM_HALF_CYCLE_RELOAD, PWM_ENABLE); This code enables half-cycle reload for the PWM A module. ioctl(PWM_B, PWM_HALF_CYCLE_RELOAD, PWM_DISABLE); This code disables half-cycle reload for the PWM B module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-563...
Page 682 This code selects the PWM B module Value Register 3 for the PWM2 and PWM3 pins in top/bottom correction, and the PWM Value Register 5 for the PWM4 and PWM5 pins in top/bottom correction. 5-564 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 683 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-565...
Page 684 Design/Implementation: The PWM_SET_PRESCALER ioctl command is implemented as a macro. Example 5-406. PWM_SET_PRESCALER ioctl(PWM_A, PWM_SET_PRESCALER, PWM_PRESCALER_DIV_2); This code sets the PWM A clock frequency as one half of the IP Bus frequency. ioctl(PWM_B, PWM_SET_PRESCALER, PWM_PRESCALER_DIV_1); 5-566 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 685 This code sets the PWM B clock frequency equal to the IP Bus frequency. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-567...
Page 686 Design/Implementation: The PWM_RELOAD_INT ioctl command is implemented as a macro. Example 5-407. PWM_RELOAD_INT ioctl(PWM_A, PWM_RELOAD_INT, PWM_ENABLE); This code enables a PWM A reload interrupt request. ioctl(PWM_B, PWM_RELOAD_INT, PWM_DISABLE); This code disables any PWM B reload interrupt request. 5-568 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 687 Example 5-408. PWM_SET_CURRENT_SENSING ioctl(PWM_B,PWM_SET_CURRENT_SENSING,PWM_CORRECTION_DURING_CYCLE); This code sets the PWM B sample correction on pins IS1, IS2 and IS3 at the half-cycle in center-aligned operation or at the end of the cycle in edge-aligned operation. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-569...
Page 688 Design/Implementation: The PWM_DEVICE ioctl command is implemented as a macro. Example 5-409. PWM_DEVICE ioctl(PWM_A, PWM_DEVICE, PWM_ENABLE); This code enables the PWM A generator and the corresponding pins. ioctl(PWM_B, PWM_DEVICE, PWM_DISABLE); This code disables the PWM B generator and the corresponding pins. 5-570 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 689 This command clears the PWMF bit (Bit 4) in the PWM Control Register. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The PWM_CLEAR_RELOAD_FLAG ioctl command is implemented as a macro. Example 5-410. PWM_CLEAR_RELOAD_FLAG ioctl(PWM_A, PWM_CLEAR_RELOAD_FLAG, NULL); This code clears the PWM A reload flag. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-571...
Page 690 Special Issues: Use of this ioctl command may unintentionally result in clearing an interrupt flag. Design/Implementation: The PWM_LOAD_OK ioctl command is implemented as a macro. Example 5-411. PWM_LOAD_OK ioctl(PWM_A, PWM_LOAD_OK, NULL); This code loads prescaler, modulus and PWM values of PWM A. 5-572 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 691 Design/Implementation: The PWM_FAULT_INT_ENABLE ioctl command is implemented as a macro. Example 5-412. PWM_FAULT_INT_ENABLE ioctl(PWM_A, PWM_FAULT_INT_ENABLE, PWM_FAULT_1); This code enables a PWM A FAULT1 Pin interrupt request. ioctl(PWM_B, PWM_FAULT_INT_ENABLE, PWM_FAULT_3); This code enables a PWM B FAULT3 Pin interrupt request. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-573...
Page 692 Design/Implementation: The PWM_FAULT_INT_DISABLE ioctl command is implemented as a macro. Example 5-413. PWM_FAULT_INT_DISABLE ioctl(PWM_A, PWM_FAULT_INT_DISABLE, PWM_FAULT_1); This code disables any PWM A FAULT1 Pin interrupt request. ioctl(PWM_B, PWM_FAULT_INT_DISABLE, PWM_FAULT_0); This code disables a PWM B FAULT0 Pin interrupt request. 5-574 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 693 Example 5-414. PWM_SET_AUTOMATIC_FAULT_CLEAR ioctl(PWM_A, PWM_SET_AUTOMATIC_FAULT_CLEAR, PWM_FAULT_1); This code sets automatic clearing of a FAULT1 Pin fault on PWM A. ioctl(PWM_B, PWM_SET_AUTOMATIC_FAULT_CLEAR, PWM_FAULT_0); This code sets automatic clearing of FAULT0 Pin fault on PWM B. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-575...
Page 694 Example 5-415. PWM_SET_MANUAL_FAULT_CLEAR ioctl(PWM_A, PWM_SET_MANUAL_FAULT_CLEAR, PWM_FAULT_1); This code sets manual clearing of a FAULT1 Pin fault on PWM A. ioctl(PWM_B, PWM_SET_MANUAL_FAULT_CLEAR, PWM_FAULT_3); This code sets manual clearing of FAULT3 Pin fault on PWM B. 5-576 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 695 Design/Implementation: The PWM_CLEAR_FAULT_FLAG ioctl command is implemented as a macro. Example 5-416. PWM_CLEAR_FAULT_FLAG ioctl(PWM_A, PWM_CLEAR_FAULT_FLAG, PWM_FAULT_1); This code clears the FAULT1 Pin fault flag on PWM A. ioctl(PWM_B, PWM_CLEAR_FAULT_FLAG, PWM_FAULT_0); This code clears FAULT0 Pin fault flag on PWM B. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-577...
Page 696 Design/Implementation: The PWM_OUTPUT_PAD ioctl command is implemented as a macro. Example 5-417. PWM_OUTPUT_PAD ioctl(PWM_A, PWM_OUTPUT_PAD, PWM_ENABLE); This code enables the PWM A output pads. ioctl(PWM_B, PWM_OUTPUT_PAD, PWM_DISABLE); This code disables the PWM B output pads. 5-578 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 697 MC_PWM_SIGNAL_2 | MC_PWM_SIGNAL_5); This code enables PWM2 and PWM5 pins of PWM B to be controlled by software. ioctl(PWM_B, PWM_OUTPUT_SOFTWARE_CONTROL, MC_PWM_NO_SIGNALS); This code disables all PWM pins of PWM B to be controlled by software. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-579...
Page 698 = MC_PWM_SIGNAL_2 | MC_PWM_SIGNAL_4; ioctl(PWM_A, PWM_OUTPUT_CONTROL, tempSignals); This code activates PWM2 and PWM4 pins of PWM A. ioctl(PWM_B, PWM_OUTPUT_CONTROL, MC_PWM_SIGNAL_2 | MC_PWM_SIGNAL_4); This code activates PWM2 and PWM4 pins of PWM B. 5-580 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 699 = 0x7fff; ioctl(PWM_A, PWM_SET_MODULO, modulo); This code writes a new value to the PWM A Counter Modulo Register. ioctl(PWM_B, PWM_SET_MODULO, 0x0fff); This code writes 0x0fff to the PWM B Counter Modulo Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-581...
Page 700 This code stores the content of the PWM A Counter Modulo Register to the modulo variable. modulo = ioctl(PWM_B, PWM_GET_MODULO, NULL); This code stores the content of the PWM B Counter Modulo Register to the modulo variable. 5-582 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 701 Example 5-422. PWM_SET_DEADTIME UWord16 deadtime; deadtime = 0x00ff; ioctl(PWM_A, PWM_SET_DEADTIME, deadtime); This code writes a new value to the PWM A Deadtime Register. ioctl(PWM_B, PWM_SET_DEADTIME, 0x007f); This code writes 0x007f to the PWM B Deadtime Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-583...
Page 702 = 0x00ff; ioctl(PWM_A, PWM_SET_DEADTIME_0, deadtime); This code writes a new value to the PWM A Deadtime Register 0. ioctl(PWM_B, PWM_SET_DEADTIME_0, 0x007f); This code writes 0x007f to the PWM B Deadtime Register 0. 5-584 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 703 = 0x00ff; ioctl(PWM_A, PWM_SET_DEADTIME_1, deadtime); This code writes a new value to the PWM A Deadtime Register 1. ioctl(PWM_B, PWM_SET_DEADTIME_1, 0x007f); This code writes 0x007f to the PWM B Deadtime Register 1. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-585...
Page 704 UWord16 dismap; dismap = 0x00ff; ioctl(PWM_A, PWM_WRITE_DISABLE_MAPPING_REG1, dismap); This code writes a new value to the PWM A Disable Mapping Register 1 which disables all faults on PWM2 and PWM3 pins. ioctl(PWM_B, PWM_WRITE_DISABLE_MAPPING_REG1, 0xfff0); 5-586 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 705 This code writes 0xfff0 to the PWM B Disable Mapping Register 1 to disable all faults on PWM0 pin. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-587...
Page 706 This code writes a new value to the PWM A Disable Mapping Register 2 to disable Fault2 and Fault3 on PWM4 pin. ioctl(PWM_B, PWM_WRITE_DISABLE_MAPPING_REG2, PWM_ZERO_MASK); This code writes 0x0000 to the PWM B Disable Mapping Register 2 to disable all faults on PWM4 and PWM5 pins. 5-588 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 707 Design/Implementation: The PWM_SET_ALIGNMENT ioctl command is implemented as a macro. Example 5-427. PWM_SET_ALIGNMENT ioctl(PWM_A, PWM_SET_ALIGNMENT, PWM_ALIGN_EDGE); This code sets PWM A channels to use edge-aligned waveforms. ioctl(PWM_B, PWM_SET_ALIGNMENT, PWM_ALIGN_CENTER); This code sets PWM B channels to use center-aligned waveforms. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-589...
Page 708 This code sets PWM A channel zero to one, to the negative top-side polarity. ioctl(PWM_B, PWM_SET_NEG_TOP_SIDE_POLARITY, PWM_CHANNEL_23 | PWM_CHANNEL_45); This code sets PWM B channels two to three and four to five, to the negative top-side polarity. 5-590 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 709 Example 5-429. PWM_SET_NEG_BOTTOM_SIDE_POLARITY ioctl(PWM_A, PWM_SET_NEG_BOTTOM_SIDE_POLARITY, PWM_CHANNEL_01); This code sets PWM A channel zero to one, to the negative bottom-side polarity. ioctl(PWM_B, PWM_SET_NEG_BOTTOM_SIDE_POLARITY, PWM_ZERO_MASK); This code sets all three PWM B channel to the positive bottom-side polarity. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-591...
Page 710 Example 5-430. PWM_SET_INDEPENDENT_OPERATION ioctl(PWM_A, PWM_SET_INDEPENDENT_OPERATION, PWM_CHANNEL_45); This code sets PWM A channel four to five as independent PWMs. ioctl(PWM_B, PWM_SET_INDEPENDENT_OPERATION, PWM_ZERO_MASK); This code sets all PWM B channels as complementary PWM pairs. 5-592 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 711 Example 5-431. PWM_SET_INDEPENDENT_MODE ioctl(PWM_A, PWM_SET_INDEPENDENT_MODE, PWM_CHANNEL_45); This code sets PWM A channel four to five as independent PWMs. ioctl(PWM_B, PWM_SET_INDEPENDENT_MODE, PWM_CHANNEL_01 | PWM_CHANNEL_23 | PWM_CHANNEL_45); This code sets all PWM B channels as independent PWMs. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-593...
Page 712 PWM_SET_COMPLEMENTARY_MODE, PWM_CHANNEL_01); This code sets PWM A channel zero to one as complementary PWM pair. ioctl(PWM_B, PWM_SET_COMPLEMENTARY_MODE, PWM_CHANNEL_01 | PWM_CHANNEL_23 | PWM_CHANNEL_45); This code sets all PWM B channels as complementary PWM pairs. 5-594 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 713 Special Issues: The WP bit can be cleared only by a reset. Design/Implementation: The PWM_SET_WRITE_PROTECT ioctl command is implemented as a macro. Example 5-433. PWM_SET_WRITE_PROTECT ioctl(PWM_A, PWM_SET_WRITE_PROTECT, NULL); This code write-protects corresponding PWM A registers. ioctl(PWM_B, PWM_SET_WRITE_PROTECT, NULL); This code write-protects corresponding PWM B registers. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-595...
Page 714 Design/Implementation: The PWM_HARDWARE_ACCELERATION ioctl command is implemented as a macro. Example 5-434. PWM_HARDWARE_ACCELERATION ioctl(PWM_A, PWM_HARDWARE_ACCELERATION, PWM_ENABLE); This code enables PWM A generator and the corresponding pins. ioctl(PWM_B, PWM_HARDWARE_ACCELERATION, PWM_DISABLE); This code disables PWM B generator and the corresponding pins. 5-596 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 715 This code masks PWM2 and PWM3 logical channels of the PWM A module. ioctl(PWM_B, PWM_SET_CHANNEL_MASK, MC_PWM_SIGNAL_2 | MC_PWM_SIGNAL_5); This code masks PWM2 and PWM5 logical channels of the PWM B module. ioctl(PWM_B, PWM_SET_CHANNEL_MASK, MC_PWM_NO_SIGNALS); This code unmasks all PWM logical channels of the PWM B module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-597...
Page 716 This code specifies that when PWM B Value Register 0 is loaded, this value is also copied to the PWM Value Registers 1 to 3 (these four PWM Value Registers contain the same value). 5-598 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 717 Design/Implementation: The PWM_SET_SWAP ioctl command is implemented as a macro. Example 5-437. PWM_SET_SWAP ioctl(PWM_A, PWM_SET_SWAP, PWM_CHANNEL_45); This code swaps PWM A channel four and PWM A channel five. ioctl(PWM_B, PWM_SET_SWAP, PWM_ZERO_MASK); This code sets no swap between PWM B channels. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-599...
Page 718 = 0x4000; ioctl(PWM_A, PWM_WRITE_VALUE_REG_0, pulse); This code writes a new value to the PWM A Value Register 0. ioctl(PWM_B, PWM_WRITE_VALUE_REG_4, 0x7fff); This code writes 0x7fff to the PWM B Value Register 4. 5-600 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 719 Example 5-439. PWM_WRITE_VALUE_REGS_COMPL pwm_sComplementaryValues compVal; compVal.pwmChannel_0_Value = 0x2000; compVal.pwmChannel_2_Value = 0x4000; compVal.pwmChannel_4_Value = 0x6000; ioctl(PWM_A, PWM_WRITE_VALUE_REGS_COMPL, &compVal); This code writes the new values (pulse widths) to the PWM A Value Registers 0, 2 and 4. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-601...
Page 720 = 0x3000; indepVal.pwmChannel_3_Value = 0x4000; indepVal.pwmChannel_4_Value = 0x5000; indepVal.pwmChannel_5_Value = 0x6000; ioctl(PWM_A, PWM_WRITE_VALUE_REGS_INDEP, &indepVal); This code writes the new values (pulse widths) to the PWM A Value Registers 0, 1, 2, 3, 4 and 5. 5-602 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 721 Example 5-441. PWM_READ_FAULT_STATUS_REG UWord16 statusWord; statusWord = ioctl(PWM_A, PWM_READ_FAULT_STATUS_REG, NULL); This code stores the content of the PWM A Fault Status & Acknowledge Register to the variable statusWord. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-603...
Page 722 Design/Implementation: The PWM_READ_COUNTER_REG ioctl command is implemented as a macro. Example 5-442. PWM_READ_COUNTER_REG UWord16 counter; counter = ioctl(PWM_A, PWM_READ_COUNTER_REG, NULL); This code stores the content of the PWM A Counter Register to the variable counter. 5-604 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 723 Design/Implementation: The PWM_READ_CONTROL_REG ioctl command is implemented as a macro. Example 5-443. PWM_READ_CONTROL_REG UWord16 controlWord; controlWord = ioctl(PWM_A, PWM_READ_CONTROL_REG, NULL); This code stores the content of the PWM A Control Register to the variable controlWord. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-605...
Page 724 Design/Implementation: The PWM_READ_PORT_REG ioctl command is implemented as a macro. Example 5-444. PWM_READ_PORT_REG UWord16 portWord; portWord = ioctl(PWM_A, PWM_READ_COUNTER_REG, NULL); This code stores the content of the PWM A Port Register to the variable portWord. 5-606 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 725 Design/Implementation: The PWM_GET_CURRENT_STATUS_INPUTS ioctl command is implemented as a macro. Example 5-445. PWM_GET_CURRENT_STATUS_INPUTS UWord16 isStatus; isStatus = ioctl(PWM_A, PWM_GET_CURRENT_STATUS_INPUTS, NULL); This code stores the status of the ISx bits in the PWM A Port Register to the variable isStatus. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-607...
Page 726 Design/Implementation: The PWM_GET_FAULT_INPUTS ioctl command is implemented as a macro. Example 5-446. PWM_GET_FAULT_INPUTS UWord16 faultStatus; faultStatus = ioctl(PWM_A, PWM_GET_FAULT_INPUTS, NULL); This code stores the status of the FAULTx bits in the PWM A Port Register to the variable faultStatus. 5-608 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 727 Design/Implementation: The PWM_GET_FAULT_INPUT_x ioctl command is implemented as a macro. Example 5-447. PWM_GET_FAULT_INPUT_x UWord16 faultStatus2; faultStatus2 = ioctl(PWM_A, PWM_GET_FAULT_INPUT_2, NULL); This code stores the status of the FAULT2 bit in the PWM A Port Register to the variable faultStatus2. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-609...
Page 728 This code enables software control of PWM A pins PWM0 and PWM1 and activates both pins in the independent PWMs operation or activates the PWM0 pin while PWM1 is the complement to PWM0 in the complementary PWM pairs mode. 5-610 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 729 This code writes a new value to the PWM A Value Register 0 which actually represents 50% of duty cycle and sets the LDOK bit in the PWM Control Register. ioctl(PWM_B, PWM_UPDATE_VALUE_REG_3, 0x2000); /* 25% */ FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-611...
Page 730 This code writes 0x2000 to the PWM B Value Register 3, which actually represents 25% of duty cycle and sets the LDOK bit in the PWM Control Register. 5-612 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 731 Design/Implementation: The PWM_UPDATE_VALUE_REGS_COMPL ioctl command is implemented as a macro. Example 5-450. PWM_UPDATE_VALUE_REGS_COMPL pwm_sComplementaryValues compVal; compVal.pwmChannel_0_Value = 0x2000; /* 25% */ compVal.pwmChannel_2_Value = 0x4000; /* 50% */ compVal.pwmChannel_4_Value = 0x6000; /* 75% */ ioctl(PWM_A, PWM_UPDATE_VALUE_REGS_COMPL, &compVal); FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-613...
Page 732 This code writes the new values to the PWM A Value Registers 0, 2 and 4, which actually represent the desired duty cycles in percentage and sets the LDOK bit in the PWM Control Register. 5-614 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 733 This code writes new values to the PWM A Value Registers 0, 1, 2, 3, 4 and 5, which actually represent the desired duty cycles in percentage and sets the LDOK bit in the PWM Control Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-615...
Page 734 PWM_HARDWARE_ACCELERATION command) prior to this command. Design/Implementation: The PWM_UPDATE_VALUE_SET_VLMODE ioctl command is implemented as a macro. Example 5-452. PWM_UPDATE_VALUE_SET_VLMODE pwm_sUpdateValueSetVlmode data; data.DutyCycle = 0x2000; /* 25% */ data.Vlmode = PWM_LOAD_FROM_0_TO_3; ioctl(PWM_A, PWM_UPDATE_VALUE_SET_VLMODE, &data); 5-616 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 735 This code writes a new value to the PWM A Value Register 0, which actually represents 25% of duty cycle. This value is also copied to PWM A Value Registers 1, 2 and 3, and sets the LDOK bit in the PWM Control Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-617...
Page 736 Example 5-453. PWM_SET_MASK_SWAP pwm_sChannelControl data; data.Mask = MC_PWM_SIGNAL_0 | MC_PWM_SIGNAL_1; data.Swap = PWM_CHANNEL_45; ioctl(PWM_A, PWM_SET_MASK_SWAP, &data); This code masks PWM0 and PWM1 signals of PWM A and simultaneously the PWM4 and PWM5 signals-channels are swapped. 5-618 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 737 Design/Implementation: The PWM_DEBUG_OPERATION ioctl command is implemented as a macro. Example 5-454. PWM_DEBUG_OPERATION ioctl(PWM_A, PWM_DEBUG_OPERATION, PWM_RUN); This code enables PWM A operation during debug mode. ioctl(PWM_B, PWM_DEBUG_OPERATION, PWM_STOP); This code disables PWM B operation during debug mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-619...
Page 738 Design/Implementation: The PWM_WAIT_OPERATION ioctl command is implemented as a macro. Example 5-455. PWM_WAIT_OPERATION ioctl(PWM_A, PWM_WAIT_OPERATION, PWM_RUN); This code enables PWM A operation during WAIT mode. ioctl(PWM_B, PWM_WAIT_OPERATION, PWM_STOP); This code disables PWM B operation during WAIT mode. 5-620 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 739 Example 5-456. PWM_MASK_SWAP_OPERATION ioctl(PWM_A, PWM_MASK_SWAP_OPERATION, PWM_ENHANCED); This code enables improved SWAP and MASK operations on the PWM A module. ioctl(PWM_B, PWM_MASK_SWAP_OPERATION, PWM_80X_COMPATIBLE); This code disables improved SWAP and MASK operations on the PWM B module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-621...
Page 740 Design/Implementation: The PWM_SET_HALF_CYCLE_INTERNAL_CORRECTION ioctl command is implemented as a macro. Example 5-457. PWM_SET_HALF_CYCLE_INTERNAL_CORRECTION ioctl(PWM_A, PWM_SET_HALF_CYCLE_INTERNAL_CORRECTION, PWM_CHANNEL_01 | PWM_CHANNEL_23); This code sets half cycle internal correction method for PWM pairs 0-1 and 2-3 on PWM A. 5-622 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 741 Special Issues: None. Design/Implementation: The PWM_SET_FULL_CYCLE_INTERNAL_CORRECTION ioctl command is implemented as a macro. Example 5-458. PWM_SET_FULL_CYCLE_INTERNAL_CORRECTION ioctl(PWM_A, PWM_SET_FULL_CYCLE_INTERNAL_CORRECTION, PWM_CHANNEL_45); This code sets full cycle internal correction method for PWM pair 4-5 on PWM A. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-623...
Page 742 Design/Implementation: The PWM_READ_INTERNAL_CORRECTION_CONTROL_REG ioctl command is implemented as a macro. Example 5-459. PWM_READ_INTERNAL_CORRECTION_CONTROL_REG UWord16 icontrolWord; icontrolWord = ioctl(PWM_A, PWM_READ_INTERNAL_CORRECTION_CONTROL_REG, NULL); This code stores the content of the PWM A Internal Correction Control Register to the variable icontrolWord. 5-624 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 743 OUTCTL0 and OUTCTL1 (bits 8 and 9 of the PWM Output Control Register) are set when using this command. Design/Implementation: The PWM_SET_SOURCE_0 ioctl command is implemented as a macro. Example 5-460. PWM_SET_SOURCE_0 ioctl(PWM, PWM_SET_SOURCE_0, PWM_SOURCE_ADC_0); This code determines that ADC SAMPLE0 result is used as PWM source. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-625...
Page 744 OUTCTL2 and OUTCTL3 (bits 10 and 11 of the PWM Output Control Register) are set when using this command. Design/Implementation: The PWM_SET_SOURCE_1 ioctl command is implemented as a macro. Example 5-461. PWM_SET_SOURCE_1 ioctl(PWM, PWM_SET_SOURCE_1, PWM_SOURCE_ADC_1); This code determines that ADC SAMPLE1 result is used as PWM source. 5-626 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 745 OUTCTL4 and OUTCTL5 (bits 12 and 13 of the PWM Output Control Register) are set when using this command. Design/Implementation: The PWM_SET_SOURCE_2 ioctl command is implemented as a macro. Example 5-462. PWM_SET_SOURCE_2 ioctl(PWM, PWM_SET_SOURCE_2, PWM_SOURCE_ADC_2); This code determines that ADC SAMPLE2 result is used as PWM source. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-627...
Page 746 Example 5-463. PWM_SET_COMPARE_INVERT_x ioctl(PWM, PWM_SET_COMPARE_INVERT_0, PWM_NORMAL); The PWM compare output 0 is driven to high state when the value of the PWM Value Register 0 is greater than the value of the PWM counter. 5-628 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 747 Special Issues: This command is applicable only on MC56F802x/3x and MC56F800x. Design/Implementation: PWM_SET_ACTIVE_HIGH_FAULTS ioctl command implemented as a macro. Example 5-464. PWM_SET_ACTIVE_HIGH_FAULTS ioctl(PWM, PWM_SET_ACTIVE_HIGH_FAULTS, PWM_FAULT_0 | PWM_FAULT_1); The PWM FAULT inputs 0 and 1 are configured as active-high. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-629...
Page 748 Special Issues: This command is applicable only on MC56F802x/3x and MC56F800x. Design/Implementation: PWM_SET_ACTIVE_LOW_FAULTS ioctl command implemented as a macro. Example 5-465. PWM_SET_ACTIVE_LOW_FAULTS ioctl(PWM, PWM_SET_ACTIVE_LOW_FAULTS, PWM_FAULT_2); The PWM FAULT input 2 is configured as active-low. 5-630 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 749 Special Issues: This command is applicable only on MC56F802x/3x and MC56F800x. Design/Implementation: The PWM_DISABLE_SYNC ioctl command is implemented as a macro. Example 5-466. PWM_DISABLE_SYNC ioctl(PWM, PWM_DISABLE_SYNC, NULL); This code disables the SYNC feature and reverts the FAULT2 pin to the default functionality. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-631...
Page 750 Special Issues: This command is applicable only on MC56F802x/3x and MC56F800x. Design/Implementation: The PWM_ENABLE_SYNC_OUT ioctl command is implemented as a macro. Example 5-467. PWM_ENABLE_SYNC_OUT ioctl(PWM, PWM_ENABLE_SYNC_OUT, NULL); This code enables the SYNC-output feature which replaces the PWM FAULT2 signal. 5-632 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 751 Design/Implementation: The PWM_ENABLE_SYNC_IN ioctl command is implemented as a macro. Example 5-468. PWM_ENABLE_SYNC_IN ioctl(PWM, PWM_ENABLE_SYNC_IN, 0x7fff); This code enables the SYNC-input synchronization signal on the Fault 2 pin to clear the internal PWM counter at any time. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-633...
Page 752 This code configures the Fault 0 input filter in terms that the glitches shorter than 8 clocks are filtered-out. On the other hand, this filter causes 10 clocks latency for the Fault 0 input signal. 5-634 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 753 This code configures the Fault 0 input filter in terms that the glitches shorter than 8 clocks are filtered-out. On the other hand, this filter causes 10 clocks latency for the Fault 0 input signal. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform...
Page 754 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The PWM_SET_PULSE_EDGE_CONTROL_x ioctl command is implemented as a macro. Example 5-471. PWM_SET_PULSE_EDGE_CONTROL_x ioctl(PWM, PWM_SET_PULSE_EDGE_CONTROL_0, PWM_NORMAL_MODE); This code sets PWM0/PWM1 pair to normal mode. 5-636 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 755: Pwm Driver Application
PWM Reload Interrupt and changes its state within the interrupt service routine. The PWM driver application found e.g. {DSP56800E_Quick_Start Source}\..\sample_applications\MC56F8346EVM\pwm_demo and consists of the application pwm_demo.mcp and the source code for the application main.c. To view the signal apply a scope probe. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-637...
Page 756 Example 5-472. PWM Driver Application - appconfig.h /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2007 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * File Name: appconfig.h * Description: file for static configuration of the application...
Page 757 PWM module operation: Disabled Prescaler: /8 , PWM clock period: 2 us PWM frequency: 7.62963 Hz , Period: 131.06801 ms PWM Deadtime: 8.18975 ms PWM Reload Frequency: Every 10 opportunity Alignment: Center Debug Mode Operation: Stop FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-639...
Page 758 Pin 6: Function: GPIO , Direction: Output , Init.Value: Low - 0 , Interrupt: Disable, Int.Polarity: Active high , Output-Mode: Push-pull , Pin 7: Function: GPIO , Direction: Output , Init.Value: Low - 0 , Interrupt: Disable, Int.Polarity: Active high , Output-Mode: Push-pull , 5-640 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 759 Pin 10: Function: ISB0 , PullUp: Enable , Pin 11: Function: ISB1 , PullUp: Enable , Pin 12: Function: ISB2 , PullUp: Enable , #define GPIO_D_DDR_INIT 0x00C0 #define GPIO_D_PER_INIT 0x1F01 End of autogenerated code ********************************************************************** ..*/ #endif FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-641...
Page 760 Example 5-473. PWM Driver Application - main.c /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2007 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * FILE NAME: main.c * DESCRIPTION: Sample application demonstrating the use of PWM driver...
Page 761 GPIO_INIT, NULL); #endif #ifdef GPIO_B ioctl(GPIO_B, GPIO_INIT, NULL); #endif #ifdef GPIO_C ioctl(GPIO_C, GPIO_INIT, NULL); #endif #ifdef GPIO_D ioctl(GPIO_D, GPIO_INIT, NULL); #endif #ifdef GPIO_E ioctl(GPIO_E, GPIO_INIT, NULL); #endif #ifdef GPIO_F ioctl(GPIO_F, GPIO_INIT, NULL); #endif FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-643...
Page 762 5-644 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 763: Sci Driver
0xF200 0xF280 SCI 1 (SCI1_BASE) 0xF210 0xF290 5.15.2.1 API Definition The following header files are needed in order to use the SCI device driver: Required Header File(s): #include “qs.h” #include “sci.h” Public Data Structure(s): FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-645...
Page 764: Configuration Items
The built-in software layer can operate in two different modes, depending on the SCI_x_HIGHLEVEL_MODE macro value. When high level layer is to be used on more than one SCI module, the same mode must be selected for all modules. 5-646 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 765 BUFFERED operation. The “bIsFull” is “true” when buffer just get full or “false” when it is getting free again. When BUFFERED operation is used (SCI_x_HIGHLEVEL_MODE defined as 2), the following configuration items also apply: FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-647...
Page 766: Api Specification
Note: inout parameters are typically input pointer variables in which the caller passes the address of a pre-allocated data structure to a function. The function stores its results within that data structure. The actual value of the inout pointer parameter is not changed. 5-648 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 767 / only one of the specified items is allowed | consolidation of items is allowed ( item1 | item2 | item3 ) & intersection of items is allowed ( item1 & item2 & item3 ) FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-649...
Page 768 Interrupt enable or disable for indi- SCI_TX_IDLE_INT SCI_DISABLE vidual interrupt sources. SCI_RX_FULL_INT The same operation possible with SCI_RX_ERROR_INT SCI_INT_ENABLE / DISABLE MC56F80xx only on SCI_ENABLE / None Enables or disables LIN slave SCI_LIN_MODE SCI_DISABLE operation. 5-650 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 769 None Sets transmit FIFO threshold SCI_SET_TXEMPTY_CONDITION when a new characters will be where condition is one of: requested from the CPU (by sig- WHEN_FIFO_EMPTY / naling the TXEMPTY interrupt). WHEN_1_OR_LESS_IN_FIFO / WHEN_2_OR_LESS_IN_FIFO / WHEN_3_OR_LESS_IN_FIFO FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-651...
Page 770 ERED operation. SCI_GET_TX_BUFFER_ NULL Word16 Returns the free space in the FREESPACE transmit buffer during the BUFF- ERED operation. SCI_SEND_XON NULL None Send the XON priority character. SCI_SEND_XOFF NULL None Send the XOFF priority character. 5-652 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 771: Detailed Api Specification
SCI driver are used. See Chapter 5.15.3.39 and Chapter 5.15.3.40. 5.15.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the usage of the ioctl commands. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-653...
Page 772 Special Issues: The SCI_INIT ioctl command must be used if the read/write functions are called within the application. Design/Implementation: The SCI_INIT ioctl command is implemented as a function call. Example 5-474. SCI_INIT ioctl(SCI_0, SCI_INIT, NULL); This code initializes the SCI 0. 5-654 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 773 Range Issues: param must be set within 0 and 8191, due to the 13-bit SCI Baud Rate Register. Special Issues: None. Design/Implementation: The SCI_SET_BAUDRATE ioctl command is implemented as a macro. Example 5-475. SCI_SET_BAUDRATE ioctl(SCI_0, SCI_SET_BAUDRATE, SCI_BAUD_9600); This code sets a baud rate of 9600 bps. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-655...
Page 774 Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SCI_OPERATING_MODE ioctl command is implemented as a macro. Example 5-476. SCI_OPERATING_MODE ioctl(SCI_0, SCI_OPERATING_MODE, SCI_SINGLE_WIRE_MODE); This code sets the SCI 0 module to single-wire loop mode. 5-656 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 775 TE (Transmitter Enable) bit in the SCI Control Register. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SCI_TRANSMITTER ioctl command is implemented as a macro. Example 5-477. SCI_TRANSMITTER ioctl(SCI_0, SCI_TRANSMITTER, SCI_ENABLE); This code enables the SCI 0 transmitter. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-657...
Page 776 RE (Receiver Enable) bit in the SCI Control Register. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SCI_RECEIVER ioctl command is implemented as a macro. Example 5-478. SCI_RECEIVER ioctl(SCI_0, SCI_RECEIVER, SCI_ENABLE); This code enables the SCI 0 receiver. 5-658 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 777 Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SCI_WAKEUP_MODE ioctl command is implemented as a macro. Example 5-479. SCI_WAKEUP_CONDITION ioctl(SCI_0, SCI_WAKEUP_CONDITION, SCI_WAKE_BY_ADDRESS); This code sets the SCI 0 wake-up by address mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-659...
Page 778 Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SCI_DATA_FORMAT ioctl command is implemented as a macro. Example 5-480. SCI_DATA_FORMAT ioctl(SCI_0, SCI_DATA_FORMAT, SCI_WORD_9BIT); This code sets the SCI 0 word length to 9 bit. 5-660 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 779 Special Issues: None. Design/Implementation: The SCI_PARITY ioctl command is implemented as a macro. Example 5-481. SCI_PARITY ioctl(SCI_0, SCI_PARITY, SCI_PARITY_EVEN); This code enables the parity function of the SCI 0 module and sets even parity. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-661...
Page 780 Register. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SCI_DATA_POLARITY ioctl command is implemented as a macro. Example 5-482. SCI_DATA_POLARITY ioctl(SCI_0, SCI_DATA_POLARITY, SCI_INVERTED); This code sets inverted mode of the SCI 0. 5-662 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 781 Special Issues: None. Design/Implementation: The SCI_STOP_IN_WAIT ioctl command is implemented as a macro. Example 5-483. SCI_STOP_IN_WAIT ioctl(SCI_0, SCI_STOP_IN_WAIT, SCI_ENABLE); This code enables the SCI 0 low-power STOP mode of the SCI module in WAIT mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-663...
Page 782 SBK (Send Break Bit) bit in the SCI Control Register. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SCI_ ioctl command is implemented as a macro. Example 5-484. SCI_SEND_BREAK ioctl(SCI_0, SCI_SEND_BREAK, NULL); This code sends one break character from SCI 0. 5-664 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 783 Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SCI_WAIT ioctl command is implemented as a macro. Example 5-485. SCI_WAIT ioctl(SCI_0, SCI_WAIT, NULL); This code puts the SCI 0 receiver in sleep mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-665...
Page 784 RWU (Receiver Wake-up Bit) bit in the SCI Control Register. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SCI_WAKEUP ioctl command is implemented as a macro. Example 5-486. SCI_WAKEUP ioctl(SCI_0, SCI_WAKEUP, NULL); This code wakes up the SCI 0 receiver. 5-666 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 785 Register and SCI Control Register 2. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SCI_INT_ENABLE ioctl command is implemented as a macro. Example 5-487. SCI_INT_ENABLE ioctl(SCI_0, SCI_INT_ENABLE, SCI_TX_EMPTY); This code enables the SCI 0 Transmitter Empty Interrupt. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-667...
Page 786 Control Register and SCI Control Register 2. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SCI_INT_DISABLE ioctl command is implemented as a macro. Example 5-488. SCI_INT_DISABLE ioctl(SCI_0, SCI_INT_DISABLE, SCI_TX_EMPTY); This code disables the SCI 0 Transmitter Empty Interrupt. 5-668 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 787 Design/Implementation: The SCI_GET_STATUS_REG ioctl command is implemented as a macro. Example 5-489. SCI_GET_STATUS_REG tmp = ioctl(SCI_0, SCI_GET_STATUS_REG, NULL); This code reads the content of the SCI 0 Status Register and stores it into variable tmp. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-669...
Page 788 Range Issues: None. Special Issues: None. Design/Implementation: The SCI_CLEAR_STATUS_REG ioctl command is implemented as a macro. Example 5-490. SCI_CLEAR_STATUS_REG UWord16 stat = ioctl(SCI_0, SCI_GET_STATUS_REG, NULL); ioctl(SCI_0, SCI_CLEAR_STATUS_REG, NULL); This code clears the SCI 0 Status Register. 5-670 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 789 Range Issues: None. Special Issues: None. Design/Implementation: The SCI_TEST_STATUS_REG ioctl command is implemented as a macro. Example 5-491. SCI_TEST_STATUS_REG if(ioctl(SCI_0, SCI_TEST_STATUS_REG, SCI_RX_IDLE_LINE_FLAG)) This code tests the RX IDLE bit of the SCI 0 Status Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-671...
Page 790 Design/Implementation: The SCI_READ_DATA ioctl command is implemented as a macro. Example 5-492. SCI_READ_DATA tmp = ioctl(SCI_0, SCI_READ_DATA, NULL); This code reads the content of the SCI 0 Data Register and stores it into variable tmp. 5-672 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 791 Special Issues: None. Design/Implementation: The SCI_WRITE_DATA ioctl command is implemented as a macro. Example 5-493. SCI_WRITE_DATA ioctl(SCI_0, SCI_WRITE_DATA, ‘A’); This code writes ‘A’ to the SCI Data Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-673...
Page 792 Special Issues: None. Design/Implementation: The SCI_READ_CONTROL_REG ioctl command is implemented as a macro. Example 5-494. SCI_READ_CONTROL_REG tmp = ioctl(SCI_0, SCI_READ_CONTROL_REG, NULL); This code stores the content of the SCI Control Register into variable tmp. 5-674 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 793 Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SCI_WRIRTE_CONTROL_REG ioctl command is implemented as a macro. Example 5-495. SCI_WRITE_CONTROL_REG ioctl(SCI_0, SCI_WRITE_CONTROL_REG, 0x0004); This code writes 0x0004 to the SCI 0 Control Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-675...
Page 794 Range Issues: None. Special Issues: None. Design/Implementation: The SCI_GET_TX_EMPTY ioctl command is implemented as a macro. Example 5-496. SCI_GET_TX_EMPTY tmp = ioctl(SCI_0, SCI_GET_TX_EMPTY, NULL); This code returns the SCI 0 Status Register, bit TDRE. 5-676 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 795 Range Issues: None. Special Issues: None. Design/Implementation: The SCI_GET_TX_IDLE ioctl command is implemented as a macro. Example 5-497. SCI_GET_TX_IDLE tmp = ioctl(SCI_0, SCI_GET_TX_IDLE, NULL); This code returns the SCI 0 Status Register, bit TIDLE. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-677...
Page 796 Range Issues: None. Special Issues: None. Design/Implementation: The SCI_GET_RX_FULL ioctl command is implemented as a macro. Example 5-498. SCI_GET_RX_FULL tmp = ioctl(SCI_0, SCI_GET_RX_FULL, NULL); This code returns the SCI 0 Status Register, bit RDRF. 5-678 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 797 Range Issues: None. Special Issues: None. Design/Implementation: The SCI_GET_RX_IDLE ioctl command is implemented as a macro. Example 5-499. SCI_GET_RX_IDLE tmp = ioctl(SCI_0, SCI_GET_RX_IDLE, NULL); This code returns the SCI 0 Status Register, bit RIDLE. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-679...
Page 798 Special Issues: None. Design/Implementation: The SCI_GET_RX_ERROR ioctl command is implemented as a macro. Example 5-500. SCI_GET_RX_ERROR tmp = ioctl(SCI_0, SCI_GET_ERROR, NULL); This code returns the SCI 0 Status Register, bits OR, NF, FE and PF. 5-680 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 799 Range Issues: None. Special Issues: None. Design/Implementation: The SCI_GET_RX_OVERRUN ioctl command is implemented as a macro. Example 5-501. SCI_GET_RX_OVERRUN tmp = ioctl(SCI_0, SCI_GET_RX_OVERRUN, NULL); This code returns the SCI 0 Status Register, bit OR. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-681...
Page 800 Range Issues: None. Special Issues: None. Design/Implementation: The SCI_GET_RX_NOISE_ERROR ioctl command is implemented as a macro. Example 5-502. SCI_GET_RX_NOISE_ERROR tmp = ioctl(SCI_0, SCI_GET_RX_NOISE_ERROR, NULL); This code returns the SCI 0 Status Register, bit NF. 5-682 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 801 Range Issues: None. Special Issues: None. Design/Implementation: The SCI_GET_RX_FRAMING_ERROR ioctl command is implemented as a macro. Example 5-503. SCI_GET_RX_FRAMING_ERROR tmp = ioctl(SCI_0, SCI_GET_RX_FRAMING_ERROR, NULL); This code returns the SCI 0 Status Register, bit FE. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-683...
Page 802 Range Issues: None. Special Issues: None. Design/Implementation: The SCI_GET_RX_PARITY_ERROR ioctl command is implemented as a macro. Example 5-504. SCI_GET_RX_PARITY_ERROR tmp = ioctl(SCI_0, SCI_GET_RX_PARITY_ERROR, NULL); This code returns the SCI 0 Status Register, bit PF. 5-684 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 803 Range Issues: None. Special Issues: None. Design/Implementation: The SCI_GET_RX_ACTIVE ioctl command is implemented as a macro. Example 5-505. SCI_GET_RX_ACTIVE tmp = ioctl(SCI_0, SCI_GET_RX_ACTIVE, NULL); This code returns the SCI 0 Status Register, bit RAF. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-685...
Page 804 Special Issues: This command is applicable only on MC56F80xx. Design/Implementation: The SCI_LIN_MODE ioctl command is implemented as a macro. Example 5-506. SCI_LIN_MODE ioctl( SCI_0, SCI_LIN_MODE, SCI_ENABLE); This code enables the LIN slave operation on the SCI_0/SCI module. 5-686 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 805 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The SCI_QUEUED_MODE ioctl command is implemented as a macro. Example 5-507. SCI_QUEUED_MODE ioctl(SCI, SCI_QUEUED_MODE, SCI_ENABLE); This code enables queued mode of the SCI module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-687...
Page 806 SCI will signal TXEMPTY. In other words it means that when the TXEMPTY flag or interrupt is detected, up to four bytes (FIFO depth) can be written to the transmit register at once. See also the SCI_CAN_WRITE_DATA ioctl command. 5-688 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 807 RXFULL flag to be set, just like in the non-queued mode. However, unlike the non-queued mode the receive FIFO accepts additional three characters (up to FIFO depth) before the receive-overrun occurs. See also the SCI_CAN_READ_DATA ioctl command. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-689...
Page 808 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The SCI_CAN_READ_DATA ioctl command is implemented as a macro. Example 5-510. SCI_CAN_READ_DATA UWord16 byte; while(ioctl(SCI, SCI_CAN_READ_DATA, NULL)) byte = ioctl(SCI, SCI_READ_DATA, NULL); This code reads all bytes from the SCI receive FIFO. 5-690 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 809 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The SCI_CAN_WRITE_DATA ioctl command is implemented as a macro. Example 5-511. SCI_CAN_WRITE_DATA if(ioctl(SCI, SCI_CAN_WRITE_DATA, NULL)) ioctl(SCI, SCI_WRITE_DATA, *pNextByte++); This code writes one data byte into the transmit FIFO if possible. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-691...
Page 810 Special Issues: The read function in non-blocking mode is not reentrant, see Section 5.15.3.42 and Section . The interrupt functions of the SCI driver must be installed to obtain proper functionality of the read function (See Table 5-576). 5-692 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 811 Note: Symbol x in the Table 5-576 should be replaced with the number of the SCI module e.g. Sci0RxFullISR. non-blocking mode: None. Design/Implementation: The read is implemented as a function call for all modes. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-693...
Page 812 Note: Symbol x in the Table 5-576 should be replaced with the number of the SCI module e.g. Sci0TxEmptyISR. non-blocking mode: None. Design/Implementation: The write is implemented as a function call for all modes. 5-694 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 813 Range Issues: None. Special Issues: None. Design/Implementation: The SCI_CLEAR_EXCEPTION ioctl command is implemented as a macro. Example 5-512. SCI_CLEAR_EXCEPTION ioctl(SCI_0, SCI_CLEAR_EXCEPTION, NULL); This code clears exceptions generated by read/write functions for the SCI 0 module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-695...
Page 814 Special Issues: None. Design/Implementation: The SCI0_GET_STATUS ioctl command is implemented as a macro. Example 5-513. SCI0_GET_STATUS tmp = ioctl(SCI_0, SCI0_GET_STATUS, NULL); This code reads the status of the read/write function and stores it into variable tmp. 5-696 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 815 Design/Implementation: The SCI_WRITE_CANCEL ioctl command is implemented as a macro. Example 5-514. SCI_WRITE_CANCEL write(SCI_0, NON_BLOCKING, buffer, 10); ioctl(SCI_0, SCI_WRITE_CANCEL, NULL); This code cancels a non-blocking write operation into the SCI 0 module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-697...
Page 816 Design/Implementation: The SCI_READ_CANCEL ioctl command is implemented as a macro. Example 5-515. SCI_READ_CANCEL read(SCI_0, NON_BLOCKING, buffer, 10); ioctl(SCI_0, SCI_READ_CANCEL, NULL); This code cancels a non-blocking read operation into the SCI 0 module. 5-698 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 817 Design/Implementation: The SCI_BUFFERED_RX ioctl command is implemented as a function call. Example 5-516. SCI_BUFFERED_RX Word16 readChars; ioctl(SCI_0, SCI_BUFFERED_RX, SCI_ENABLE); readChars = read(SCI_0, BUFFERED, buffer, 10); This code enables the buffered receive operation and reads up to 10 characters from the receivers circular buffer. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-699...
Page 818 Design/Implementation: The SCI_BUFFERED_TX ioctl command is implemented as a function call. Example 5-517. SCI_BUFFERED_TX ioctl(SCI_0, SCI_BUFFERED_TX, SCI_ENABLE); write(SCI_0, BUFFERED, “Hello World”, 11); This code enables the buffered transmit operation and writes the “Hello World” string to the transmitter circular buffer. 5-700 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 819 Design/Implementation: The SCI_GET_RX_CHARS_READY ioctl command is implemented as a function call. Example 5-518. SCI_GET_RX_CHARS_READY if(ioctl(SCI_0, SCI_GET_RX_CHARS_READY, NULL) > 10) read(SCI_0, BUFFERED, buff, sizeof(buff)); This code checks whether any more than 10 characters are available in the receiver’s buffer and reads them. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-701...
Page 820 Special Issues: This command can be applied when BUFFERED high-level operation mode is selected only. Design/Implementation: The SCI_GET_RX_BUFFER_FREESPACE ioctl command is implemented as a function call. Example 5-519. SCI_GET_RX_BUFFER_FREESPACE if(ioctl(SCI_0, SCI_GET_RX_BUFFER_FREESPACE, NULL) < 5) This code checks whether the free space is below 5 characters. 5-702 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 821 Example 5-520. SCI_GET_TX_BUFFER_FREESPACE if(ioctl(SCI_0, SCI_GET_TX_BUFFER_FREESPACE, NULL) >= 11) write(SCI_0, BUFFERED, “Hello World”, 11); This code sends the string “Hello World” after it assures the whole string will fit in the transmitter buffer. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-703...
Page 822 Special Issues: This command can be applied when BUFFERED high-level operation mode is selected only. Design/Implementation: The SCI_SEND_XON ioctl command is implemented as a macro. Example 5-521. SCI_SEND_XON ioctl(SCI_0, SCI_SEND_XON, NULL); This code sends the XON character. 5-704 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 823 Special Issues: This command can be applied when BUFFERED high-level operation mode is selected only. Design/Implementation: The SCI_SEND_XOFF ioctl command is implemented as a macro. Example 5-522. SCI_SEND_XOFF ioctl(SCI_0, SCI_SEND_XOFF, NULL); This code sends the XOFF character. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-705...
Page 824: Sci Driver Application
Example 5-523. SCI Driver Sample Application - appconfig.h /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2007 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * File Name: appconfig.h...
Page 825 #define SEMI_CSBAR2_INIT 0x0005 #define SEMI_CSOR0_INIT 0x1FC3 #define SEMI_CSOR1_INIT 0x1BA3 #define SEMI_CSOR2_INIT 0x1DA3 INTC Configuration -------------------------------------------- All maskable interrupts disabled: No IRQ A trigger mode: Low-level sensitive IRQ B trigger mode: Low-level sensitive #define INTC_ICTL_INIT 0x0000 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-707...
Page 826 Parity: None Polarity: True polarity Loop mode: Disable Function in Wait Mode: SCI module enabled in Wait Mode #define SCI_0_SCICR_INIT 0x0000 #define SCI_0_HIGHLEVEL_MODE #define SCI_0_RX_BUFFER_OKLIMIT 0x000A #define SCI_0_RX_BUFFER_LOWLIMIT 0x0003 #define SCI_0_RX_BUFFER_SIZE 0x14 #define SCI_0_TX_BUFFER_SIZE 0x14 5-708 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 827 #define SCI_0_RX_XONXOFF 0x01 #define SCI0CHAR char #define SCI_0_RX_CHAR_HOOK rx_char_hook End of autogenerated code ********************************************************************** ..*/ #endif FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-709...
Page 828 Example 5-524. SCI Driver Sample Application - main.c /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2007 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * FILE NAME: main.c * DESCRIPTION: Sample application which shows how to read/write from/to SCI module The application echoes back to PC any characters received on SCI.
Page 829 /* for asterisk, togle LED and togle rx enable */ if(rxchar == '*') ioctl(GPIO_LEDS, GPIO_TOGGLE_PIN, LED_R); rxEna = !rxEna; /* never echo asterisk */ return 1; /* throw character away if rxEna is non-zero */ FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-711...
Page 830 GPIO_INIT, NULL); #endif #ifdef GPIO_B ioctl(GPIO_B, GPIO_INIT, NULL); #endif #ifdef GPIO_C ioctl(GPIO_C, GPIO_INIT, NULL); #endif #ifdef GPIO_D ioctl(GPIO_D, GPIO_INIT, NULL); #endif #ifdef GPIO_E ioctl(GPIO_E, GPIO_INIT, NULL); #endif #ifdef GPIO_F ioctl(GPIO_F, GPIO_INIT, NULL); #endif 5-712 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 831: Spi Driver
/ for SPI (SPI_BASE) 0xF100 0xF0C0 SPI0 (SPI0_BASE) 0xF220 0xF220 0xF2A0 SPI1 (SPI1_BASE) 0xF230 0xF2B0 5.16.2.1 API Definition The following header files are needed in order to use the SPI device driver: Required Header File(s): FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-713...
Page 832: Configuration Items
Name of the built in interrupt service routine imple- yy = SPI0 Receiver Full Interrupt mented in spi.c file. INT_VECTOR_ADDR_yy Spi0TxEmptyISR Name of the built in interrupt service routine imple- yy = SPI0 Transmitter Empty Interrupt mented in spi.c file. 5-714 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 833: Api Specification
Function arguments for each routine are described as in, out, or inout. 1. in argument means that the parameter value is an input only to the function. 2. out argument means that the parameter value is an output only from the function. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-715...
Page 834 Address of the allocated data buffer. size Number of words to be read (in case of read function call) or to be written (in case of write function call). Item Separator Convention: 5-716 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 835 SPI_OPEN_DRAIN SPI pins. SPI_SET_BAUD_DIV SPI_DIV2 / SPI_DIV8 / None Sets SPI baud rate (clock) SPI_DIV16 / SPI_DIV32 / divisor. SPI_DIV64 / SPI_DIV128 / SPI_DIV256 new on MC56F800x: SPI_DIV512 / SPI_DIV1024 / SPI_DIV2048 / SPI_DIV4096 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-717...
Page 836 (test if any SPI error) SPI_CLEAR_MODE_FAULT NULL None Clears Status and Control Register MODF bit (“Mode Fault bit”). only on MC56F802x/3x and SPI_MULT_DIV_1x / None Multiplies baud-rate divisor MC56F800x: SPI_MULT_DIV_2x value by a given factor. SPI_MULT_BAUD_DIV 5-718 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 837 Returns non-zero if there is a SPI_CAN_WRITE_DATA free space in the transmit FIFO. High-level software layer commands: SPI_CLEAR_EXCEPTION NULL None Clears read/write functions exception if exists SPI_GET_STATUS NULL UWord16 Get read/write functions SPI operation status FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-719...
Page 838: Detailed Api Specification
SPI driver are used. See Section 5.16.3.38 and Section 5.16.3.39. 5.16.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the usage of the ioctl commands. 5-720 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 839 Example 5-525. SPI_INIT ioctl(SPI_0, SPI_INIT, NULL); This code initializes the SPI module with values defined in appconfig.h. The appconfig.h file can be edited manually or generated by the Graphical Configuration Tool. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-721...
Page 840 Example 5-526. SPI_DEVICE /* configure desired SPI parameters */ /* ... */ /* enable it */ ioctl(SPI_0, SPI_DEVICE, SPI_ENABLE); This code enables the SPI interface. Before enabling, the SPI module should be properly configured. 5-722 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 841 SPI Status and Control Register, bit SPMSTR (“Master Slave”). Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SPI_SET_MODE ioctl command is implemented as a macro. Example 5-527. SPI_SET_MODE ioctl(SPI_0, SPI_SET_MODE, SPI_MASTER); This code sets the SPI to Master mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-723...
Page 842 Range Issues: None. Special Issues: None. Design/Implementation: The SPI_SET_ORDER ioctl command is implemented as a macro. Example 5-528. SPI_SET_ORDER ioctl(SPI_0, SPI_SET_ORDER, SPI_MSB_FIRST); This code sets the SPI to shift out the MSB bit first. 5-724 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 843 Special Issues: None. Design/Implementation: The SPI_SET_CLOCK_POLARITY ioctl command is implemented as a macro. Example 5-529. SPI_SET_CLOCK_POLARITY ioctl(SPI_0, SPI_SET_CLOCK_POLARITY, SPI_FALLING_EDGE); This code sets the SPI to shift out data on the falling edge of the SCLK signal. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-725...
Page 844 Special Issues: None Design/Implementation: The SPI_SET_CLOCK_PHASE ioctl command is implemented as a macro. Example 5-530. SPI_SET_CLOCK_PHASE ioctl(SPI_0, SPI_SET_CLOCK_PHASE, SPI_SS_EDGE); This code sets the SPI to start shift data on the falling edge of the SS signal. 5-726 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 845 Control Register, bit MODFEN (“Mode Fault Enable”). Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SPI_SET_MODE_FAULT ioctl command is implemented as a macro. Example 5-531. SPI_SET_MODE_FAULT ioctl(SPI_0, SPI_SET_MODE_FAULT, SPI_ENABLE); This code enables the SPI mode fault error detection. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-727...
Page 846 Range Issues: param: 2-16 Special Issues: None. Design/Implementation: The SPI_SET_TX_DATA_SIZE ioctl command is implemented as a macro. Example 5-532. SPI_SET_TX_DATA_SIZE ioctl(SPI_0, SPI_SET_TX_DATA_SIZE, 8); This code sets the SPI transmission word length to 8 bit. 5-728 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 847 Data Size and Control Register WOM (“Wired-OR Mode”) bit. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The SPI_SET_WIRED_OR_MODE command is implemented as a macro. Example 5-533. SPI_SET_WIRED_OR_MODE ioctl(SPI_0, SPI_SET_WIRED_OR_MODE, SPI_OPEN_DRAIN); This code enables pull-ups for the SPI pins. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-729...
Page 848 Design/Implementation: The SPI_SET_BAUD_DIV ioctl command is implemented as a macro. Example 5-534. SPI_SET_BAUD_DIV ioctl(SPI_0, SPI_SET_BAUD_DIV, SPI_DIV8); This code sets the SPI clock to IPbus frequency divided by 8 (usually 5MHz for 40MHz IPbus clock). 5-730 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 849 Design/Implementation: The SPI_RX_FULL_INT command is implemented as a macro. Example 5-535. SPI_RX_FULL_INT /* enable SPI receive interrupt */ ioctl(SPI_0, SPI_RX_FULL_INT, SPI_ENABLE); /* ... */ /* disable SPI receive interrupt */ /ioctl(SPI_0, SPI_RX_FULL_INT, SPI_DISABLE); This code switches on/off the SPI receiver interrupt. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-731...
Page 850 Design/Implementation: The SPI_TX_EMPTY_INT command is implemented as a macro. Example 5-536. SPI_TX_EMPTY_INT /* enable SPI transmit interrupt */ ioctl(SPI_0, SPI_TX_EMPTY_INT, SPI_ENABLE); /* ... */ /* disable SPI transmit interrupt */ /ioctl(SPI_0, SPI_TX_EMPTY_INT, SPI_DISABLE); This code switches on/off the SPI transmit interrupt. 5-732 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 851 Design/Implementation: The SPI_ERROR_INT command is implemented as a macro. Example 5-537. SPI_ERROR_INT /* enable SPI error interrupt */ ioctl(SPI_0, SPI_ERROR_INT, SPI_ENABLE); /* ... */ /* disable SPI error interrupt */ /ioctl(SPI_0, SPI_ERROR_INT, SPI_DISABLE); This code switches on/off the SPI error interrupt. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-733...
Page 852 Special Issues: None. Design/Implementation: The SPI_INT_ENABLE command is implemented as a macro. Example 5-538. SPI_INT_ENABLE /* enable SPI interrupts */ ioctl(SPI_0, SPI_INT_ENABLE, SPI_TX_EMPTY | SPI_RX_FULL); This code enables the SPI Receiver Full and Transmitter Empty interrupt. 5-734 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 853 Special Issues: None. Design/Implementation: The SPI_INT_DISABLE command is implemented as a macro. Example 5-539. SPI_INT_DISABLE /* enable SPI interrupts */ ioctl(SPI_0, SPI_INT_DISABLE, SPI_TX_EMPTY | SPI_RX_FULL); This code disables the SPI Receiver Full and Transmitter Empty interrupt. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-735...
Page 854 SPI_TX_EMPTY | SPI_RX_FULL | SPI_ERROR); /* ... */ /* disable SPI error interrupt */ /ioctl(SPI_0, SPI_INT_SELECT, SPI_RX_FULL); After execution of this code SPI Receiver Full interrupt remains enabled, SPI Transmitter Empty and SPI Receiver error will be disabled. 5-736 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 855 Example 5-541. SPI_WRITE_DATA /* SPI is properly configured and enabled */ /* write data to SPI bus (if in Master mode) */ ioctl(SPI_0, SPI_WRITE_DATA,0x58A4); This code puts 1 data word on the SPI bus. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-737...
Page 856 Example 5-542. SPI_READ_DATA UWord16 D1; /* SPI is properly configured and enabled */ /* read previously received data */ D1 = ioctl(SPI_0, SPI_READ_DATA, NULL); This code reads the data word received from the SPI bus. 5-738 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 857 /* Data Transmit Register ready to receive new data word */ ioctl(SPI_0, SPI_WRITE_DATA, 0x0057); This code tests the SPTE bit in the Status and Control Register and writes a new word into the Data Transmit Register, if empty. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-739...
Page 858 /* new data in Data Receive Register ready */ D1 = ioctl(SPI_0, SPI_READ_DATA, NULL); This code tests the status and control register, bit SPRF and reads a new word from the Data Receive Register, if any. 5-740 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 859 D1 = ioctl(SPI_0, SPI_READ_RX_REG, NULL); This code tests the Status and Control Register, bit OVRF. If the bit is set, it reads the previous data word from the Data Receive Register and clears bit OVRF. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-741...
Page 860 Example 5-546. SPI_READ_CONTROL_REG UWord16 reg; /* read SPI0 Status and Control Register */ reg = ioctl(SPI_0, SPI_READ_CONTROL_REG, NULL); This code reads the SPI Status and Control Register and stores its value in the reg variable. 5-742 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 861 Design/Implementation: The SPI_WRITE_CONTROL_REG command is implemented as a macro. Example 5-547. SPI_WRITE_CONTROL_REG /* write SPI0 Status and Control Register */ ioctl(SPI_0, SPI_WRITE_CONTROL_REG, 0x0020); This code writes 0x0020 in the SPI Status and Control Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-743...
Page 862 /* test status and control register MODF bit */ if (ioctl(SPI_0, SPI_GET_MODE_FAULT, NULL)) /* error in /SS level occurred */ ioctl(SPI_0, SPI_CLEAR_MODE_FAULT, NULL); This code tests the Status and Control Register, bit MODF. This bit is cleared, if it is set. 5-744 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 863 SPI_GET_RXD_OVERFLOW commands can be used */ if (ioctl(SPI_0, SPI_GET_RXD_OVERFLOW, NULL)) /* receive overflow */ else /* mode fault error */ ioctl(SPI_0, SPI_CLEAR_MODE_FAULT, NULL); This code tests Status and Control Register, bits OVRF and MODF and shows possible error states. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-745...
Page 864 Design/Implementation: The SPI_CLEAR_MODE_FAULT command is implemented as a macro. Example 5-550. SPI_CLEAR_MODE_FAULT /* clear status and control register MODF bit */ ioctl(SPI_0, SPI_CLEAR_MODE_FAULT, NULL)) This code clears the Status and Control Register, bit MODF. 5-746 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 865 Special Issues: This command is applicable only on MC56F802x/3x and MC56F800x. Design/Implementation: The SPI_MULT_BAUD_DIV ioctl command is implemented as a macro. Example 5-551. SPI_MULT_BAUD_DIV ioctl(SPI, SPI_SET_BAUD_DIV, SPI_DIV256); ioctl(SPI, SPI_MULT_BAUD_DIV, SPI_ENABLE); This code sets total baud-rate divisor value of 512. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-747...
Page 866 Special Issues: This command is applicable only on MC56F802x/3x and MC56F800x. Design/Implementation: The SPI_TEST_SS_INPUT ioctl command is implemented as a macro. Example 5-552. SPI_TEST_SS_INPUT if(ioctl(SPI, SPI_TEST_SS_INPUT, NULL)) This code tests the immediate state of the SS input pin. 5-748 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 867 This command changes the SS_DDR, SS_AUTO and SS_STRB bits of the SPI Data Size and Control Register (SPDSCR). Returns: None. Range Issues: None. Special Issues: This command is applicable only on MC56F802x/3x and MC56F800x. Design/Implementation: The SPI_SET_SS_MODE ioctl command is implemented as a macro. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-749...
Page 868 Example 5-553. SPI_SET_SS_MODE ioctl(SPI, SPI_SET_SS_MODE, SPI_SS_MANUAL_OUT); This code configures the slave-select pin to a manual control mode. 5-750 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 869 Design/Implementation: The SPI_SET_SS_OUTPUT ioctl command is implemented as a macro. Example 5-554. SPI_SET_SS_OUTPUT ioctl(SPI, SPI_SET_SS_MODE, SPI_SS_MANUAL_OUT); ioctl(SPI, SPI_SET_SS_OUTPUT, SPI_HIGH); This code configures the slave-select pin for a manual control and sets the pin output high. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-751...
Page 870 Special Issues: This command is applicable only on MC56F802x/3x and MC56F800x. Design/Implementation: The SPI_SET_SS_WIRED_OR_MODE ioctl command is implemented as a macro. Example 5-555. SPI_SET_SS_WIRED_OR_MODE ioctl(SPI, SPI_SET_SS_WIRED_OR_MODE, SPI_ENABLE); This code configures the slave-select pin to the open-drain mode. 5-752 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 871 Design/Implementation: The SPI_OVERRIDE_SS_INPUT ioctl command is implemented as a macro. Example 5-556. SPI_OVERRIDE_SS_INPUT ioctl(SPI, SPI_OVERRIDE_SS_INPUT, SPI_DISABLE); This code reverts the SS signal to a default behavior when it is sourced from the SS pin. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-753...
Page 872 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The SPI_QUEUED_MODE ioctl command is implemented as a macro. Example 5-557. SPI_QUEUED_MODE ioctl(SPI, SPI_QUEUED_MODE, SPI_ENABLE); This code enables queued mode of the SPI module. 5-754 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 873 SPI will signal TXEMPTY. In other words it means that when the TXEMPTY flag or interrupt is detected, up to four bytes (FIFO depth) can be written to the transmit register at once. See also the SPI_CAN_WRITE_DATA ioctl command. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-755...
Page 874 RXFULL flag to be set, just like in the non-queued mode. However, unlike the non-queued mode the receive FIFO accepts additional three characters (up to FIFO depth) before the receive- overrun occurs. See also the SPI_CAN_READ_DATA ioctl command. 5-756 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 875 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The SPI_CAN_READ_DATA ioctl command is implemented as a macro. Example 5-560. SPI_CAN_READ_DATA UWord16 byte; while(ioctl(SPI, SPI_CAN_READ_DATA, NULL)) byte = ioctl(SPI, SPI_READ_DATA, NULL); This code reads all bytes from the SPI receive FIFO. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-757...
Page 876 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The SPI_CAN_WRITE_DATA ioctl command is implemented as a macro. Example 5-561. SPI_CAN_WRITE_DATA if(ioctl(SPI, SPI_CAN_WRITE_DATA, NULL)) ioctl(SPI, SPI_WRITE_DATA, *pNextByte++); This code writes one data byte into the transmit FIFO if possible. 5-758 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 877 Note: Symbol “x” in the Table 5-636 should be replaced with the number of the SPI module e.g. Spi0ReceiveISR. non-blocking mode: None. Design/Implementation: The non-blocking and blocking mode of the read macro are implemented as a function call. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-759...
Page 878 Note: Symbol “x” in the Table 5-638 should be replaced with the number of the SPI module e.g. Spi0TxEmptyISR. non-blocking mode: None. Design/Implementation: The non-blocking and blocking mode of the write macro are implemented as a function call. 5-760 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 879 Range Issues: None. Special Issues: None. Design/Implementation: The SPI_CLEAR_EXCEPTION ioctl command is implemented as a macro. Example 5-562. SPI_CLEAR_EXCEPTION ioctl(SPI_0, SPI_CLEAR_EXCEPTION, NULL); This code clears an exception generated by read/write functions for the SPI 0 module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-761...
Page 880 Special Issues: None. Design/Implementation: The SPI_GET_STATUS ioctl command is implemented as a macro. Example 5-563. SPI_GET_STATUS tmp = ioctl(SPI_0, SPI_GET_STATUS, NULL); This code reads the read/write function operation status and stores it to variable tmp. 5-762 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 881 NON_BLOCKING, buffer, 10); ioctl(SPI_0, SPI_WRITE_CANCEL, NULL); This code cancels a non-blocking write operation on the SPI 0 module. It means that a write function can be called again before finishing previous write operations. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-763...
Page 882 This code cancels non-blocking read operation on the SPI 0 module during receive operation. It means that a read function can be called again before finishing previous read operations. After that it runs another read operation for 5 words. 5-764 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 883: Spi Driver Application
SPI peripheral or to another MCU/DSP. driver application found e.g. {DSP56800E_Quick_Start Source}\..sample_applications\MC56F8346EVM directory and consists of the application project spi_demo.mcp and the source code for the application main.c. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-765...
Page 884 Example 5-566. SPI Driver Sample Application - appconfig.h /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2007 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * File Name: appconfig.h * Description: file for static configuration of the application...
Page 885 Pin 12: Function: ISB2 , PullUp: Enable , #define GPIO_D_PER_INIT 0x1FC1 GPIO_E Configuration -------------------------------------------- Pin 0: Function: TXD0 , PullUp: Enable , Pin 1: Function: RXD0 , PullUp: Enable , Pin 2: Function: A6 , PullUp: Enable , FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-767...
Page 886 SCLK Phase: Transmission started by edge on SS pin Shift order: MSB first Wired OR mode: Normal SS Mode Fault Enable: Enable Interrupts: Receiver: Disable Error: Disable Transmitter: Disable #define SPI_0_SPSCR_INIT 0x6520 End of autogenerated code ********************************************************************** ..*/ #endif 5-768 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 887 Example 5-567. SPI Driver Sample Application - main.c /******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2004-2007 Freescale Semiconductor, Inc. * (c) Copyright 2001-2004 Motorola, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** * FILE NAME: main.c * DESCRIPTION: SPI driver demo program - communicates with MAXIM MAX5251 quad 10-bit DAC.
Page 888 /* waits to SPI write end - it tests RX full flag */ while (!ioctl(SPI_0, SPI_GET_RX_FULL, NULL)) /* possible to test the other events */ /* inserted delay for timing requirements of MAX5251 */ //archDelay(3); /* /CS DAC "H" */ ioctl(GPIO_SPI, GPIO_SET_PIN, SPI_SS); 5-770 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 889 GPIO_INIT, NULL); #endif #ifdef GPIO_B ioctl(GPIO_B, GPIO_INIT, NULL); #endif #ifdef GPIO_C ioctl(GPIO_C, GPIO_INIT, NULL); #endif #ifdef GPIO_D ioctl(GPIO_D, GPIO_INIT, NULL); #endif #ifdef GPIO_E ioctl(GPIO_E, GPIO_INIT, NULL); #endif #ifdef GPIO_F ioctl(GPIO_F, GPIO_INIT, NULL); #endif FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-771...
Page 890 5-772 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 891: Iic Driver (Mc56F801X,Mc56F800X)
An IIC transaction begins when the Master transmits the address byte and the addressed (Slave) node acknowledges it. In the first byte, the Master also specifies whether the transaction is Read-from-slave or Write-to-slave. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-773...
Page 892: Iic Bus Transmission Signals
This section defines the terms and formulas used later in Section 5.17.3. Table 5-643. IIC Module Base Address Module base address MC56F800x MC56F801x MC56F802x/3x MC56F83xx of / for IIC (IIC_BASE) 0xF120 0xF0D0 N/A (different module) 5-774 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 893: Api Definition
Reset value used. IIC_NFILT_INIT UWord16 Initial value of the IIC Noise Filter Register Register not initialized. (NFILT). Reset value used. IIC_ADDR_INIT UWord16 Initial value of the IIC Address Register Register not initialized. (ADDR). Reset value used. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-775...
Page 894 UWord16 Initial value for the Low Time Out Register Register not initialized. High (IICSLTH). Reset value used. IIC_IICSMB_INIT UWord16 Initial value for the Control and Status Register not initialized. Register (IICSMB). Reset value used. 5-776 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 895: Api Specification
& intersection of items is allowed ( item1 & item2 & item3 ) Table 5-647. IIC Module ioctl Commands pParam Return Description IIC_INIT NULL None Initializes the IIC module using the appconfig.h values. IIC_SET_ADDRESS UWord16 None Set the slave address of the IIC Bus node FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-777...
Page 896 IIC_TRANSFER_COMPLETE | UWord16 Test IIC Status Register for the IIC_ADDRESSED_AS_SLAVE | selected bits. Returns non-zero if IIC_BUS_BUSY | any of bits selected in the parame- IIC_ARBITRATION_LOST | ter are set. IIC_SLAVE_TRANSMIT | IIC_IBUS_INT | IIC_RX_ACK 5-778 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 897 IIC_CLEAR_LOW_TIMEOUT_FLAG MC56F800x only: UWord16 (0..127) None Sets SMBus address. IIC_SET_SMBUS_ADDRESS MC56F800x only: NULL UWord16 Reads and returns SMBus address. IIC_GET_SMBUS_ADDRESS MC56F800x only: UWord16(0..65535) None Writes value into the SCL low time- IIC_WRITE_SCL_LOW_TIMEOUT out registers. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-779...
Page 898: Detailed Api Specification
Reads and returns value from the IIC_READ_SCL_LOW_TIMEOUT SCL low timeout registers. 5.17.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the usage of the ioctl commands. 5-780 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 899 Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_INIT ioctl command is implemented as a function call. Example 5-568. IIC_INIT ioctl(IIC, IIC_INIT, NULL); This code calls the driver initialization function. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-781...
Page 900 Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_SET_ADDRESS ioctl command is implemented as a macro. Example 5-569. IIC_SET_ADDRESS ioctl(IIC, IIC_SET_ADDRESS, 10); This code sets the IIC slave address to 10. 5-782 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 901 Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_GET_ADDRESS ioctl command is implemented as a macro. Example 5-570. IIC_GET_ADDRESS UWord16 a; a = ioctl(IIC, IIC_GET_ADDRESS, NULL); This code reads the actual slave address. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-783...
Page 902 Example 5-571. IIC_SET_PRESCALER ioctl(IIC, IIC_SET_PRESCALER, 0xBF); This code sets the following IIC Bus parameters: • SCL Divider: 15360 clocks • SDA Hold: 2052 clocks • SCL Hold (Start): 7672 clocks • SCL Hold (Stop): 7684 clocks 5-784 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 903 Range Issues: None. Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_I_BUS ioctl command is implemented as a macro. Example 5-572. IIC_I_BUS ioctl(IIC, IIC_I_BUS, IIC_ENABLE); This code enables the IIC module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-785...
Page 904 Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_I_BUS_INT ioctl command is implemented as a macro. Example 5-573. IIC_I_BUS_INT ioctl(IIC, IIC_I_BUS_INT, IIC_ENABLE); This code enables the interrupt of the IIC module. 5-786 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 905 Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_MASTER_SLAVE_MODE ioctl command is implemented as a macro. Example 5-574. IIC_MASTER_SLAVE_MODE ioctl(IIC, IIC_MASTER_SLAVE_MODE, IIC_MASTER); This code switches the IIC module into the master mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-787...
Page 906 Special Issues: This command is applicable only on MC56F801x and MC56F800x and MC56F800x. Design/Implementation: The IIC_GET_MASTER_MODE ioctl command is implemented as a macro. Example 5-575. IIC_GET_MASTER_MODE if(ioctl(IIC, IIC_GET_MASTER_MODE, NULL)) // ... master mode processing This code tests the IIC is in master mode. 5-788 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 907 Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_TX_RX_MODE ioctl command is implemented as a macro. Example 5-576. IIC_TX_RX_MODE ioctl(IIC, IIC_TX_RX_MODE, IIC_TRANSMIT) This code switches the mode into the transmitting mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-789...
Page 908 Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_GET_TX_MODE ioctl command is implemented as a macro. Example 5-577. IIC_GET_TX_MODE if(ioctl(IIC, IIC_GET_TX_MODE, NULL)) // ... transmit mode processing This code tests whether the transmission mode is active. 5-790 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 909 Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_TX_ACK ioctl command is implemented as a macro. Example 5-578. IIC_TX_ACK ioctl(IIC, IIC_TX_ACK, IIC_NO_ACK) This command disables generating of the acknowledge for the next byte received. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-791...
Page 910 Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_REPEAT_START ioctl command is implemented as a macro. Example 5-579. IIC_REPEAT_START ioctl(IIC, IIC_REPEAT_START, NULL); This command generates the repeated START condition on the IIC bus. 5-792 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 911 Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_WRITE_CONTROL_REG ioctl command is implemented as a macro. Example 5-580. IIC_WRITE_CONTROL_REG ioctl(IIC, IIC_WRITE_CONTROL_REG, 0); This code writes zero to Control Register, shutting down the IIC module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-793...
Page 912 Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_READ_CONTROL_REG ioctl command is implemented as a macro. Example 5-581. IIC_READ_CONTROL_REG UWord16 ctl; ctl = ioctl(IIC, IIC_READ_CONTROL_REG, NULL); This code reads the content of the Control Register. 5-794 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 913 Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_READ_DATA ioctl command is implemented as a macro. Example 5-582. IIC_READ_DATA UWord16 b; b = ioctl(IIC, IIC_READ_DATA, NULL); This code reads the byte received from the IIC. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-795...
Page 914 Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_WRITE_DATA ioctl command is implemented as a macro. Example 5-583. IIC_WRITE_DATA ioctl(IIC, IIC_WRITE_DATA, ‘A’); This code writes a data byte to DATA transmit register. 5-796 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 915 Range Issues: None. Special Issues: This command is applicable only on MC56F801x. Design/Implementation: The IIC_SET_NOISE_FILTER ioctl command is implemented as a macro. Example 5-584. IIC_SET_NOISE_FILTER ioctl(IIC, IIC_SET_NOISE_FILTER, 0); This code disables the IIC Noise Filter. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-797...
Page 916 Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_READ_STATUS_REG ioctl command is implemented as a macro. Example 5-585. IIC_READ_STATUS_REG UWord16 status = ioctl(IIC, IIC_READ_STATUS_REG, NULL); This code reads content of the IIC Status Register. 5-798 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 917 // .. this (slave) node was just addressed // Now set test the IIC_SLAVE_TRANSMIT and set // Transmit or Receive mode accordingly This code tests the IAAS (Addressed as slave) bit in the Status Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-799...
Page 918 Range Issues: None. Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: IIC_CLEAR_ARBITRATION_LOST ioctl command implemented as a macro. Example 5-587. IIC_CLEAR_ARBITRATION_LOST ioctl(IIC, IIC_CLEAR_ARBITRATION_LOST, NULL); This code clears the “Arbitration Lost” status flag. 5-800 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 919 Range Issues: None. Special Issues: This command is applicable only on MC56F801x and MC56F800x. Design/Implementation: The IIC_CLEAR_I_BUS_INT ioctl command is implemented as a macro. Example 5-588. IIC_CLEAR_I_BUS_INT ioctl(IIC, IIC_CLEAR_I_BUS_INT, NULL);\ This code clears the interrupt flag. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-801...
Page 920 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The IIC_SET_GENERAL_CALL_ADDRESS ioctl command is implemented as a macro. Example 5-589. IIC_SET_GENERAL_CALL_ADDRESS ioctl(IIC, IIC_SET_GENERAL_CALL_ADDRESS, IIC_ENABLE); This code enables the General Call Address. 5-802 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 921 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The IIC_SET_ADDRESS_EXTENSION_MODE ioctl command is implemented as a macro. Example 5-590. IIC_SET_ADDRESS_EXTENSION_MODE ioctl(IIC, IIC_SET_ADDRESS_EXTENSION_MODE, IIC_10BIT); This code selects 10-bit address scheme. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-803...
Page 922 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The IIC_SET_ADDRESS_EXTENSION ioctl command is implemented as a macro. Example 5-591. IIC_SET_ADDRESS_EXTENSION ioctl(IIC, IIC_SET_ADDRESS_EXTENSION, (555>>8)); This code sets upper three bits of the slave address in the 10-bit address scheme. 5-804 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 923 Range Issues: UWord16 value must be in range of 0 to 1023. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The IIC_SET_10BIT_ADDRESS ioctl command is implemented as a macro. Example 5-592. IIC_SET_10BIT_ADDRESS ioctl(IIC, IIC_SET_10BIT_ADDRESS, 555); This code sets the 10-bit slave address. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-805...
Page 924 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The IIC_GET_10BIT_ADDRESS ioctl command is implemented as a macro. Example 5-593. IIC_GET_10BIT_ADDRESS UWord16 address=ioctl(IIC, IIC_GET_10BIT_ADDRESS, NULL); This code reads and returns the 10-bit slave address. 5-806 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 925 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The IIC_SET_FAST_ACK_NACK ioctl command is implemented as a macro. Example 5-594. IIC_SET_FAST_ACK_NACK ioctl(IIC, IIC_SET_FAST_ACK_NACK, IIC_DISABLE); This code disables the fast set up ACK/NACK response. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-807...
Page 926 Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The IIC_SET_SMBUS_RESPONSE_ADDRESS ioctl command is implemented as a macro. Example 5-595. IIC_SET_SMBUS_RESPONSE_ADDRESS ioctl(IIC, IIC_SET_SMBUS_RESPONSE_ADDRESS, IIC_ENABLE); This code ensables SMBus alert response address. 5-808 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 927 Returns: None. Range Issues: None. Special Issues: This command is applicable only on MC56F800x. Design/Implementation: IIC_SET_SECOND_IIC_ADDRESS ioctl command implemented as a macro. Example 5-596. IIC_SET_SECOND_IIC_ADDRESS ioctl(IIC, IIC_SET_SECOND_IIC_ADDRESS, IIC_DISABLE); This code disables SMBus device default address. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-809...
Page 928 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The IIC_SET_TIME_OUT_CLOCK ioctl command is implemented as a macro. Example 5-597. IIC_SET_TIME_OUT_CLOCK ioctl(IIC, IIC_SET_TIME_OUT_CLOCK, IIC_DIV1); This code select Time Out Counter clock to bus frequency. 5-810 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 929 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The IIC_TEST_TIMEOUT_FLAGS command is implemented as a macro. Example 5-598. IIC_TEST_TIMEOUT_FLAGS if(ioctl(IIC, IIC_TEST_TIMEOUT_FLAGS, IIC_LOW_TIMEOUT)) This code tests low timeout flag of the IIC module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-811...
Page 930 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The IIC_CLEAR_LOW_TIMEOUT_FLAG command is implemented as a macro. Example 5-599. IIC_CLEAR_LOW_TIMEOUT_FLAG if(ioctl(IIC, IIC_TEST_TIMEOUT_FLAGS, IIC_LOW_TIMEOUT ioctl(IIC, IIC_CLEAR_LOW_TIMEOUT_FLAG, NULL); This code shows how the low timeout flag is read, processed and cleared. 5-812 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 931 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The IIC_SET_SMBUS_ADDRESS ioctl command is implemented as a macro. Example 5-600. IIC_SET_SMBUS_ADDRESS ioctl(IIC, IIC_SET_SMBUS_ADDRESS, 100); This code sets the IIC SMBus slave address to 100. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-813...
Page 932 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The IIC_GET_SMBUS_ADDRESS ioctl command is implemented as a macro. Example 5-601. IIC_GET_SMBUS_ADDRESS UWord16 a; a = ioctl(IIC, IIC_GET_SMBUS_ADDRESS, NULL); This code reads the actual SMBus slave address. 5-814 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 933 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: IIC_WRITE_SCL_LOW_TIMEOUT ioctl command implemented as a macro. Example 5-602. IIC_WRITE_SCL_LOW_TIMEOUT ioctl(IIC, IIC_SET_TIME_OUT_CLOCK, IIC_DIV64); ioctl(IIC, IIC_WRITE_SCL_LOW_TIMEOUT, 10000); This code sets the SCL low timeout to 640000 bus clocks. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-815...
Page 934 Special Issues: This command is applicable only on MC56F800x. Design/Implementation: The IIC_READ_SCL_LOW_TIMEOUT ioctl command is implemented as a macro. Example 5-603. IIC_READ_SCL_LOW_TIMEOUT UWord16 a; a = ioctl(IIC, IIC_READ_SCL_LOW_TIMEOUT, NULL); This code reads the SCL low timeout value. 5-816 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 935: Iic Driver Sample Application
See the appconfig.h file listing for more details. The application can be found at e.g. sample_applications\MC56F8013DEMO\iic_demo directory and consists of the application project iic_demo.mcp, source code for the application main.c and configuration file appconfig.h. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-817...
Page 936: Iic Interrupt Handling
Figure 5-3. IIC Interrupt Handling 5-818 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 937: Iic Driver (Mc56F802X/3X)
This section is intended as a source of quick access information, while the details are discussed in Section 5.18.3. Table 5-684. IIC Module Base Address Module base address MC56F801x MC56F802x/3x MC56F83xx of / for IIC (IIC_BASE) N/A (different module) 0xF280 FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-819...
Page 938: Api Definition
Initial value of the IIC Fast Speed Clock High Count Register IIC_FSLCNT_INIT UWord16 Initial value of the IIC Fast Speed Clock Low Count Register IIC_IENBL_INIT UWord16 Initial value of the IIC Interrupt Enable Register 5-820 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 939: Api Specification
( item1 & item2 & item3 ) Table 5-687. ioctl commands param Return Description IIC_INIT NULL None Initializes IIC module by data from configuration file (appconfig.h). IIC_MODULE IIC_ENABLE/ None Enables or disables IIC device. IIC_DISABLE FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-821...
Page 940 Returns non-zero value when master transaction may be started. IIC_INITIATE_TRANSACTION UWord16 None Initiates standard transaction to the addressed target. (Address value. When 10-bit address is to be specified, combine the address value with: IIC_10BIT_ADDRESS) 5-822 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 941 IIC_RXOVR_INT | IIC_INT_DISABLE IIC_RXUND_INT | Error, General Call, Receiver, IIC_GC_INT | Transmitter, Status. IIC_RXFULL_INT | IIC_TXDONE_INT | IIC_RDREQ_INT | IIC_TXEMPTY_INT | IIC_STDET_INT | IIC_STPDET_INT | IIC_ACT_INT IIC_READ_INT_FLAGS NULL UWord16 Reads all interrupt flags. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-823...
Page 942 Only the following error flags are evaluated: IIC_STDET_INT | IIC_STPDET_INT | IIC_ACT_INT IIC_CLEAR_ALL_INTS NULL None Clears all interrupt flags and the TXABRTSRC register. IIC_READ_TXABORT_SOURCE NULL UWord16 Returns value of the TXABRTSRC Register. 5-824 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 943: Detailed Api Specification
Returns non-zero if any of given IIC_STAT_xxx bits Status Register bits is set. 5.18.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the usage of the ioctl commands. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-825...
Page 944 Example 5-604. IIC_INIT ioctl(IIC, IIC_INIT, NULL); This code initializes the IIC module by the values defined in the appconfig.h file. The appconfig.h file can be edited manually or generated by the Graphical Configuration Tool. 5-826 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 945 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The IIC_MODULE command is implemented as a macro. Example 5-605. IIC_MODULE /* enable it */ ioctl(IIC, IIC_MODULE, IIC_ENABLE); This code enables the IIC module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-827...
Page 946 Design/Implementation: The IIC_TRY_GRACEFUL_SHUTDOWN command is implemented as a function call. Example 5-606. IIC_TRY_GRACEFUL_SHUTDOWN if(ioctl(IIC,IIC_TRY_GRACEFUL_SHUTDOWN,0)==IIC_SHUTDOWN_SUCCESS) // IIC disabled else // IIC still active This code performs the graceful shutdown of the IIC module with a maximum possible time-out value. 5-828 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 947 Special Issues: This command is applicable only on MC56F802x/3x. This command may only be applied when IIC module is disabled. Design/Implementation: The IIC_SLAVE_OPERATION command is implemented as a macro. Example 5-607. IIC_SLAVE_OPERATION ioctl(IIC, IIC_SLAVE_OPERATION, IIC_ENABLE); This code enables the slave operation if the IIC module. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-829...
Page 948 Special Issues: This command is applicable only on MC56F802x/3x. This command may only be applied when IIC module is disabled. Design/Implementation: The IIC_MASTER_OPERATION command is implemented as a macro. Example 5-608. IIC_MASTER_OPERATION ioctl(IIC, IIC_MASTER_OPERATION, IIC_ENABLE); This code enables the master operation if the IIC module. 5-830 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 949 Design/Implementation: The IIC_USE_REPEATED_START command is implemented as a macro. Example 5-609. IIC_USE_REPEATED_START ioctl(IIC, IIC_USE_REPEATED_START, IIC_ENABLE); This code enables the repeated start signal to be generated by the IIC module when operating in master mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-831...
Page 950 Special Issues: This command is applicable only on MC56F802x/3x. This command may only be applied when IIC module is disabled. Design/Implementation: The IIC_SET_ADDRESS command is implemented as a macro. Example 5-610. IIC_SET_ADDRESS ioctl(IIC, IIC_SET_ADDRESS, 0x10); This code configures the 7-bit slave address of the IIC module. 5-832 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 951 Special Issues: This command is applicable only on MC56F802x/3x. This command may only be applied when IIC module is disabled. Design/Implementation: The IIC_SET_SPEED_MODE command is implemented as a macro. Example 5-611. IIC_SET_SPEED_MODE ioctl(IIC, IIC_SET_SPEED_MODE, IIC_FAST_SPEED); This code selects the fast speed mode. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-833...
Page 952 IIC_SET_FSHCNT, 43); ioctl(IIC, IIC_SET_FSLCNT, 37); This code selects the SCL high and low times for the fast speed mode. In result, the 400 kbps speed is selected when IIC operates at 32 MHz. 5-834 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 953 Design/Implementation: The IIC_CAN_INITIATE_TRANSACTION command is implemented as a macro. Example 5-613. IIC_CAN_INITIATE_TRANSACTION if(ioctl(IIC, IIC_CAN_INITIATE_TRANSACTION, NULL)) // initiate master transaction to a target address 0x10 ioctl(IIC, IIC_INITIATE_TRANSACTION, 0x10); This code checks if a new master transaction can be initiated. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-835...
Page 954 // initiate master transaction to a target address 0x10 ioctl(IIC, IIC_INITIATE_TRANSACTION, 0x10); This code checks if a new master transaction can be initiated and, if possible, it initiates the transaction to a node 0x10. 5-836 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 955 // initiate master transaction to a target address 0x10 ioctl(IIC, IIC_INITIATE_SB_TRANSACTION, 0x10); This code checks if a new master transaction can be initiated and, if possible, it initiates the “start byte” transaction to a node 0x10. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-837...
Page 956 IIC_CAN_INITIATE_TRANSACTION, NULL)) // initiate master transaction to a target address 0x10 ioctl(IIC, IIC_INITIATE_GC_TRANSACTION, NULL); This code checks if a new master transaction can be initiated and, if possible, it initiates the “general call” transaction. 5-838 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 957 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: IIC_MASTER_TRANSACTION_ACTIVE command implemented as a macro. Example 5-617. IIC_MASTER_TRANSACTION_ACTIVE if(ioctl(IIC, IIC_MASTER_TRANSACTION_ACTIVE, NULL)) // master transaction is in progress This code checks if a master transaction is in progress. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-839...
Page 958 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The IIC_CAN_READ_DATA command is implemented as a macro. Example 5-618. IIC_CAN_READ_DATA if(ioctl(IIC, IIC_CAN_READ_DATA, NULL)) data = ioctl(IIC, IIC_READ_DATA, NULL); This code checks if a receive byte is available and reads it. 5-840 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 959 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The IIC_READ_DATA command is implemented as a macro. Example 5-619. IIC_READ_DATA if(ioctl(IIC, IIC_CAN_READ_DATA, NULL)) data = ioctl(IIC, IIC_READ_DATA, NULL); This code checks if a receive byte is available and reads it. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-841...
Page 960 Design/Implementation: The IIC_CAN_WRITE_DATA command is implemented as a macro. Example 5-620. IIC_CAN_WRITE_DATA if(ioctl(IIC, IIC_CAN_WRITE_DATA, NULL)) ioctl(IIC, IIC_WRITE_DATA, data); This code checks if the IIC transmitter accepts another byte to its FIFO and, if yes, it writes the data byte for transmission. 5-842 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 961 Design/Implementation: The IIC_WRITE_DATA command is implemented as a macro. Example 5-621. IIC_WRITE_DATA if(ioctl(IIC, IIC_CAN_WRITE_DATA, NULL)) ioctl(IIC, IIC_WRITE_DATA, data); This code checks if the IIC transmitter accepts another byte to its FIFO and, if yes, it writes the data byte for transmission. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-843...
Page 962 Example 5-622. IIC_CAN_REQUEST_DATA if(ioctl(IIC, IIC_CAN_REQUEST_DATA, NULL)) ioctl(IIC, IIC_REQUEST_DATA, NULL); This code checks if the IIC receiver accepts another byte to its FIFO and, if yes, it requests the data byte to be shifted-in. 5-844 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 963 Design/Implementation: The IIC_READ_REQUEST command is implemented as a macro. Example 5-623. IIC_READ_REQUEST if(ioctl(IIC, IIC_CAN_REQUEST_DATA, NULL)) ioctl(IIC, IIC_READ_REQUEST, NULL); This code checks if the IIC receiver accepts another byte to its FIFO and, if yes, it requests the data byte to be shifted-in. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-845...
Page 964 Design/Implementation: The IIC_INT_ENABLE command is implemented as a macro. Example 5-624. IIC_INT_ENABLE ioctl(IIC, IIC_INT_ENABLE, IIC_RXFULL_INT | IIC_RDREQ_INT); This code enables the receiver-full and read-request interrupts - the ones needed when operating in slave mode. 5-846 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 965 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The IIC_INT_DISABLE command is implemented as a macro. Example 5-625. IIC_INT_DISABLE ioctl(IIC, IIC_INT_DISABLE, IIC_RXFULL_INT | IIC_RDREQ_INT); This code disables the receiver-full and read-request interrupts. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-847...
Page 966 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The IIC_READ_INT_FLAGS command is implemented as a macro. Example 5-626. IIC_READ_INT_FLAGS if(ioctl(IIC, IIC_READ_INT_FLAGS, NULL) & IIC_STAT_RXOVR) // IIC receiver overflow happened This code polls the receiver overrun error condition. 5-848 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 967 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The IIC_TEST_INT_FLAGS command is implemented as a macro. Example 5-627. IIC_TEST_INT_FLAGS if(ioctl(IIC, IIC_TEST_INT_FLAGS, IIC_STAT_RXOVR)) // IIC receiver overflow happened This code polls the receiver overrun error condition. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-849...
Page 968 & IIC_TXABRT_INT) // handle tx-abort interrupt if(irq & IIC_TXOVR_INT) // handle tx-overrun interrupt // clear all interrupt flags handled above ioctl(IIC, IIC_CLEAR_EINT_FLAGS, irq); This code processes and acknowledges the IIC error interrupt sources. 5-850 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 969 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The IIC_CLEAR_GINT_FLAGS command is implemented as a macro. Example 5-629. IIC_CLEAR_GINT_FLAGS // clear GC interrupt ioctl(IIC, IIC_CLEAR_GINT_FLAGS, IIC_GC_INT); This code acknowledges the IIC general-call interrupt source. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-851...
Page 970 & IIC_TXDONET_INT) // handle tx-done interrupt if(irq & IIC_RDREQ_INT) // handle read request interrupt // clear all interrupt flags handled above ioctl(IIC, IIC_CLEAR_TINT_FLAGS, irq); This code processes and acknowledges the IIC transmitter interrupt sources. 5-852 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 971 & IIC_STDET_INT) // handle start-detected interrupt if(irq & IIC_STPDET_INT) // handle stop-detected interrupt // clear all interrupt flags handled above ioctl(IIC, IIC_CLEAR_SINT_FLAGS, irq); This code processes and acknowledges the IIC status interrupt sources. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-853...
Page 972 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The IIC_CLEAR_ALL_INTS command is implemented as a macro. Example 5-632. IIC_CLEAR_ALL_INTS // clear all interrupt flags ioctl(IIC, IIC_CLEAR_ALL_INTS, NULL); This code clears all IIC interrupt sources and clears the TXABRTSRC Register. 5-854 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 973 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The IIC_READ_TXABORT_SOURCE command is implemented as a macro. Example 5-633. IIC_READ_TXABORT_SOURCE UWord16 abrtsrc = ioctl(IIC, IIC_READ_TXABORT_SOURCE, NULL); This code reads the Transmitter Abort Source Register. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-855...
Page 974 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The IIC_CLEAR_TXABORT_SOURCE command is implemented as a macro. Example 5-634. IIC_CLEAR_TXABORT_SOURCE ioctl(IIC, IIC_CLEAR_TXABORT_SOURCE, NULL); This code clears the Transmitter Abort Source register and interrupt flag. 5-856 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 975 Design/Implementation: The IIC_READ_STATUS_FLAGS command is implemented as a macro. Example 5-635. IIC_READ_STATUS_FLAGS if(ioctl(IIC, IIC_READ_STATUS_FLAGS, NULL) & IIC_STAT_ACT) // IIC is active This code reads the IIC Status Register and tests the “Activity” (ACT) bit. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-857...
Page 976 Special Issues: This command is applicable only on MC56F802x/3x. Design/Implementation: The IIC_TEST_STATUS_FLAGS command is implemented as a macro. Example 5-636. IIC_TEST_STATUS_FLAGS if(ioctl(IIC, IIC_TEST_STATUS_FLAGS, IIC_STAT_ACT)) // IIC is active This code tests “Activity” (ACT) bit in the IIC Status Register. 5-858 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 977: Iic Driver Applications
Please see the description of this application in section Section 5.17.4. The supported EVM boards for the IIC sample application are MC56F8025DEMO and MC56F8037EVM. Please see the application source code in {DSP56800E_Quick_Start Source}\..\sample_applications\EVM\iic_demo FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-859...
Page 978 5-860 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 979: Temperature Sensor System Driver
The following header files are needed in order to use the Temperature Sensor device driver: Required Header File(s): #include “qs.h” #include “tsensor.h” The following information may be found in the header file tsensor.h. Public Data Structure(s): None FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-861...
Page 980: Configuration Items
Table 5-723. Temperature Sensor Driver Arguments - ioctl pModuleBase Temperature Sensor module identifier. Use TSENSOR. Commands found in tsensor.h which are used to modify the Temperature Sensor module status and control registers. See Table 5-724. 5-862 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 981: Detailed Api Specification
UWord16 Returns the status of the Tem- perature Sensor System. 5.19.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code examples illustrate the ioctl commands usage. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-863...
Page 982 Range Issues: None. Special Issues: None. Design/Implementation: The TSENSOR_INIT ioctl command is implemented as a function. Example 5-637. TSENSOR_INIT ioctl(TSENSOR, TSENSOR_INIT, NULL); This code initializes the Temperature Sensor System module with the initialization value from appconfig.h. 5-864 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 983 TSENSOR_POWER_OFF. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The TSENSOR_DEVICE ioctl command is implemented as a macro. Example 5-638. TSENSOR_DEVICE ioctl(TSENSOR, TSENSOR_DEVICE, TSENSOR_POWER_ON); This code powers on the Temperature Sensor device. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-865...
Page 984 Special Issues: None. Design/Implementation: The TSENSOR_IS_POWERED_ON ioctl command is implemented as a macro. Example 5-639. TSENSOR_IS_POWERED_ON UWord16 tSensorPwr; tSensorPwr = ioctl(TSENSOR, TSENSOR_IS_POWERED_ON, NULL); This code stores the status of the Temperature Sensor System to variable tSensorPwr. 5-866 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 985: Temperature Sensor System Driver Application
5.19.4 Temperature Sensor System Driver Application FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-867...
Page 986 5-868 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 987: Quad Timer Driver
API Definition The following header files are needed in order to use the Quad Timer device driver: Required Header File(s): #include “qs.h“ #include “qtimer.h” The following information may be found in the header file qtimer.h. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-869...
Page 988: Configuration Items
Note - “xx” specifies the used timer. It can be A0, A1, A2, A3, B0, B1, B2, B3, C0, C1, C2, C3, D0, D1, D2, D3 or just 0, 1, 2, 3 in case of single timer. 5-870 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 989 & intersection of items is allowed ( item1 & item2 & item3 ) Table 5-731. ioctl commands param / pParam Return Description QT_INIT NULL None Initializes timer/counter by data from configuration file (appcon- fig.h). FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-871...
Page 990 Sets whether timer/counter is counting up or down. QT_CO_CHANNEL_INIT QT_ENABLE / QT_DISABLE None Enables/disables another timer in the same Quad Timer module to force re-initialization of this timer when it has encountered an active compare event. 5-872 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 991 QT_SET_CAPTURE_MODE QT_CAPTURE_DISABLED / None Sets Input Capture Mode. QT_RISING_EDGE / QT_FALLING_EDGE / QT_BOTH_EDGES QT_MASTER_MODE QT_ENABLE / QT_DISABLE None Enables/disables Master Mode. QT_EXT_OFLAG_FORCE QT_ENABLE / QT_DISABLE None Enables/disables external OFLAG force. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-873...
Page 992 Writes 16-bit value to the Timer REG2 Comparator Load Registers 2 (TMRCMPLD2). QT_WRITE_LOAD_REG UWord16 None Writes 16-bit value to the timer/counter Load Register (TMRLOAD). QT_WRITE_COUNTER_REG UWord16 None Writes 16-bit value to the timer/counter Counter Register (TMRCNTR). 5-874 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 993: Detailed Api Specification
Writes given value to the Input QT_WRITE_FILT_REG Filter Register. 5.20.3 Detailed API Specification The detailed functionality of all ioctl commands is explained in this section. The code example illustrates the usage of the ioctl commands. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-875...
Page 994 Range Issues: None. Special Issues: None. Design/Implementation: The QT_INIT ioctl command is implemented as a function call. Example 5-640. QT_INIT ioctl(QTIMER_D1, QT_INIT, NULL); This code initializes timer/counter D1 with the initialization values from appconfig.h. 5-876 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 995 Special modes affect also bits 2-0 (Output Mode), bit 6 (ONCE) and bit 5 (LENGTH). Bit 5 is not affected by QT_PULSE_OUTPUT_MODE. Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The QT_SET_COUNT_MODE ioctl command is implemented as a macro. Example 5-641. QT_SET_COUNT_MODE ioctl(QTIMER_D0, QT_SET_COUNT_MODE, QT_COUNT_RISING_EDGES_MODE); FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-877...
Page 996 This code sets the timer/counter D0 count mode to “Count rising edges of primary source“. The timer/counter starts counting immediately. ioctl(QTIMER_D0, QT_SET_COUNT_MODE, QT_NO_OPERATION); This code stops the timer/counter D0. 5-878 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 997 Quad Timer module. Design/Implementation: The QT_SET_PRIMARY_SOURCE ioctl command is implemented as a macro. Example 5-642. QT_SET_PRIMARY_SOURCE ioctl(QTIMER_B3, QT_SET_PRIMARY_SOURCE, QT_COUNTER0_OUTPUT); This code selects the primary count source timer/counter B0 output for timer/counter B3. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-879...
Page 998 Timer module as the timer/counter, which is selected by the parameter pModuleBase. Design/Implementation: The QT_SET_SECONDARY_SOURCE ioctl command is implemented as a macro. Example 5-643. QT_SET_SECONDARY_SOURCE ioctl(QTIMER_B3, QT_SET_SECONDARY_SOURCE, QT_COUNTER0_INPUT); This code selects the secondary count source timer/counter B0 input pin for timer/counter B3. 5-880 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...
Page 999 Range Issues: None. Special Issues: None. Design/Implementation: The QT_SET_COUNT_ONCE ioctl command is implemented as a macro. Example 5-644. QT_SET_COUNT_ONCE ioctl(QTIMER_C0, QT_SET_COUNT_ONCE, QT_COUNT_REPEATEDLY); This code selects the continuous count mode (count repeatedly) for timer/counter C0. FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-881...
Page 1000 Returns: None. Range Issues: None. Special Issues: None. Design/Implementation: The QT_SET_COUNT_LENGTH ioctl command is implemented as a macro. Example 5-645. QT_SET_COUNT_LENGTH ioctl(QTIMER_C0, QT_SET_COUNT_LENGTH, QT_ROLL_OVER); This code sets the binary roll over mode for timer/counter C0. 5-882 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR...