Programmable Chip-Select (56F827 only)
During a normal mode, external access, the data lines are driven only during an external write
cycle.
Table 7-3. Port A and PCS Operation with DRV Bit = 0
Mode
Normal Mode, External Access
Normal Mode, Internal Access
Stop Mode
Wait Mode
Reset Mode
Table 7-4. Port A and PCS Operation with DRV Bit = 1
Mode
Normal Mode, External Access
Normal Mode, Internal Access
Stop Mode
Wait Mode
Reset Mode
During a Normal mode external access, data lines are driven only during an external write cycle.
7.5 Programmable Chip-Select (56F827 only)
Typical systems require some external hardware to provide chip-selects for external peripherals.
Many of these devices do not have all the signals required for an asynchronous bus interface.
Additionally, higher levels of integration can provide cost, speed, and reliability advantages over
external logic. The programmable chip-selects described here provide the means to minimize this
external logic. The primary function of the chip-selects is to provide the chip enables for external
memory and peripheral devices. There are up to eight programmable chip-select signals
available. All chip-select pins are software programmable.
7.6 Chip Select Features (56F827 Only)
• Reduced system complexity
— No external glue logic required for typical systems, if the chip-selects are used.
• Eight programmable active-low chip-selects (PCS7 - PCS0)
• Control for external boot device
8
A0-A15
PS, DS, RD, WR
Driven
Driven
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Pulled High Internally
A0-A15
PS, DS, RD, WR
Driven
Driven
Driven
Driven
Driven
Driven
Driven
Driven
Driven
Pulled High Internally
56F826/827 User Manual, Rev. 3
Pins
PCSn (827 only)
Driven
Tri-stated
Tri-stated
Tri-stated
Pulled High Internally
Pins
PCSn (827 only)
Driven
Tri-stated
Tri-stated
Tri-stated
Pulled High Internally
Freescale Semiconductor
D0-D15
Driven
Tri-stated
Tri-stated
Tri-stated
Tri-stated
D0-D15
Driven
Tri-stated
Tri-stated
Tri-stated
Tri-stated
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