Freescale Semiconductor 56F800 User Manual page 94

On-Chip Peripheral Memory Map
Table 3-22. SSI Registers Address Map (
Register
Abbreviation
STX
SRX
SCSR
SCR2
STXCR
SRXCR
STSR
SFCSR
SOR
Table 3-23. SCI0 Registers Address Map (
Register
Abbreviation
SCI0_SCIBR
SCI0_SCICR
SCI0_SCISR
SCI0_SCIDR
Table 3-24. SCI1 Registers Address Map (
Register
Abbreviation
SCI1_SCIBR
SCI1_SCICR
SCI1_SCISR
SCI1_SCIDR
Table 3-25. 56F827 SCI2 Registers Address Map (
Register
Abbreviation
SCI2_SCIBR
SCI2_SCICR
SCI2_SCISR
SCI2_SCIDR
22
Register Description
Transmit Register
Receive Register
Control/Status Register 1
Control Register 2
Transmit Control Register
Receive Control Register
Time Slot Register
FIFO Control/Status Register
Reserved
Option Register
Register Description
Baud Rate Register
Control Register
Status Register
Data Register
Register Description
Baud Rate Register
Control Register
Status Register
Data Register
Register Description
Baud Rate Register
Control Register
Status Register
Data Register
56F826/827 User Manual, Rev. 3
)
SSI_BASE = $10E0
Address Offset Base Address
$0 SSI_BASE
$1 SSI_BASE
$2 SSI_BASE
$3 SSI_BASE
$4 SSI_BASE
$5 SSI_BASE
$6 SSI_BASE
$7 SSI_BASE
$9 SSI_BASE
)
SCI0_BASE = $1160
Address Offset Base Address
$0 SCI0_BASE
$1 SC0_BASE
$2 SCI0_BASE
$3 SCI0_BASE
)
SCI1_BASE = $1170
Address Offset Base Address
$0 SCI1_BASE
$1 SCI1_BASE
$2 SCI1_BASE
$3 SCI1_BASE
SCI2_BASE = $1180
Address Offset Base Address
$0 SCI2_BASE
$1 SCI2_BASE
$2 SCI2_BASE
$3 SCI2_BASE
Freescale Semiconductor
)