Freescale Semiconductor MC9S12ZVM series Reference Manual

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MC9S12ZVM-Family

Reference Manual

HCS12

Microcontrollers

Rev. 1.3

20 JAN 2014

MC9S12ZVMRMV1

freescale.com

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Summary of Contents for Freescale Semiconductor MC9S12ZVM series

Page 1 MC9S12ZVM-Family Reference Manual HCS12 Microcontrollers Rev. 1.3 20 JAN 2014 MC9S12ZVMRMV1 freescale.com...
Page 2 Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its ofﬁcers,...
Page 3: Table Of Contents
1.9.3 Low Power Modes ............50 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 4 2.5.2 Over-Current Protection on EVDD1 ........115 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 5 5.1.1 Glossary ............. 143 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 6 Application Information ............229 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 7 8.4.1 Phase Locked Loop with Internal Filter (PLL) ....... 293 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 8 9.8.2 List Usage — CSL single buffer mode and RVL double buffer mode ... . . 366 9.8.3 List Usage — CSL double buffer mode and RVL double buffer mode ... . . 367 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 9 11.6.2 Timer Overﬂow Interrupt (TOF) ......... . 402 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 10 13.4.3 Reload mechanism ........... . . 481 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 11 14.8.2 BLDC 6-Step Commutation ..........553 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 12 16.3.2 Register Descriptions ........... 601 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 13 18.1.1 Features ............. 663 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 14 19.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM ....738 19.5.3 Mode and Security Effects on Flash Command Availability ..... 739 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 15 H.1 Master Mode ..............783 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 16 L.20 0x0980-0x0987 LINPHY0 ............824 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 17: Introduction
I/O ports are available with interrupt capability allowing wake-up from stop or wait modes. The MC9S12ZVM-Family is a general-purpose family of devices suitable for a range of applications, including: • 3-phase sensorless BLDC motor control for — Fuel pump MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 18: Features
1. Options featuring a single SCI include the SCI1 instantiation 2. External CAN physical interface required 1.2.2 Functional Differences Between N06E and 0N95G Masksets NOTE N95G also includes bug ﬁxes that are not listed here because they do not constitute MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 19 — Added register access restrictions when DBG is disarmed but a proﬁling transmission is still active — Added a register bit to indicate that the proﬁling transmission is still active • — Improved handling of attempted internal accesses during STOP mode MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 20: Functional Differences Between 1N95G And 0N95G Masksets
On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages — Optional VREG ballast control output to supply an external CAN physical layer • Two current sense circuits for overcurrent detection or torque measurement MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 21: Module Features
— Four comparators (A, B, C and D) each conﬁgurable to monitor PC addresses or addresses of data accesses — A and C compare full address bus and full 32-bit data bus with data bus mask register — B and D compare full address bus only MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 22: Embedded Memory
— Automated program and erase algorithm — User margin level setting for reads 1.4.2.4 SRAM • Up to 8 KB of general-purpose RAM with ECC — Single bit error correction and double bit error detection MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 23: Clocks, Reset & Power Management Unit (Cpmu)
— Trimmed accuracy over -40°C to 150°C junction temperature range: ±1.3%max. 1.4.4 Main External Oscillator (XOSCLCP) • Amplitude controlled Pierce oscillator using 4 MHz to 20 MHz crystal — Current gain control on amplitude output — Signal with low harmonic distortion MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 24: Timer (Tim)
Current limitation for LIN Bus pin falling edge. • Over-current protection. • LIN TxD-dominant timeout feature monitoring the LPTxD signal. • Automatic transmitter shutdown in case of an over-current or TxD-dominant timeout. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 25: Serial Communication Interface Module (Sci)
Dual ADC — 12-bit resolution — Up to 9 external channels & 8 internal channels — 2.5us for single 12-bit resolution conversion — Left or right aligned result data — Continuous conversion mode MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 26: Supply Voltage Sensor (Bats)
Sustaining charge pump with two external capacitors and diodes • Optional boost convertor conﬁguration with voltage feedback • FET-Predriver desaturation and error recognition • Monitoring of FET High Side drain (HD) voltage • Diagnostic failure management MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 27: Current Sense
Chapter 1 Device Overview MC9S12ZVM-Family 1.4.16 Current Sense • 2 channel, integrated op-amp functionality MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 28: Block Diagram
Synchronous Serial IF Block Diagram shows the maximum configuration Not all pins or all peripherals are available on all devices and packages. Rerouting options are not shown. Figure 1-1. MC9S12ZVM-Family Block Diagram MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 29: Device Memory Map
Reserved 0x0500–0x053F 0x0540–0x057F Reserved 0x0580–0x059F 0x05A0–0x05BF Reserved 0x05C0–0x05EF TIM0 0x05F0–0x05FF Reserved 0x0600–0x063F ADC0 0x0640–0x067F ADC1 0x0680–0x069F Reserved 0x06A0–0x06BF 0x06C0–0x06DF CPMU 0x06E0–0x06EF Reserved 0x06F0–0x06F7 BATS 0x06F8–0x06FF Reserved 0x0700–0x0707 SCI0 0x0708–0x070F Reserved 0x0710–0x0717 SCI1 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 30 Reserved register space shown above is not allocated to any module. This register space is reserved for future use. Writing to these locations has no effect. Read access to these locations returns zero. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 31 Unmapped 6 MByte 0x80_0000 Program NVM max. 8 MB Unmapped address range Low address aligned High address aligned 0xFF_FFFF Figure 1-2. MC9S12ZVM-Family Global Memory Map. (See Table 1-2 for individual device details) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 32: Part Id Assignments
Table 1-5. Port Availability by Package Option Port 64 LQFP Port AD PAD[8:0] Port E PE[1:0] Port P PP[2:0] Port S PS[5:0] Port T PT[3:0] sum of ports MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 33: Detailed External Signal Descriptions
PP[2:0] are general-purpose input or output signals. The signals can be conﬁgured on per signal basis as interrupt inputs with wake-up capability (KWP[2:0]). They can have a pull-up or pull-down device selected and enabled on per signal basis. During and out of reset the pull devices are disabled. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 34 1.7.2.12 SCI[1:0] Signals 1.7.2.12.1 RXD[1:0] Signals These signals are associated with the receive functionality of the serial communication interfaces (SCI[1:0]). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 35 EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the internal PLLCLK, independent of EXTAL and XTAL. XTAL is the oscillator output. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 36 LIN Physical Layer Signals 1.7.2.21.1 LIN0 This pad is connected to the single-wire LIN data bus. This signal is only available on S12ZVML versions. 1.7.2.21.2 LP0TXD This is the LIN physical layer transmitter input signal. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 37 LS[2:0] - Low-Side Source signals The pins are the low-side source connections for the low-side power FETs. The pins are the power ground pins used to return the gate currents from the low-side power FETs. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 38 The MCU can supply an external CAN physical interface device directly, thus removing the need for an external voltage regulator. 1.7.2.23.1 BCTLC BCTLC provides the base current of an external bipolar that supplies an external CAN physical interface. This signal is only available on S12ZVMC versions. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 39: Power Supply Pins
1.7.3.4 VDDF, VSS1 — NVM Power and Ground Pin The VDDF voltage supply of nominally 2.8V is generated by the internal voltage regulator. The return current path is through the VSS1 pin. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 40: Package And Pinouts
The pin out details are shown in the following diagrams. Signals in brackets denote routing options. NOTE For the S12ZVM32 derivative the pins 1 and 64 are unused. Pin 64 must be connected to ground and pin1 left unconnected. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 41 PDOCLK / SCK0 / KWS4 / PS4 64-pin LQFP-EP VLS2 PDO / SS0 / KWS5 / PS5 VBS2 BCTL VSSB VBS0 VLS0 VLS_OUT VSUP Figure 1-3. MC9S12ZVM-Family 64-pin LQFP pin out - LIN PHY option MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 42 PDOCLK / SCK0 / KWS4 / PS4 64-pin LQFP-EP VLS2 PDO / SS0 / KWS5 / PS5 VBS2 BCTL VSSB VBS0 VLS0 VLS_OUT VSUP Figure 1-4. MC9S12ZVM-Family 64-pin LQFP pin out - External CAN PHY option MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 43 MOSI0 / (TXD1) / DBGEEV / KWS3 / PS3 PDOCLK / SCK0 / KWS4 / PS4 64-pin LQFP-EP VLS2 PDO / SS0 / KWS5 / PS5 VBS2 BCTL VSSB VBS0 VLS0 VLS_OUT VSUP Figure 1-5. MC9S12ZVM32 64-pin LQFP pin out MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 44 VSS2 — — — — — — — — — — — — — — — PAD0 KWAD0 AN0_0 AMP0 — — PERADL/ PPSADL PAD1 KWAD1 AN0_1 AMPM0 — — PERADL/ PPSADL MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 45 — — — — — — VLS1 — — — — — — — — VBS1 — — — — — — — — — — — — — — — — MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 46: Internal Signal Mapping
ADC Reference Voltages For both ADC modules, VRH_1 is mapped to VDDA; VRH_0 is mapped to PAD[8]; VRL_0 and VRL_1 are both mapped to VSSA, whereby VRL_1 is the preferred reference for low noise. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 47: Motor Control Loop Signals
GDU DC link voltage monitor Internal_4 Reserved Internal_5 Reserved Internal_6 Reserved Internal_7 Reserved 1. Selectable in CPMU 1.8.2 Motor Control Loop Signals The motor control loop signals are described in 1.13.3.1 Motor Control Loop Overview MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 48: Device Level Pmf Connectivity
The bus frequency must not be changed before launching the ERASE_FLASH command. 1.8.7 CPMU Connectivity The API clock generated in the CPMU is not mapped to a device pin in the MC9S12ZVM-Family. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 49: Modes Of Operation
The MC9S12ZVM-Family supports BDC communication throughout the device Stop mode. During Stop mode, writes to control registers can alter the operation and lead to unexpected results. It is thus recommended not to reconﬁgure the peripherals during STOP using the debugger. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 50: Low Power Modes
CPMU continues operation as in run mode. With BDC enabled and BDCCIS bit set, then all clocks remain active to allow BDC access to internal peripherals. If the BDC is enabled and MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 51: Security
SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’. Table 1-11. Security Bits SEC[1:0] Security State 1 (secured) 1 (secured) 0 (unsecured) 1 (secured) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 52: Operation Of The Secured Microcontroller
(e.g. through a serial port) The backdoor key access method allows debugging of a secured microcontroller without having to erase the Flash. This is particularly useful for failure analysis. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 53: Reprogramming The Security Bits
Power-On Reset (POR) None None Low Voltage Reset (LVR) None None External pin RESET None None Clock monitor reset None OSCE Bit in CPMUOSC register COP watchdog reset None CR[2:0] in CPMUCOP register MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 54: Interrupt Vectors
Vector base + 0x19C SCI0 I bit SCI0CR2 (TIE, TCIE, RIE, ILIE) Vector base + 0x198 SCI1 I bit SCI1CR2 (TIE, TCIE, RIE, ILIE) Vector base + 0x194 Reserved Vector base + 0x190 Reserved MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 55 GDU Voltage Limit Detected I bit GDUIE (GOCIE, GHHDFIE, GLVLSFIE) Vector base + 0x134 Reserved Vector base + 0x128 Vector base + 0x124 Port S interrupt I bit PIES[5:0] Vector base + 0x120 Reserved MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 56 Vector base + 0xC4 PMF Fault I bit PMFFIE(FIE[5:0]) Vector base + 0xC0 PMF Reload Overrun I bit PMFROIE(PMFROIEA,PMF ROIEB,PMFROIEC) Vector base + 0xBC Reserved Vector base + 0x10 1. 15 bits vector address based MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 57: Effects Of Reset
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register are loaded from the Flash conﬁguration ﬁeld byte at global address 0xFF_FE0E during the reset sequence. See Table 1-14 Table 1-15 for coding. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 58: Cpmu High Temperature Trimming
VDDA reference is limited by the internal voltage regulator accuracy. In order to compensate for VDDA reference voltage variation in this case, the reference voltage MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 59: Sci Baud Rate Detection
Motor Control Application Overview The following sections provide information for using the device in motor control applications. These sections provide a description of motor control loop considerations that are not detailed in the individual MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 60 – sensorless based on back-EMF ADC measurements 3. PMSM - high-end wiper, pumps, fans and blowers – simple sinewave commutation with position sensor Hall effect, sine-cos – FOC with sine-cos position sensor – sensorless 3-phase sinewave control MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 61 PTU, commands for the ADC and results from the ADC. If the PTU is enabled the reload and async_reload events are immediately passed through to the ADC and GDU modules. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 62 Regarding the raw PWM signal as the starting point and stepping through the control loop stages, the factors shown in Figure 1-8 contribute to delays within the control loop, starting with the deadtime MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 63 At the end of the conversion sequence the ﬁrst ADC command from the new sequence is loaded and the ADCx waits for the next trigger_x. The PTU continues to generate the trigger_x events for each trigger time from the list until a new reload or async_reload occurs. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 64 The main philosophy is that all cycle-by-cycle settings for cycle n need to be done within cycle n-1. The main control cycle synchronization event is the PMF reload event, which can be generated every n PWM periods. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 65 In some cases, the ADC values for the current control cycle can be ignored. 1.13.3.7 Asynchronous Timing This case is an extension of the dynamic timing case by an asynchronous event generated by the Timer. Note the asynchronous term is referenced to the control cycle. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 66 Once the measurement is properly conﬁgured (correct value is measured at deﬁned time) the output actuation (control action) is conﬁgured. The following modules are involved in signal measurements. • TIM (to identify asynchronous commutation) [BLDC applications only] MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 67 5. Execute the STOP instruction The return from stop is expected in reverse order: 1. On returning from Stop mode the clocks are automatically enabled coherently 2. Initialize and check device proper functionality (charge pump etc.) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 68: Bdcm Complementary Mode Operation
Brushed motor is driven by the DC voltage source. A rotational ﬁeld is created by means of commutator and brushes on the motor. These drives are still very popular because sophisticated calculations and algorithms such as commutation, waveform generation, or space vector modulation are not required. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 69 Driving the DC motor from a DC voltage source, the motor can work in all four quadrants. The complementary mode of operation with deadtime insertion is needed for smooth reversal of the motor MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 70 PWM0 and PWM1 is depicted at the top and the complementary PWM0 and PWM1 waveforms are shown with deadtime insertion depicted by the gray phases before the switching edges. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 71 Modulating the PWM duty cycle every period using the function F then the duty cycle is expressed as: PWM0 duty-cycle = 0.5 + (0.5 * F ); For -1<=F <= 1; PWM2 duty-cycle = 0.5 - (0.5 * F MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 72: Tim
PMFENCx[RSTRT]. If using the restart option, then select generator A as reload signal source and keep the following conﬁgurations at their default setting: multi timebase generators (PMFCFG0[MTG]=b0), reload frequency (PMFFQCx[LDFQx]=b0), prescaler (PMFFQCx[PRSCx]=b00). 6. Enable PMF commutation event input: PMFCFG1[ENCE]=1. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 73: Commutation_Event
ADC is used to measure the back-EMF voltage and the DC bus voltage to determine the zero crossing time. For slow motor rotation the GPHS register can be polled. In either case the zero crossing event is handled MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 74: Pmsm Control
9. Startup motor by applying FOC startup algorithm. 10. Take samples of the phase currents periodically based on PWM cycle to determine motor speed. 11. Calculate FOC algorithm to determine back EMF and motor position. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 75: Reloada
3. Select correct PMF deadtime insertion based on external FET switches. 4. Enable GDU current sense opamps for measuring the phase currents from external shunts. 5. Map the output pin of each current sense opamp to the ADC input. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 76: Glb_Ldok
13. Use FOC algorithm to determine back EMF and motor speed. Figure 1-15. PMSM Sine/Cosine Control Loop Conﬁguration zero crossing phase comparison dc_bus_voltage sine/cosine sensor reload glb_ldok trigger_0 ADC0 trigger_1 reload ADC1 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 77 1. Align rotor to stator ﬁeld. 2. Await phase comparator status change. 3. Switch to alternate duty cycle register to compensate distortion. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 78: Power Domain Considerations
ESD protection diodes exist between VDDX and VDDA, therefore forcing a common operating range. The VDD domain supplies the internal device logic. The VDDF domain supplies sections of the internal Flash NVM circuitry. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 79 The time it takes to discharge the bootstrap capacitor C can be calculated from the size of the bootstrap capacitor C the leakage current on VBSx pin. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 80 VBAT, by generating a voltage of VBAT+VLS-(2xVdiode). In a reverse battery scenario, the external bipolar turns on, ensuring that the HD pin is isolated from VBAT by the external NMOS, N1. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 81 Chapter 1 Device Overview MC9S12ZVM-Family Figure 1-17. High Side Supply and Charge Pump Concept VBAT VLS_OUT (11V) 10nF GCPCD GCPE 1000µF VBSx (Motor Dependent) HIGH SIDE LOW SIDE Diode voltage drop = Vdiode MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 82 Chapter 1 Device Overview MC9S12ZVM-Family MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 83: Introduction
- inputs can be used as an external interrupt and key-wakeup source Most I/O pins can be conﬁgured by register bits to select data direction and to enable and select pullup or pulldown devices. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 84: Features
This section lists and describes the signals that do connect off-chip. Table 2-1 shows all pins with the pins and functions that are controlled by the PIM. Routing options are denoted in parenthesis. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 85 BKGD MODC MODC input during RESET — BKGD BKGD I/O S12ZBDC communication — XTAL CPMU OSC signal — GPIO PTE[1] I/O General-purpose — EXTAL CPMU OSC signal — PTE[0] I/O General-purpose — MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 86 ADC0 analog input — PTADL[1]/ I/O General-purpose; with interrupt and wakeup — KWADL[1] PAD0 AMP0 O GDU AMP0 output — AN0_0 ADC0 analog input — PTADL[0]/ I/O General-purpose; with interrupt and wakeup — KWADL[0] MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 87 PTT[1] I/O General-purpose — (RXD0) SCI0 receive S0L0RR2-0 (MISO0) I/O SPI0 master in/slave out SPI0RR (PWM3) O PWM channel 3 PWM32RR PWMPRR IOC0_0 I/O TIM0 channel 0 — PTT[0] I/O General-purpose — MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 88 I/O General-purpose; with interrupt and wakeup — KWS[1] PTUT0 O PTU trigger 0 — (LPRXD0) O LINPHY0 receive output S0L0RR2-0 RXCAN0 MSCAN0 receive — RXD1 SCI1 receive SCI1RR PTS[0]/ I/O General-purpose; with interrupt and wakeup — KWS[0] MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 89: Memory Map And Register Deﬁnition
A stop or wait recovery with the X bit set (refer to S12ZCPU reference manual) is not available. Memory Map and Register Deﬁnition This section provides a detailed description of all port integration module registers. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 90: Register Map
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x020F Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0210– Reserved 0x025F 0x0260 PTE1 PTE0 0x0261 Reserved PTIE1 PTIE0 0x0262 PTIE 0x0263 Reserved MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 91 DDRADL7 DDRADL6 DDRADL5 DDRADL4 DDRADL3 DDRADL2 DDRADL1 DDRADL0 0x0286 PERADH PERADH0 0x0287 PERADL PERADL7 PERADL6 PERADL5 PERADL4 PERADL3 PERADL2 PERADL1 PERADL0 0x0288 PPSADH PPSADH0 0x0289 PPSADL PPSADL7 PPSADL6 PPSADL5 PPSADL4 PPSADL3 PPSADL2 PPSADL1 PPSADL0 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 92 0x02C0 PTT3 PTT2 PTT1 PTT0 PTIT3 PTIT2 PTIT1 PTIT0 0x02C1 PTIT 0x02C2 DDRT DDRT3 DDRT2 DDRT1 DDRT0 0x02C3 PERT PERT3 PERT2 PERT1 PERT0 0x02C4 PPST PPST3 PPST2 PPST1 PPST0 0x02C5– Reserved 0x02CF MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 93 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 0x02E0– Reserved 0x02EF 0x02F0 PTP2 PTP1 PTP0 PTIP2 PTIP1 PTIP0 0x02F1 PTIP 0x02F2 DDRP DDRP2 DDRP1 DDRP0 0x02F3 PERP PERP2 PERP1 PERP0 0x02F4 PPSP PPSP2 PPSP1 PPSP0 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 94: Pim Registers 0X0200-0X020F
SPI0RR SCI1RR S0L0RR2-0 — — SPI0 SS0 SPI0 SCI1 SCI0-LINPHY0 (see Figure 2-2) Reset Figure 2-1. Module Routing Register 0 (MODRR0) 1. Read: Anytime Write: Once in normal, anytime in special mode MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 95 PT1 / TXD0 / LPDC0 PS1 / LPTXD0 LINPHY0 SCI0 LPTXD0 TXD0 LPDR1 LPRXD0 RXD0 T0IC3RR1-0 PS0 / LPRXD0 RXD1 ACLK PT0 / RXD0 TIM0 input capture IOC0_3 channel 3 Figure 2-2. SCI0-to-LINPHY0 Routing Options Illustration MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 96 [S0L0RR2:S0L0RR0]=0b110 and disable the LINPHY0 (LPCR[LPE]=0). This releases PS0 and PS1 to other associated functions and maintains TXD0 and RXD0 signals on PT1 and PT0, respectively, if no other function with higher priority takes precedence. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 97 The PWM channel pair can be conﬁgured for internal use with the GDU or with its related external pins only. If set the signal routing to the pins is established and the related GDU inputs are forced low. 1 PWM0 to PP0; PWM1 to PP1 0 PWM0 to GDU; PWM1 to GDU MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 98 Hall sensors. An integrated XOR gate supports direct connection of the three sensor inputs to the device. 1 TIM0 input capture channel 1 is connected to logically XORed input signals of pins PT3-1 0 TIM0 input capture channel 1 is connected to PT1 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 99 IRQ Control Register (IRQCR) Address 0x0209 Access: User read/write IRQE IRQEN Reset Figure 2-6. IRQ Control Register (IRQCR) 1. Read: Anytime Write: IRQE: Once in normal mode, anytime in special mode IRQEN: Anytime MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 100 EVDD1” 1 PP0 over-current detector enabled 0 PP0 over-current detector disabled 2.3.2.7 Reserved Register Address 0x020E Access: User read/write Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset Figure 2-8. Reserved Register MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 101: Pim Generic Registers
Pull-device availability, pull-device polarity, wired-or mode, key-wake up functionality are independent of the prioritization unless noted differently. • For availability of individual bits refer to Section 2.3.1, “Register Map” and Table 2-22. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 102 1. Read: Anytime Write:Never This is a generic description of the standard port input registers. Refer to Table 2-22 to determine the implemented bits in the respective register. Unimplemented bits read zero. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 103 Note: Due to internal synchronization circuits, it can take up to two bus clock cycles until the correct value is read on port data and port input registers, when changing the data direction register. 1 Associated pin is conﬁgured as output 0 Associated pin is conﬁgured as input MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 104 The polarity is selected by the related polarity select register bit. On open- drain output pins only a pullup device can be enabled. 1 Pull device enabled 0 Pull device disabled MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 105 Read: Anytime Address 0x028C PIEADH Access: User read/write 0x028D PIEADL 0x02D6 PIES PIEx7 PIEx6 PIEx5 PIEx4 PIEx3 PIEx2 PIEx1 PIEx0 Reset Figure 2-15. Port Interrupt Enable Register 1. Read: Anytime Write: Anytime MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 106 Writing a logic “1” to the corresponding bit ﬁeld clears the ﬂag. 1 Active edge on the associated bit has occurred 0 No active edge occurred MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 107 1. Read: Anytime Write: Anytime This is a generic description of the standard reduced drive registers. Refer to Table 2-22 to determine the implemented bits in the respective register. Unimplemented bits read zero. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 108 1 Output buffers operate as open-drain outputs 0 Output buffers operate as push-pull outputs 2.3.3.11 PIM Reserved Register Address (any reserved) Access: User read Reset Figure 2-20. PIM Reserved Register MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 109: Pim Generic Register Exceptions
2.3.4.2 Port P Interrupt Enable Register (PIEP) Read: Anytime Address 0x02F6 PIEP Access: User read/write OCIE1 PIEP2 PIEP1 PIEP0 Reset Figure 2-22. Port P Interrupt Enable Register 1. Read: Anytime Write: Anytime MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 110: Functional Description
Section 2.3.3.7, “Port Interrupt Flag Register” PIFP2-0 Functional Description 2.4.1 General Each pin except BKGD can act as general-purpose I/O. In addition each pin can act as an output or input of a peripheral module. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 111: Registers
Pulldown forced off S12ZDBG PDO, PDOCLK Forced output Forced off DBGEEV None None PTURE, PTUT1-0 Forced output Forced off PWM channel PWMx Forced output Forced off PMF fault input FAULT5 Forced input None MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 112: Pin I/O Control
2-23). If more than one peripheral function is available and enabled at the same time, the highest ranked module according the predeﬁned priority scheme in Table 2-1 will take precedence on the pin. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 113: Interrupts
IRQCR[IRQEN] bit must be set and the I bit cleared in the condition code register. The interrupt can be conﬁgured for level-sensitive or falling-edge-sensitive triggering. If IRQCR[IRQEN] is cleared while an interrupt is pending, the request will deassert. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 114: Pin Interrupts And Key-Wakeup (Kwu)
Sample count <= 4 (at active or passive level) and interrupt enabled (PIE[x]=1) and interrupt ﬂag not set (PIF[x]=0). Glitch, ﬁltered out, no interrupt ﬂag set uncertain Valid pulse, interrupt ﬂag set P_MASK P_PASS Figure 2-25. Interrupt Glitch Filter (here: active low level selected) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 115: Over-Current Interrupt
An over-current condition is detected if the output current level exceeds the threshold I in run mode. The output driver is immediately forced low and the over-current interrupt ﬂag OCIFx asserts. Refer to Section 2.4.6, “Over-Current Interrupt”. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 116 Chapter 2 Port Integration Module (S12ZVMPIMV1) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 117: Introduction
S12ZBDC module. It also provides access to the RAM for ADCs and the PTU module. The S12ZMMC determines the address mapping of the on-chip resources, regulates access priorities and enforces memory protection. Figure 3-1 shows a block diagram of the S12ZMMC module. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 118: Glossary
Access violation detection and logging — Triggers S12ZCPU machine exceptions upon detection of illegal memory accesses and uncorrectable ECC errors — Logs the state of the S12ZCPU and the cause of the access error MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 119: Modes Of Operation
Table 3-3. External System Pins Associated With S12ZMMC Pin Name Description RESET External reset signal. The RESET signal is active low. MODC This input is captured in bit MODC of the MODE register when the external RESET pin deasserts. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 120: Memory Map And Register Deﬁnition
0x0087 MMCPCL CPUPC[7:0] 0x0088- Reserved 0x00FF = Unimplemented or Reserved Figure 3-2. S12ZMMC Register Summary 3.3.2 Register Descriptions This section consists of the S12ZMMC control and status register descriptions in address order. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 121 Reset with Reset with MODC pin = 1 MODC pin = 0 Normal Special Single-Chip Single-Chip Mode (NS) write access to Mode (SS) MODE: 1 → MODC bit Figure 3-4. Mode Transition Diagram MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 122 Target Field — The TGT[3:0] bits capture the target of the faulty access. The target is captured in form of a (MMCECH) TGT[3:0] 4 bit value which is assigned as follows: 0:none 1:register space 2:RAM 3:EEPROM 4:program ﬂash 5:IFR 6-15: reserved MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 123 3.3.2.3 Captured S12ZCPU Condition Code Register (MMCCCRH, MMCCCRL) Address: 0x0082 (MMCCCRH) CPUU Reset Address: 0x0083 (MMCCCRL) CPUX CPUI Reset Figure 3-6. Captured S12ZCPU Condition Code Register (MMCCCRH, MMCCCRL) Read: Anytime Write: Never MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 124 Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL) Address: 0x0085 (MMCPCH) CPUPC[23:16] Reset Address: 0x0086 (MMCPCM) CPUPC[15:8] Reset Address: 0x0087 (MMCPCL) CPUPC[7:0] Reset Figure 3-7. Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL) Read: Anytime Write: Never MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 125: Functional Description
The S12ZMMC maps all on-chip resources into an 16MB address space, the global memory map. The exact resource mapping is shown in Figure 3-8. The global address space is used by the S12ZCPU, ADCs, PTU, and the S12ZBDC module. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 126 6 KBKB 0x1F_C000 NVM IFR 256 Byte 0x20_0000 Unmapped 6 MByte 0x80_0000 Program NVM max. 8 MByte Unmapped address range Low address aligned High address aligned 0xFF_FFFF Figure 3-8. Global Memory Map MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 127: Illegal Accesses
Illegal accesses are reported in several ways: • All illegal accesses performed by the S12ZCPU trigger machine exceptions. • All illegal accesses performed through the S12ZBDC interface, are captured in the ILLACC bit of the BDCCSRL register. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 128: Uncorrectable Ecc Faults
S12ZCPU, ADC or PTU access triggers a machine exception. Uncorrectable memory corruptions which are detected during a S12ZBDC access, are captured in the RAMWF or the RDINV bit of the BDCCSRL register. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 129: Introduction
The INT module decodes the priority of all system exception requests and provides the applicable vector for processing the exception to the CPU. The INT module supports: • I-bit and X-bit maskable interrupt requests • One non-maskable unimplemented page1 op-code trap MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 130: Glossary
1. The vector base is a 24-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as the upper 15 bits of the address) and 0x000 (used as the lower 9 bits of the address). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 131: Modes Of Operation
In stop mode, the INT module is capable of waking up the CPU if an eligible CPU exception occurs. Please refer to Section 4.5.3, “Wake Up from Stop or Wait Mode” for details. 4.1.4 Block Diagram Figure 4-1 shows a block diagram of the INT module. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 132: External Signal Description
INT module registers. Table 4-3. INT Memory Map Address Access 0x000010–0x000011 Interrupt Vector Base Register (IVBR) 0x000012–0x000016 RESERVED — 0x000017 Interrupt Request Conﬁguration Address Register (INT_CFADDR) 0x000018 Interrupt Request Conﬁguration Data Register 0 (INT_CFDATA0) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 133: Register Descriptions
0x000017 INT_CFADDR R INT_CFADDR[6:3] 0x000018 INT_CFDATA0 R PRIOLVL[2:0] 0x000019 INT_CFDATA1 R PRIOLVL[2:0] 0x00001A INT_CFDATA2 R PRIOLVL[2:0] 0x00001B INT_CFDATA3 R PRIOLVL[2:0] 0x00001C INT_CFDATA4 R PRIOLVL[2:0] = Unimplemented or Reserved Figure 4-2. INT Register Summary MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 134: Address
Therefore, changing the IVBR has no effect on the location of the reset vector (0xFFFFFC–0xFFFFFF). 4.3.2.2 Interrupt Request Conﬁguration Address Register (INT_CFADDR) Address: 0x000017 INT_CFADDR[6:3] Reset = Unimplemented or Reserved Figure 4-4. Interrupt Conﬁguration Address Register (INT_CFADDR) Read: Anytime MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 135: Interrupt Request Conﬁguration Data Register
1. Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x000019 PRIOLVL[2:0] Reset = Unimplemented or Reserved Figure 4-6. Interrupt Request Conﬁguration Data Register 1 (INT_CFDATA1) 1. Please refer to the notes following the PRIOLVL[2:0] description below. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 136: Interrupt Request Conﬁguration Data Register 3 (Int_Cfdata3)
1. Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x00001D PRIOLVL[2:0] Reset = Unimplemented or Reserved Figure 4-10. Interrupt Request Conﬁguration Data Register 5 (INT_CFDATA5) 1. Please refer to the notes following the PRIOLVL[2:0] description below. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 137 (vector base + 0x0001DC) are ignored and read accesses return 0x07 (request is handled by the CPU, PRIOLVL = 7). Table 4-7. Interrupt Priority Levels Priority PRIOLVL2 PRIOLVL1 PRIOLVL0 Meaning Interrupt request is disabled Priority level 1 Priority level 2 Priority level 3 Priority level 4 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 138: Functional Description
3. The I-bit in the condition code register (CCW) of the CPU must be cleared. 4. There is no access violation interrupt request pending. 5. There is no SYS, SWI, SPARE, TRAP, Machine Exception or XIRQ request pending. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 139: Priority Decoder
(for details please refer to the Clock and Power Management Unit module (CPMU)): 1. Pin reset 2. Power-on reset 3. Low-voltage reset 4. Clock monitor reset request 5. COP watchdog reset request MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 140: Exception Priority
Figure 4-13. Interrupt Vector Table Entry Initialization/Application Information 4.5.1 Initialization After system reset, software should: • Initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xFFFE00–0xFFFFFB). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 141: Interrupt Nesting
Clear I-bit in the CCW by executing the CPU instruction CLI (thus allowing interrupt requests with higher priority) • Process data • Return from interrupt by executing the instruction RTI Stacked IPL IPL in CCW Processing Levels L3 (Pending) L1 (Pending) Reset Figure 4-14. Interrupt Processing Example MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 142: Wake Up From Stop Or Wait Mode
1. The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, the XIRQ pin is shared with other peripheral modules on the device. Please refer to the Port Integration Module (PIM) section of the MCU reference manual for details. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 143: Introduction
Normal Single Chip Mode (device operating mode) BDCSI Background Debug Controller Serial Interface. This refers to the single pin BKGD serial interface. EWAIT Optional S12 feature which allows external devices to delay external accesses until deassertion of EWAIT MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 144: Features
When operating in secure mode, BDC operation is restricted to allow checking and clearing security by mass erasing the on-chip ﬂash memory. Secure operation prevents BDC access to on-chip memory other than mass erase. The BDC command set is restricted to those commands classiﬁed as Always-available. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 145 If ACK handshaking is enabled, then the ﬁrst ACK, following a stop mode entry is long to indicate a stop exception. The BDC indicates a stop mode occurrence by setting the BDCCSR bit STOP. If the host attempts further communication before the ACK pulse generation then the OVRUN bit is set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 146: Block Diagram
If the part is still in Wait mode and a further STEP1 is carried out then the NORESP and ILLCMD bits are set because the device is no longer in active BDM for the duration of WAI execution. 5.1.4 Block Diagram A block diagram of the BDC is shown in Figure 5-1. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 147: External Signal Description
Memory Map and Register Deﬁnition 5.3.1 Module Memory Map Table 5-4 shows the BDC memory map. Table 5-4. BDC Memory Map Size Global Address Module (Bytes) Not Applicable BDC registers MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 148: Bit
— Bit 5 can only be written by WRITE_BDCCSR commands when the device is not in stop mode. — Bits 6, 1 and 0 cannot be written. They can only be updated by internal hardware. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 149 ﬂash array or by a soft reset. Reading this bit indicates the status of the requested mass erase sequence. 0 No ﬂash mass erase sequence pending completion 1 Flash mass erase sequence pending completion. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 150 RAM Write Fault — Indicates an ECC double fault during a BDC write access to RAM. RAMWF Writing a “1” to this bit, clears the bit. 0 No RAM write double fault detected. 1 RAM write double fault detected. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 151 (Section 5.4.5.1). Illegal accesses return a value of 0xEE for each data byte Writing a “1” to this bit, clears the bit. 0 No illegal access detected. 1 Illegal BDC access detected. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 152: Functional Description
After resetting into SSC mode, the initial PC address must be supplied by the host using the WRITE_Rn command before issuing the GO command. 1. BDM active immediately out of special single-chip reset. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 153: Clock Source
BDCSI Clock and FSM BDCFCLK CLKSW BDC device resource interface Core clock Figure 5-5. Clock Switch 5.4.4 BDC Commands BDC commands can be classiﬁed into three types as shown in Table 5-7. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 154 BDC shift register before the write has been completed. The external host must wait at least for 16 bdcsi cycles after a control command before starting any new serial command. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 155 ACK_ENABLE Always 0x02/dack Enable the communication handshake. Available Issues an ACK pulse after the command is executed. BACKGROUND Non-Intrusive 0x04/dack Halt the CPU if ENBDC is set. Otherwise, ignore as illegal command. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 156 READ_MEM.sz_WS Non-Intrusive (0x31+4 x sz)/ad24/d/ss/rd.sz Read the appropriately-sized (sz) memory value from the location speciﬁed by the 24- bit address and report status READ_DBGTB Non-Intrusive (0x07)/dack/rd32/dack/rd32 Read 64-bits of DBG trace buffer MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 157 BDCSI clock). 4. Removes all drive to the BKGD pin so it reverts to high impedance. 5. Listens to the BKGD pin for the sync response pulse. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 158 (ACK) pulse issued by the target MCU in response to a host command. The ACK_ENABLE command is interpreted and executed in the BDC logic without the need to interface MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 159 BDMACT is clear. Whilst in wait mode, with the pending BDM request, non-intrusive BDC commands are allowed. 5.4.4.5 DUMP_MEM.sz, DUMP_MEM.sz_WS DUMP_MEM.sz Read memory speciﬁed by debug address register, then Non-intrusive increment address 0x32 Data[7-0] MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 160 If enabled, an ACK pulse is driven before the data bytes are transmitted. The effect of the access size and alignment on the next address to be accessed is explained in more detail in Section 5.4.5.2”. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 161 0x13 Data[7-0] BDCCSRL host → host → target → target target host 0x17 Data[15-8] Data[7-0] BDCCSRL host → host → host → target → target target target host MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 162 If enabled, an ACK is driven on exiting active BDM. If a GO command is issued whilst the BDM is inactive, an illegal command response is returned and the ILLCMD bit is set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 163 This command reads the selected CPU registers and returns the 32-bit result. Accesses to CPU registers are always 32-bits wide, regardless of implemented register width. Bytes that are not implemented return MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 164 Byte alignment details are described in Section 5.4.5.2”. If the with-status option is speciﬁed, the BDCCSR status byte is returned before the read data. This status byte reﬂects the state MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 165 → target host host READ_SAME_WS Read same location speciﬁed by previous READ_MEM{_WS} Non-intrusive 0x55 BDCCSRL Data [15-8] Data [7-0] host → target → target → target → target host host host MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 166 PC address of the instruction currently being executed by the CPU. In active BDM, SYNC_PC returns the address of the next instruction to be executed on returning from active BDM. Thus following a write to the PC in active BDM, a SYNC_PC returns that written value. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 167 ACK pulse is generated after the internal write access has been completed or aborted. The hardware forces low-order address bits to zero longword accesses to ensure these accesses are on 0- modulo-size alignments. Byte alignment details are described in Section 5.4.5.2”. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 168 ERASE_FLASH commands then a timeout occurs, which forces a soft reset and initializes the sequence. The ERASE bit is cleared when the mass erase sequence has been completed. No ACK is driven. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 169: Bdc Access Of Internal Resources
CRN to CPU registers is shown in Table 5-9. Accesses to CPU registers are always 32-bits wide, regardless of implemented register width. This means that the BDC data transmission for these MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 170 5-10. Thus if address bits [1:0] are both logic “1” the access is realigned so that it does not straddle the 4-byte boundary but accesses data from within the addressed 4-byte ﬁeld. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 171 Accessed Accessed Accessed DUMP_MEM.32 0x004004 Accessed Accessed Accessed Accessed DUMP_MEM.16 0x004008 Accessed Accessed DUMP_MEM.16 0x00400A Accessed Accessed DUMP_MEM.08 0x00400C Accessed DUMP_MEM.16 0x00400D Accessed Accessed DUMP_MEM.16 0x00400E Accessed Accessed DUMP_MEM.16 0x004010 Accessed Accessed MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 172: Bdc Serial Interface
BDC. The BDC serial interface uses an internal clock source, selected by the CLKSW bit in the BDCCSR register. This clock is referred to as the target clock in the following explanation. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 173 1 from the target system. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 174 ﬁnishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then brieﬂy drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 175: Serial Interface Hardware Handshake (Ack Pulse) Protocol
ACK PULSE 32 CYCLES SPEED UP PULSE MINIMUM DELAY FROM THE BDC COMMAND BKGD PIN EARLIEST 16th CYCLE OF THE START OF LAST COMMAND BIT NEXT BIT Figure 5-9. Target Acknowledge Pulse (ACK) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 176 BDC DECODES COMMAND THE COMMAND Figure 5-10. Handshake Protocol at Command Level Alternatively, setting the STEAL bit conﬁgures the handshake protocol to make an immediate internal access, independent of free bus cycles. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 177: Hardware Handshake Abort Procedure
5.4.4.1”. Figure 5-11 shows a SYNC command being issued after a READ_MEM, which aborts the READ_MEM command. Note that, after the command is aborted a new command is issued by the host. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 178: Hardware Handshake Disabled (Ack Pulse Disabled)
ﬂagging is offered. If the ACK pulse protocol is disabled, the host needs to use the worst case delay time at the appropriate places in the protocol. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 179: Single Stepping
STEP1 has actually not ﬁnished. When an interrupt occurs the device leaves wait mode, enters active BDM and the PC points to the start of the corresponding interrupt service routine. A further ACK related to stepping over the WAI is not generated. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 180: Serial Communication Timeout
BDCSI clock frequency is expressed by Minimum f = (3/(#DLY cycles -4))f (core clock) (BDCSI clock) For the standard 16 period DLY this yields f >= (1/4)f (core clock) (BDCSI clock) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 181: Introduction
DBG module. Alternatively the DBG module can be conﬁgured over a serial interface using SWI routines. 6.1.1 Glossary Table 6-2. Glossary Of Terms Term Deﬁnition Change Of Flow. Change in the program ﬂow due to a conditional branch, indexed jump or interrupt Program Counter MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 182: Overview
— State transitions forced by software write to TRIG — State transitions forced by an external event • The following types of breakpoints — CPU breakpoint entering active BDM on breakpoint (BDM) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 183: Modes Of Operation
EVENT CONTROL MATCH1 COMPARATOR B BREAKPOINT MATCH2 REQUESTS COMPARATOR C MATCH3 COMPARATOR D TRACE CONTROL TRIGGER PROFILE OUTPUT TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 6-1. Debug Module Block Diagram MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 184: External Signal Description
Address Name Bit 7 Bit 0 0x0100 DBGC1 reserved BDMBP reserved EEVE BRKCPU TRIG 0x0101 DBGC2 CDCM ABCM Figure 6-2. Quick Reference to DBG Registers MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 185 DBGAA[23:16] 0x0116 DBGAAM DBGAA[15:8] 0x0117 DBGAAL DBGAA[7:0] 0x0118 DBGAD0 Bit 31 Bit 24 0x0119 DBGAD1 Bit 23 Bit 16 0x011A DBGAD2 Bit 15 Bit 8 Figure 6-2. Quick Reference to DBG Registers MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 186 DBGCA[23:16] 0x0136 DBGCAM DBGCA[15:8] 0x0137 DBGCAL DBGCA[7:0] 0x0138 DBGCD0 Bit 31 Bit 24 0x0139 DBGCD1 Bit 23 Bit 16 0x013A DBGCD2 Bit 15 Bit 8 Figure 6-2. Quick Reference to DBG Registers MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 187: Register Descriptions
DBG module registers that can be written are ARM, and TRIG 6.3.2.1 Debug Control Register 1 (DBGC1) Address: 0x0100 0x0100 reserved BDMBP BRKCPU reserved EEVE TRIG Reset Figure 6-3. Debug Control Register (DBGC1) Read: Anytime MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 188 External event function disabled External event forces a trace buffer entry if tracing is enabled External event is mapped to the state sequencer, replacing comparator channel 3 External event pin gates trace buffer entries MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 189 Match0 mapped to comparator A match..Match1 mapped to comparator B match. Match0 mapped to comparator A/B inside range..Match1 disabled. Match0 mapped to comparator A/B outside range..Match1 disabled. Reserved 1. Currently defaults to Match0 mapped to inside range: Match1 disabled MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 190 Trace only in address range from $00000 to Comparator D Trace only in address range from Comparator C to $FFFFFF Trace only in range from Comparator C to Comparator D Table 6-10. TRCMOD Trace Mode Bit Encoding TRCMOD Description Normal MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 191 Proﬁle Enable — This bit, when set, enables the proﬁle function, whereby a subsequent arming of the DBG PROFILE activates proﬁling. When PROFILE is set, the TRCMOD bits are ignored. 0 Proﬁle function disabled 1 Proﬁle function enabled MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 192 0xEEEE. The POR state is undeﬁned Other resets do not affect the trace buffer contents. 6.3.2.6 Debug Count Register (DBGCNT) Address: 0x0106 Reset — — — — — — — = Unimplemented or Reserved Figure 6-8. Debug Count Register (DBGCNT) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 193 Figure 6-1 and described in Section 6.3.2.12”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 194 These bits select the targeted next state whilst in State2 following a match0. 3–2 Channel 1 State Control. C1SC[1:0] These bits select the targeted next state whilst in State2 following a match1. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 195 These bits select the targeted next state whilst in State3 following a match1. 5–4 Channel 2 State Control. C2SC[1:0] These bits select the targeted next state whilst in State3 following a match2. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 196 0 No trace buffer overﬂow event 1 Trace buffer overﬂow event TRIG Flag — Indicates the occurrence of a TRIG event during the debug session. TRIGF 0 No TRIG event 1 TRIG event MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 197 State0 was entered during the session. On arming the module the state sequencer enters State1 and these bits are forced to SSF[2:0] = 001. See Table 6-24 Table 6-24. SSF[2:0] — State Sequence Flag Bit Encoding SSF[2:0] Current State State0 (disarmed) State1 State2 State3 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 198 Table 6-26 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if INST is set, because matches based on opcodes reaching the execution stage are data independent. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 199 DBGAA the address bus bits [15:0] to a logic one or logic zero. [15:0] 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 200 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Figure 6-17. Debug Comparator A Data Mask Register (DBGADM) Read: Anytime. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 201 Enable Bit — Determines if comparator is enabled COMPE 0 The comparator is not enabled 1 The comparator is enabled 1. If the ABCM ﬁeld selects range mode comparisons, then DBGACTL bits conﬁgure the comparison, DBGBCTL is ignored. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 202 DBGBA the address bus bits [15:0] to a logic one or logic zero. [15:0] 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 203 Table 6-34. Read or Write Comparison Logic Table RWE Bit RW Bit RW Signal Comment RW not used in comparison RW not used in comparison Write match No match No match MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 204 DBGCA the address bus bits [15:0] to a logic one or logic zero. [15:0] 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 205 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Figure 6-23. Debug Comparator C Data Mask Register (DBGCDM) Read: Anytime. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 206 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Enable Bit — Determines if comparator is enabled COMPE 0 The comparator is not enabled 1 The comparator is enabled MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 207 DBGDA the address bus bits [23:16] to a logic one or logic zero. [23:16] 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 208: Functional Description
Comparator Modes The DBG contains four comparators, A, B, C, and D. Each comparator compares the address stored in DBGXAH, DBGXAM, and DBGXAL with the PC (opcode addresses) or selected address bus (data MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 209 Table 6-41. Comparator Address Bus Matches Access Address ADDR[n] ADDR[n+1] ADDR[n+2] ADDR[n+3] 32-bit ADDR[n] Match Match Match Match 16-bit ADDR[n] Match Match No Match No Match 16-bit ADDR[n+1] No Match Match Match No Match MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 210 Case Address Size 32-bit DBGxD0 DBGxD1 DBGxD2 DBGxD3 32-bit DBGxD1 DBGxD2 DBGxD3 DBGxD0 32-bit DBGxD2 DBGxD3 DBGxD0 DBGxD1 32-bit DBGxD3 DBGxD0 DBGxD1 DBGxD2 16-bit DBGxD0 DBGxD1 16-bit DBGxD1 DBGxD2 16-bit DBGxD2 DBGxD3 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 211 (inside range) or outside the range (outside range). For opcode comparisons only the address of the ﬁrst opcode byte is compared with the range. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 212: Events
ﬁrst opcode byte for the match to occur. Opcode address matches are data independent thus the RWE and RW bits are ignored. CPU compares are disabled when BDM becomes active. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 213 ARM bit is cleared due to the hardware disarm. Table 6-45. Event Priorities Priority Source Action Highest TB Overﬂow Immediate force to state 0, generate breakpoint and terminate tracing MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 214: State Sequence Control
If tracing is disabled or End aligned triggering is selected, then when the Final State is reached the state sequencer returns to State0 immediately and the debug module is disarmed. If breakpoints are enabled, a breakpoint request is generated on transitions to State0. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 215: Trace Buffer Operation
Storing with Begin-Alignment, data is not stored in the trace buffer until the Final State is entered. Once the trigger condition is met the DBG module remains armed until 64 lines are stored in the trace buffer. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 216 COF addresses stored include the full address bus of CPU and an information byte, which contains bits to indicate whether the stored address was a source, destination or vector address. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 217 Normal mode proﬁling with timestamp is possible when tracing from a single source by setting the STAMP bit in DBGTCRL. This results in a different format (see Table 6-48). Table 6-47. Normal and Loop1 Mode Trace Buffer Format without Timestamp 8-Byte Wide Trace Buffer Line Mode MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 218 0 Trace buffer entry not initiated by a timestamp overﬂow 1 Trace buffer entry initiated by a timestamp overﬂow Table 6-50. CET Encoding Entry Type Description Non COF opcode address (entry forced by an external event) Vector destination address MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 219 Table 6-51. Detail Mode Trace Buffer Format without Timestamp 8-Byte Wide Trace Buffer Line Mode CDATA31 CDATA21 CDATA11 CDATA01 CINF1 CADRH1 CADRM1 CADRL1 Detail CDATA32 CDATA22 CDATA12 CDATA02 CINF2 CADRH2 CADRM2 CADRL2 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 220 Bit 2 Bit 1 Bit 0 CINF TSINF TOVF Figure 6-28. Information Bytes CINF and XINF When tracing in Detail Mode, CINF provides information about the type of CPU access being made. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 221 Each trace buffer line is ﬁlled from right to left. The ﬁnal entry on each line is always a base address, used as a reference for the previous entries on the same line. Whilst tracing, a base address is typically stored MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 222 When set, the STAMP bit in DBGTCRL conﬁgures the DBG to add a timestamp to trace buffer entries in Normal, Loop1 and Detail trace buffer modes. The timestamp is generated from a 16-bit counter and is stored to the trace buffer line each time a trace buffer entry is made. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 223 Whilst reading, an internal pointer is used to determine the next line to be read. After a tracing session, the pointer points to the oldest data entry, thus if no overﬂow has occurred, the pointer points to line0. The MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 224: Code Proﬁling
The external debugger uses both edges of the clock output to strobe the data on PDO. The ﬁrst PDOCLK edge is used to sample the ﬁrst data bit on PDO. Figure 6-30. Proﬁling Output Interface CLOCK PDOCLK DATA TBUF DEV TOOL MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 225 When the DBG module is disarmed but proﬁling transmission is ongoing, register write accesses are suppressed. When the DBG module is disarmed but proﬁling transmission is still ongoing, reading from the DBGTB returns the code 0xEE. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 226 PTIB/PTVB/PTHF format is used. Since the development tool receives the INFO byte ﬁrst, it can determine in advance the format of data it is about to receive. The MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 227 Line2 indicates that an indirect COF occurred after 8 direct COF entries. The indirect COF address is stored in bytes 7 to 5. All bits to the left of the stop bit are redundant. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 228: Breakpoints
Final State, then TRIG no longer has an effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent comparator match, it has no effect, since tracing has already started. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 229: Application Information
In this way it is possible to analyze the sequence of events emerging from reset. The recommended handling of the internal reset scenario is as follows: MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 230: Breakpoints From Other S12Z Sources
No start bit is provided. The external development tool must detect this ﬁrst rising edge after arming the DBG. To detect the end of proﬁling, the DBG ARM bit can be monitored using the BDC. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 231: Introduction
Memory Map and Register Deﬁnition This section provides a detailed description of all memory and registers for the SRAM_ECC module. 7.2.1 Register Summary Figure 7-1 shows the summary of all implemented registers inside the SRAM_ECC module. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 232 0x0009 DPTR[7:1] ECCDPTRL 0x000A - 0x000B Reserved 0x000C DDATA[15:8] ECCDDH 0x000D DDATA[7:0] ECCDDL 0x000E DECC[5:0] ECCDE 0x000F ECCDRR ECCDW ECCDR ECCDCMD = Unimplemented, Reserved, Read as zero Figure 7-1. SRAM_ECC Register Summary MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 233: Register Descriptions
Table 7-3. ECCIE Field Description Field Description Single bit ECC Error Interrupt Enable — Enables Single ECC Error interrupt. SBEEIE 0 Interrupt request is disabled 1 Interrupt will be requested whenever SBEEIF is set MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 234 Single bit ECC Error Interrupt Flag — The ﬂag is set to 1 when a single bit ECC error occurs. SBEEIF 0 No occurrences of single bit ECC error since the last clearing of the ﬂag 1 Single bit ECC error has occured since the last clearing of the ﬂag MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 235 There is no additional monitoring of the register content; therefore, the software must make sure that the address value points to the system memory space. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 236 ECC Debug ECC — This register contains the raw ECC value which will be written into the system memory DECC[5:0] during a debug write command or the ECC read value from the debug read command. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 237: Functional Description
Table 7-9. Memory access cycles access Memory Access type Internal operation Error indication error cycle content 2 and 4 byte aligned write — write to memory new data — access MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 238: Aligned 2 And 4 Byte Memory Write Access
2 byte non-aligned memory write access. If the module detects a double bit ECC error during the read cycle, then the write access to the memory is blocked and the initiator module is informed about the error. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 239: Memory Read Access
RDY status bit is set. 7.3.5 Interrupt Handling This section describes the interrupts generated by the SRAM_ECC module and their individual sources. Vector addresses and interrupt priority are deﬁned at the MCU level. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 240: Ecc Algorithm
DPTR. During this access, the raw data DDATA and the ECC value DECC are written directly into the system memory. If the debug write access is done, the ECCDW register bit is cleared. The debug write MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 241 During the debug read access no ECC check is performed, so that no single or double bit ECC error indication is activated. If the ECCDW and the ECCDR bits are set at the same time, then only the debug write access is performed. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 242 Chapter 7 ECC Generation Module (SRAM_ECCV1) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 243: Introduction
• The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal ﬁlter. • The Internal Reference Clock (IRC1M) provides a 1MHz internal clock. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 244: Features
Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based. • PLL stability is sufﬁcient for LIN communication in slave mode, even if using IRC1M as reference clock The Internal Reference Clock (IRC1M) has the following features: MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 245 — Power-on reset (POR) — Low-voltage reset (LVR) — COP time-out — Loss of oscillation (Oscillator clock monitor fail) — Loss of PLL clock (PLL clock monitor fail) — External pin RESET MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 246: Modes Of Operation
PLL conﬁguration is used for the selected oscillator frequency. — This mode can be entered from default mode PEI by performing the following steps: – Make sure the PLL conﬁguration is valid for the selected oscillator frequency. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 247 CSAD. When bit CSAD is set the ACLK clock source for the COP is stopped during Full Stop Mode and COP continues to operate after exit from Full Stop MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 248 Additionally the COP can be forced to the maximum time-out period in Active BDM Mode. For details please see also the RSBCK and CR[2:0] bit description ﬁeld of Table 8-13 Section 8.3.2.10, “S12CPMU_UHV_V6 COP Control Register (CPMUCOP) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 249: S12Cpmu_Uhv_V6 Block Diagram
Osc. RTI Interrupt RTIE COP time-out COPCLK IRCCLK to Reset Watchdog Generator IRCCLK Real Time OSCCLK RTICLK Interrupt (RTI) OSCCLK CPMUCOP COPOSCSEL0 RTIOSCSEL CPMURTI UPOSC=0 clears Figure 8-1. Block diagram of S12CPMU_UHV_V6 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 250 Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Figure 8-2 shows a block diagram of the XOSCLCP. OSCMOD Clock monitor fail Monitor OSCCLK Peak Gain Control Detector VDD=1.8V Quartz Crystals XTAL EXTAL Ceramic Resonators Figure 8-2. XOSCLCP Block Diagram MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 251: Signal Description
VDDA has to be connected externally to VDDX. 8.2.5 VDDX, VSSX— Pad Supply Pins VDDX is the supply domain for the digital Pads. An off-chip decoupling capacitor (10µF plus 220 nF(X7R ceramic)) between VDDX and VSSX is required. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 252: Bctl— Base Control Pin For External Pnp
Depending on the VSEL setting either the voltage level generated by the temperature sensor or the VREG bandgap voltage is driven to a special channel input of the ADC Converter. See device level speciﬁcation for connectivity of ADC special channels. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 253: Memory Map And Registers
0x000A CPMUPLL 0x000B CPMURTI RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 0x000C CPMUCOP WCOP RSBCK WRTMASK RESERVED 0x000D CPMUTEST0 RESERVED 0x000E CPMUTEST1 = Unimplemented or Reserved Figure 8-3. CPMU Register Summary MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 254 0x001A CPMUOSC OSCE Reserved 0x001B CPMUPROT PROT RESERVED 0x001C CPMUTEST2 CPMU 0x001D EXTCON EXTXON INTXON VREGCTL 0x001E CPMUOSC2 OMRE OSCMOD CPMU 0x001F RESERVED1F = Unimplemented or Reserved Figure 8-3. CPMU Register Summary MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 255: Register Descriptions
8.3.2.10, “S12CPMU_UHV_V6 COP Control Register (CPMUCOP) for details.This ﬂag can only be cleared by writing a 1. Writing a 0 has no effect. 0 COP reset has not occurred. 1 COP reset has occurred. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 256 The VCOFRQ[1:0] bits are used to conﬁgure the VCO gain for optimal stability and lock time. For correct PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 257 2MHz range. The bits can still be written but will have no effect on the PLL ﬁlter conﬁguration. For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufﬁcient stability). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 258 Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 8-3. Reference Clock Frequency Selection if OSC_LCP is enabled REFCLK Frequency Ranges REFFRQ[1:0] (OSCE=1) 1MHz <= f <= 2MHz 2MHz < f <= 6MHz 6MHz < f <= 12MHz >12MHz MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 259 (increases or decreases) f in order to avoid sudden load changes for the on-chip voltage regulator. 8.3.2.5 S12CPMU_UHV_V6 Interrupt Flags Register (CPMUIFLG) This register provides S12CPMU_UHV_V6 status bits and interrupt ﬂags. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 260 Oscillator Status Bit — UPOSC reﬂects the status of the oscillator. Writes have no effect. Entering Full Stop UPOSC Mode UPOSC is cleared. 0 The oscillator is off or oscillation is not qualiﬁed by the PLL. 1 The oscillator is qualiﬁed by the PLL. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 261 0 PLL LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. Oscillator Corrupt Interrupt Enable Bit OSCIE 0 Oscillator Corrupt interrupt requests are disabled. 1 Interrupt will be requested whenever OSCIF is set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 262 (write OMRE = 1 in CPMUOSC2 register). If the oscillator monitor reset feature is disabled (OMRE = 0) and the oscillator clock is used as system clock, the system will stall in case of loss of oscillation. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 263 1 COP continues running during Pseudo Stop Mode if COPOSCSEL=1 Note: If PCE=0 or COPOSCSEL=0 then the COP will go static while Stop Mode is active. The COP counter will not be reset. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 264 UPOSC= 0 clears the COPOSCSEL0 bit. 0 COP clock source is IRCCLK. 1 COP clock source is OSCCLK Table 8-7. COPOSCSEL1, COPOSCSEL0 clock source select description COPOSCSEL1 COPOSCSEL0 COP clock source IRCCLK OSCCLK ACLK MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 265 The modulation frequency is f divided by 16. See Table 8-9 for coding. Table 8-9. FM Amplitude selection FM Amplitude / Variation FM off ±1% ±2% ±4% MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 266 Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to RTR[3:0] provide additional granularity.Table 8-11 Table 8-12 show all possible divide values selectable by the CPMURTI register. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 267 15x2 1110 (÷15) 16x2 16x2 16x2 16x2 16x2 16x2 16x2 1111 (÷16) Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 268 1100 (÷13) 14x10 28x10 70x10 140x10 280x10 700x10 1.4x10 2.8x10 1101 (÷14) 15x10 30x10 75x10 150x10 300x10 750x10 1.5x10 3x10 1110 (÷15) 16x10 32x10 80x10 160x10 320x10 800x10 1.6x10 3.2x10 1111 (÷16) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 269 2. Writing WCOP bit (anytime in Special Mode, once in Normal Mode) with WRTMASK = 0. 3. Changing RSBCK bit from “0” to “1”. In Special Mode, any write access to CPMUCOP register restarts the COP time-out period. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 270 4) Operation in Special Mode Table 8-14. COP Watchdog Rates if COPOSCSEL1=0. (default out of reset) COPCLK Cycles to time-out (COPCLK is either IRCCLK or OSCCLK depending on the COPOSCSEL0 bit) COP disabled MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 271 Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Table 8-15. COP Watchdog Rates if COPOSCSEL1=1. COPCLK Cycles to time-out (COPCLK is ACLK divided by 2) COP disabled MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 272 Writing to this register when in Special Mode can alter the S12CPMU_UHV_V6’s functionality. Module Base + 0x000E Reset = Unimplemented or Reserved Figure 8-15. Reserved Register (CPMUTEST1) Read: Anytime Write: Only in Special Mode MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 273 Module Base + 0x0010 HTDS VSEL HTIE HTIF Reset = Unimplemented or Reserved Figure 8-17. High Temperature Control Register (CPMUHTCTL) Read: Anytime Write: VSEL, HTE, HTIE and HTIF are write anytime, HTDS is read only MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 274 Writing a 0 has no effect. If enabled (HTIE=1), HTIF causes an interrupt request. 0 No change in HTDS bit. 1 HTDS bit has changed. Figure 8-18. Voltage Access Select TEMPSENSE VSEL Channel MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 275 Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This ﬂag can only be cleared by LVIF writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request. 0 No change in LVDS bit. 1 LVDS bit has changed. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 276 This ﬂag can only be cleared by writing a 1.Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request. 0 API time-out has not yet occurred. 1 API time-out has occurred. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 277 Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) Figure 8-21. Waveform selected on API_EXTCLK pin (APIEA=1, APIFE=1) API min. period / 2 APIES=0 API period APIES=1 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 278 ACLKTR[4] Decreases period less than ACLKTR[5] increased it ACLKTR[3] Decreases period less than ACLKTR[4] ACLKTR[2] Decreases period less than ACLKTR[3] ACLKTR[1] Decreases period less than ACLKTR[2] ACLKTR[0] Decreases period less than ACLKTR[1] MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 279 For APICLK bit clear the ﬁrst time-out period of the API will show a latency time between two to three f cycles due to synchronous clock gate ACLK release when the API feature gets enabled (APIFE bit set) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 280 12 * Bus Clock period ..FFFD 131068 * Bus Clock period FFFE 131070 * Bus Clock period FFFF 131072 * Bus Clock period When f is trimmed to 20KHz. ACLK MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 281 Writing to this register when in Special Mode can alter the S12CPMU_UHV_V6’s functionality. Module Base + 0x0016 Reset = Unimplemented or Reserved Figure 8-25. Reserved Register (CPMUTEST3) Read: Anytime Write: Only in Special Mode MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 282 Table 8-25. Trimming Effect of HTTR Trimming Effect HTTR[3] Increases V twice of HTTR[2] HTTR[2] Increases V twice of HTTR[1] HTTR[1] Increases V twice of HTTR[0] HTTR[0] Increases V (to compensate Temperature Offset) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 283 0.15%, i.e. 0.3% is the distance between two trimming values). Figure 8-29 shows the relationship between the trim bits and the resulting IRC1M frequency. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 284 Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6) IRC1M frequency (IRCCLK) IRCTRIM[9:6] 1.5MHz ..IRCTRIM[5:0] 1MHz 600KHz IRCTRIM[9:0] $000 $3FF Figure 8-29. IRC1M Frequency Trimming Diagram MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 285 Setting TCTRIM[4:0] at 0x00000 or 0x10000 does not mean that the temperature coefﬁcient will be zero. These two combinations basically switch off the TC compensation module, which results in the nominal TC of the IRC1M. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 286 NOTE Since the IRC1M frequency is not a linear function of the temperature, but more like a parabola, the above relative variation is only an indication and should be considered with care. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 287 Figure 8-31. S12CPMU_UHV_V6 Oscillator Register (CPMUOSC) Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect. NOTE. Write to this register clears the LOCK and UPOSC status bits. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 288 Pseudo Stop Mode. UPOSC Do not alter this bit from its reset value. It is for Manufacturer use only and can change the Oscillator behavior. Reserved MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 289 (see list of protected registers above): Writing 0x26 to the CPMUPROT register clears the PROT bit, other write accesses set the PROT bit. 0 Protection of clock conﬁguration registers is disabled. 1 Protection of clock conﬁguration registers is enabled. (see list of protected registers above). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 290 Writing to this register when in Special Mode can alter the S12CPMU_UHV_V6’s functionality. Module Base + 0x001C Reset = Unimplemented or Reserved Figure 8-33. Reserved Register CPMUTEST2 Read: Anytime Write: Only in Special Mode MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 291 Internal voltage regulator Enable Bit for VDDX domain— Should be set to 1 if no external BJT is present on INTXON the PCB, cleared otherwise. 0 VDDX control loop does not use internal power transistor 1 VDDX control loop uses internal power transistor MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 292 If OSCE bit in CPMUOSC register is 1, then the OSCMOD bit can not be changed (writes will have no effect). 0 External oscillator conﬁgured for loop controlled mode (reduced amplitude on EXTAL and XTAL)) 1 External oscillator conﬁgured for full swing mode (full swing amplitude on EXTAL and XTAL) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 293: Functional Description
If PLL is selected (PLLSEL=1) f bus ------------ - NOTE Although it is possible to set the dividers to command a very high clock frequency, do not exceed the speciﬁed bus frequency limit for the MCU. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 294 , and is cleared when Lock the VCO frequency is out of the tolerance, ∆ • Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 295: Startup From Reset
Stop Mode due to clock domain crossing synchronization. This latency time occurs if COP clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for details). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 296: Full Stop Mode Using Oscillator Clock As Source Of The Bus Clock
Stop Mode due to clock domain crossing synchronization. This latency time occurs if COP clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for details). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 297: External Oscillator
EXTAL UPOSC ﬂag is set upon successful start of oscillation UPOSC OSCCLK select OSCCLK as Core/Bus Clock by writing PLLSEL to zero PLLSEL based on OSCCLK based on PLL Clock Core Clock MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 298: System Clock Conﬁgurations
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the PLL locks again. Application software needs to be prepared to deal with the impact of loosing the oscillator status at any time. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 299: Resets
Low Voltage Reset (LVR) None External pin RESET None PLL Clock Monitor Reset None Oscillator Clock Monitor Reset OSCE Bit in CPMUOSC register and OMRE Bit in CPMUOSC2 register COP Reset CR[2:0] in CPMUCOP register MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 300: Description Of Reset Operation
In case of loss of PLL clock oscillation or the PLL clock frequency is below the failure assert frequency (see device electrical characteristics for values), the S12CPMU_UHV_V6 generates a PLL Clock PMFA Monitor Reset. In Full Stop Mode the PLL and the PLL clock monitor are disabled. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 301: Computer Operating Properly Watchdog (Cop) Reset
Once this is done, the COP time-out period is restarted. If the program fails to do this and the COP times out, a COP reset is generated. Also, if any value other than $55 or $AA is written, a COP reset is generated. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 302: Power-On Reset (Por)
8-35. Refer to MCU speciﬁcation for related vector addresses and priorities. Table 8-35. S12CPMU_UHV_V6 Interrupt Vectors Interrupt Source Local Enable Mask RTI time-out interrupt I bit CPMUINT (RTIE) PLL lock interrupt I bit CPMUINT (LOCKIE) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 303: Description Of Interrupt Operation
Any change in PLL conﬁguration or any other event which causes the PLL lock status to be cleared leads to a loss of the oscillator status information as well (UPOSC=0). Oscillator status change interrupts are locally enabled with the OSCIE bit. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 304 It is possible to generate with the API a waveform at the external pin API_EXTCLK by setting APIFE and enabling the external access with setting APIEA. 1. For details please refer to “8.4.6 System Clock Conﬁgurations” MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 305: Initialization/Application Information
/* example for OSC = 4 MHz and Bus Clock = 25MHz, That is VCOCLK = 50MHz */ /* Initialize */ /* PLL Clock = 50 MHz, divide by one */ CPMUPOSTDIV = 0x00; /* Generally: Whenever changing PLL reference clock (REFCLK) frequency to a higher value */ MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 306 /* put your code to loop and wait for the LOCKIF or */ /* poll CPMUIFLG register until both LOCK status is “1” */ /* that is CPMIFLG == 0x18 */ /*....continue to your main code execution here....*/ MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 307: Introduction
The four bits of register ADCFLWCTL reﬂect the captured request and status of the four internal interface Signals (LoadOK, Trigger, Restart, and Seq_abort; see also Figure 9-2) if access conﬁguration is set accordingly and indicate event progress (when an event is processed and when it is ﬁnished). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 308 ﬁnished respectively aborted, which could take up to a maximum latency time of t (see device level speciﬁcation for more details). DISABLE MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 309: Key Features
Conversion Command (CSL) loading possible from System RAM or NVM • Single conversion ﬂow control register with software selectable access path • Two conversion ﬂow control modes optimized to different application use cases MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 310: Modes Of Operation
— The RVL buffer select (RVL_SEL) is not changed if a CSL is in process at MCU Stop Mode request. Hence the same buffer will be used after exit from Stop Mode that was used when the Stop Mode request occurred. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 311 — The RVL buffer select (RVL_SEL) is not changed if a CSL is in process at MCU Wait Mode request. Hence the same RVL buffer will be used after exit from Wait Mode that was used when Wait Mode request occurred. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 312 Freeze Mode is entered. After exit from MCU Freeze Mode with previously frozen conversion sequence the ADC continues the conversion with the next conversion command and all ADC interrupt ﬂags are unchanged during MCU Freeze Mode. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 313: Block Diagram
Register (SAR) VRL_0 ... Alternative and C-DAC ... Result ... List VDDA ... (RAM) Result 63 VSSA Final ..Buffer ext. Buffer Comparator Channel Sample & Hold ADC12B_LBA Figure 9-2. ADC12B_LBA Block Diagram MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 314: Signal Description
Please refer to the device reference manual for availability and connectivity of these pins. 9.3.1.3 VDDA, VSSA These pins are the power supplies for the analog circuitry of the ADC12B_LBA block. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 315: Memory Map And Register Deﬁnition
0x000B ADCCONIE_1 CON_IE[7:1] EOL_IE 0x000C ADCCONIF_0 CON_IF[15:8] 0x000D ADCCONIF_1 CON_IF[7:1] EOL_IF R CSL_IMD RVL_IMD 0x000E ADCIMDRI_0 RIDX_IMD[5:0] 0x000F ADCIMDRI_1 = Unimplemented or Reserved Figure 9-3. ADC12B_LBA Register Summary (Sheet 1 of 3) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 316: Address Name Bit
ADCRIDX 0x0021 ADCRBP_0 RES_PTR[19:16] 0x0022 ADCRBP_1 RES_PTR[15:8] 0x0023 ADCRBP_2 RES_PTR[7:2] CMDRES_OFF0[6:0] 0x0024 ADCCROFF0 0x0025 ADCCROFF1 CMDRES_OFF1[6:0] 0x0026 Reserved Reserved = Unimplemented or Reserved Figure 9-3. ADC12B_LBA Register Summary (Sheet 2 of 3) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 317 Name Bit 7 Bit 0 0x0027 Reserved Reserved 0x0028 Reserved Reserved R Reserved Reserved 0x0029 Reserved 0x002A- Reserved 0x003F = Unimplemented or Reserved Figure 9-3. ADC12B_LBA Register Summary (Sheet 3 of 3) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 318: Adc_En
ADC freezes the conversion at next conversion boundary at Freeze Mode entry. Wait Mode Conﬁguration — This bit inﬂuences conversion ﬂow during Wait Mode. SWAI ADC continues conversion in Wait Mode. ADC halts the conversion at next conversion boundary at Wait Mode entry. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 319 Each conversion ﬂow control bit (SEQA, RSTA, TRIG, LDOK) must be controlled by software or internal interface according to the requirements described in Section 9.5.3.2.4, “The two conversion ﬂow control Mode Conﬁgurations and overview summary in Table 9-10. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 320: Csl_Bmod Rvl_Bmod Smod_Acc Aut_Rsta
ADC conversion ﬂow control mode “Trigger Mode” and “Restart Mode” (anytime during application runtime). No automatic Restart Event after exit from MCU Stop Mode. 1 Automatic Restart Event occurs after exit from MCU Stop Mode. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 321: Csl_Sel
Sequence Abort Event after exit from MCU Wait Mode (see also the Note in Section 9.2.1.2, “MCU Operating Modes). 0 ADC not in idle state. 1 ADC is in idle state. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 322 ADC Clock Prescaler — These 7bits are the binary prescaler value PRS. The ADC conversion clock frequency PRS[6:0] is calculated as follows: f BUS ----------------------------------- - Refer to Device Speciﬁcation for allowed frequency range of f ATDCLK MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 323 SRES[0] ADC Resolution 8-bit data Reserved 10-bit data Reserved 12-bit data Reserved Reserved settings cause a severe error at ADC conversion start whereby the CMD_EIF ﬂag is set and ADC ceases operation MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 324: Seqa Trig Rsta
ﬁve Bus Clock cycles plus an uncertainty of a few Bus Clock cycles. For more details regarding the sample phase please refer to Section 9.5.2.2, “Sample and Hold Machine with Sample Buffer Ampliﬁer. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 325 This bit can be controlled via the internal interface Signal “Trigger” if access control is conﬁgured accordingly via ACC_CFG[1:0]. After being set an additional request via internal interface Signal “Trigger“ causes the ﬂag TRIG_EIF to be set. 0 No conversion sequence trigger. 1 Trigger to start conversion sequence. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 326 The LDOK_EIF error ﬂag is also not set in “Restart Mode” if the ﬁrst Restart Event occurs after: - ADC got enabled - Exit from Stop Mode - ADC Soft-Reset 0 Load of alternative list done. 1 Load alternative list. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 327 Section 9.5.3.2.4, “The two conversion ﬂow control Mode Conﬁgurations, Section 9.5.3.2.5, “The four ADC conversion ﬂow control bits Section 9.5.3.2.6, “Conversion ﬂow control in case of conversion sequence control bit overrun scenarios MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 328: Ia_Eie Cmd_Eie
1 Restart Request error interrupt enabled. Load OK Error Interrupt Enable Bit — This bit enables the Load OK error interrupt. LDOK_EIE 0 Load OK error interrupt disabled. 1 Load OK error interrupt enabled. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 329: Seqad_Ie Conif_Oie Reserved
ADCCONIF Register Flags Overrun Interrupt Enable — This bit enables the ﬂag which indicates if an overrun CONIF_OIE situation occurred for one of the CON_IF[15:1] ﬂags or for the EOL_IF ﬂag. 0 No ADCCONIF Register Flag overrun occurred. 1 ADCCONIF Register Flag overrun occurred. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 330: Ia_Eif Cmd_Eif
CSL. The ADC ceases operation if this error ﬂag is set (issue of type severe). 0 No “End Of List” error. 1 “End Of List” command type missing in current executed CSL. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 331 - ADC Soft-Reset - ADC used in CSL single buffer mode The ADC continues operation if this error ﬂag is set. 0 No Load OK error situation occurred. 1 Load OK error situation occurred. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 332 The overrun is detected if any of the conversion interrupt ﬂags (CON_IF[15:1]) is set while the ﬁrst conversion result of a CSL is stored (result of ﬁrst conversion from top of CSL is stored). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 333: Eol_Ie
1 ADC conversion interrupt enabled. End Of List Interrupt Enable Bit — This bit enables the end of conversion sequence list interrupt. EOL_IE 0 End of list interrupt disabled. 1 End of list interrupt enabled. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 334: Eol_If
ﬂag can be used again (see also Section 9.8.6, “RVL swapping in RVL double buffer mode and related registers ADCIMDRI and ADCEOLRI. NOTE Overrun situation of a ﬂag CON_IF[15:1] and EOL_IF are indicated by ﬂag CONIF_OIF. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 335 The register ADCIMDRI is updated and simultaneously a conversion interrupt ﬂag CON_IF[15:1] occurs when the corresponding conversion command (conversion command with INTFLG_SEL[3:0] set) has been processed and related data has been stored to RAM. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 336 NOTE The conversion interrupt EOL_IF occurs and simultaneously the register ADCEOLRI is updated when the “End Of List” conversion command type has been processed and related data has been stored to RAM. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 337 Continue Conversion) End Of List (Wrap to top of CSL and: - In “Restart Mode” wait for Restart Event followed by a Trigger - In “Trigger Mode” wait for Trigger or Restart Event) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 338 Table 9-21. Conversion Interrupt Flag Select CON_IF[15:1] INTFLG_SEL[3] INTFLG_SEL[2] INTFLG_SEL[1] INTFLG_SEL[0] Comment 0x0000 No ﬂag set 0x0001 0x0002 0x0004 0x0008 Only one ﬂag can 0x0010 be set ..(one hot coding) 0x0800 0x1000 0x2000 0x4000 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 339 Table 9-23. Analog Input Channel Select CH_SEL[5] CH_SEL[4] CH_SEL[3] CH_SEL[2] CH_SEL[1] CH_SEL[0] Analog Input Channel VRL_0/1 VRH_0/1 (VRH_0/1 + VRL_0/1) / 2 Reserved Reserved Reserved Reserved MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 340 Table 9-23 is the maximum number of implemented analog input channels on the device. Please refer to the device overview of the reference manual for details regarding number of analog input channels. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 341 If bit SMOD_ACC is set modifying this register must be done carefully - only when no conversion and conversion sequence is ongoing. Table 9-25. Sample Time Select Sample Time SMP[4] SMP[3] SMP[2] SMP[1] SMP[0] in Number of ADC Clock Cycles MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 342 Chapter 9 Analog-to-Digital Converter (ADC12B_LBA_V1) Table 9-25. Sample Time Select Sample Time SMP[4] SMP[3] SMP[2] SMP[1] SMP[0] in Number of ADC Clock Cycles Reserved Reserved Reserved Reserved MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 343 Chapter 9 Analog-to-Digital Converter (ADC12B_LBA_V1) 9.4.2.18 ADC Command Register 3 (ADCCMD_3) Module Base + 0x0017 Reserved Reserved Reserved Reset = Unimplemented or Reserved Figure 9-21. ADC Command Register 3 (ADCCMD_3) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 344 CSL start addresses in the memory map. These bits do not represent absolute addresses [5:0] instead it is a sample index (object size 32bit). See also Section 9.5.3.2.2, “Introduction of the two Command Sequence Lists (CSLs) for more details. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 345 RAM or NVM of the memory map. They are used to calculate the ﬁnal address from which the conversion commands will be loaded depending on which list is active. For more details see Section 9.5.3.2.2, “Introduction of the two Command Sequence Lists (CSLs). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 346 RVL start addresses in the memory map. These bits do not represent absolute addresses instead it is a sample index (object size 16bit). See also Section 9.5.3.2.3, “Introduction of the two Result Value Lists (RVLs) for more details. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 347 RAM of the memory map to which conversion results will be stored to at the end of a conversion. These bits can only be written if bit ADC_EN is clear. See also Section 9.5.3.2.3, “Introduction of the two Result Value Lists (RVLs). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 348 (object size 16bit for RVL, object size 32bit for CSL). See also Section 9.5.3.2.2, “Introduction of the two Command Sequence Lists (CSLs) Section 9.5.3.2.3, “Introduction of the two Result Value Lists (RVLs) for more details. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 349 RVL, object size 32bit for CSL).,These bits can only be modiﬁed if bit ADC_EN is clear. See also Section 9.5.3.2.2, “Introduction of the two Command Sequence Lists (CSLs) Section 9.5.3.2.3, “Introduction of the two Result Value Lists (RVLs) for more details. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 350: Functional Description
(Resolution Dependent Length: SRES[2:0]) Sample CAP hold phase "Buffer" "Final" Sample Time Sample Time (2 cycles) (N - 2 cycles) ADC_CLK Figure 9-28. Sampling and Conversion Timing Example (8-bit Resolution, 4 Cycle Sampling) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 351: Digital Sub-Block
(bits CSL_BMOD, RVL_BMOD). The 32-bit wide conversion command is double buffered and the currently active command is visible in the ADC register map at ADCCMD register space. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 352 Command_11 normal conversion to proceed Sequence_3 Command_12 normal conversion Wait for RSTA or LDOK+RSTA Command_13 End Of List Figure 9-29. Example CSL with sequences and an “End Of List” command type identiﬁer MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 353 Command_8 normal conversion Command_9 normal conversion Command_10 normal conversion Command_11 normal conversion Command_12 normal conversion Command_13 End Of List, wrap to top, continue Figure 9-30. Example CSL for continues conversion MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 354 RAM or NVM end address Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index Figure 9-31. Command Sequence List Schema in Double Buffer Mode MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 355 CSL double buffered mode. When the ADC is enabled, the command address registers (ADCCBP, ADCCROFF_0/2, ADCCIDX) are read only and register ADCCIDX is under control of the ADC. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 356 RAM end address Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index Figure 9-33. Result Value List Schema in Double Buffer Mode MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 357 Table 9-32. Conversion Result Justiﬁcation Overview Conversion Resolution Left Justiﬁed Result Right Justiﬁed Result (SRES[1:0]) (DJM = 1’b0) (DJM = 1’b1) 8 bit {Result[7:0],8’b00000000} {8’b00000000,Result[7:0]} 10 bit {Result[9:0],6’b000000} {6’b000000,Result[9:0]} 12 bit {Result[11:0],4’b0000} {4’b0000,Result[11:0]} MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 358 — When is the event ﬁnished — Mandatory requirements to executed the event A summary of all event combinations is provided by Table 9-10. • Trigger Event Internal Interface Signal: Trigger Corresponding Bit Name: TRIG MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 359 * The current CSL has been aborted or is about to be aborted due to a Sequence Abort Request. – Requested by: - Positive edge of internal interface signal Restart - Write Access via data bus to set control bit RSTA MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 360 Bit LDOK can only be cleared if it was set as described before and both bits (LDOK, RSTA) are cleared when the ﬁrst conversion command from top of active Sequence Command List is loaded – Mandatory Requirement: No ongoing conversion or conversion sequence Details if using the internal interface: MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 361 * A Sequence Abort request is about to be executed or has been executed. In case bit SEQA is set automatically the Restart error ﬂag RSTA_EIF is set to indicate an unexpected Restart Request. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 362 Sequence Abort Request Overrun: If a Sequence Abort Request occurs whilst bit SEQA is already set, this is deﬁned as a Sequence Abort Request Overrun situation and the overrun request is ignored. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 363 Trigger Event to continue. • If the last executed conversion command was of type “Normal Conversion” the ADC continues command execution in the order of the current CSL (continues conversion). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 364: Resets
The ADC provides one sequence abort done interrupt associated with the sequence abort request for conversion ﬂow control. Hence, there is only one dedicated interrupt ﬂag and interrupt enable bit for conversion sequence abort and it occurs when the sequence abort is done. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 365: Adc Error And Conversion Flow Control Issue Interrupt
In order to make the ADC operational again an ADC Soft-Reset must be issued. Remaining error interrupt ﬂags cause an error interrupt if enabled, but ADC continues operation. The related interrupt ﬂags are: • RSTAR_EIF • LDOK_EIF • CONIF_OIF MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 366: Use Cases And Application Information
The last entirely ﬁlled RVL (an RVL where the corresponding CSL has been executed including the “End Of List “ command type) is shown by register ADCEOLRI. The CSL is used in single buffer mode and bit CSL_SEL is forced to 1’b0. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 367: List Usage — Csl Double Buffer Mode And Rvl Double Buffer Mode
Command Sequence List is reached, if bits LDOK and RSTA are set, the commands list is swapped. CSL_0 RVL_0 RVL_1 CSL_1 (unused) Figure 9-38. CSL Double Buffer Mode — RVL Single Buffer Mode Diagram MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 368: List Usage — Csl Double Buffer Mode And Rvl Double Buffer Mode
Hence application software can pick up conversion results, or groups of results, or an entire result list driven fully by interrupts. A use case example diagram is shown in Figure 9-40. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 369 One of the CON_IF interrupt ﬂags occurs Delay can vary depending on the DMA performance, and ADC conﬁguration (conversion delay ﬂow using the Trigger to proceed through the CSL) Figure 9-40. RVL Swapping — Use Case Diagram MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 370: Conversion Flow Control Application Information
After the Restart Event is ﬁnished (bit RSTA is cleared), the ADC accepts a new Trigger Event (bit TRIG can be set) and begins conversion from the top of the currently active CSL. In conversion ﬂow control MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 371 If only a Restart Event occurs while ADC is not idle and bit SEQA is not set already (Sequence Abort Event in progress) a Sequence Abort Event is issued automatically and bit RSTAR_EIF is set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 372: Continuous Conversion
AN3 AN1 AN4 IN5 AN3 AN1 AN4 IN5 AN3 AN1 AN3 AN1 AN4 Stop Mode entry Abort Active CSL_0 Idle Idle Active Figure 9-41. Conversion Flow Control Diagram — Continuous Conversion (with Stop Mode) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 373: Triggered Conversion — Single Csl
If bit AUT_RSTA is set before Low Power Mode is entered, the conversion continues automatically as soon as a low power mode (Stop Mode or Wait Mode with bit SWAI set) is exited. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 374: Fully Timing Controlled Conversion
Timing Controlled Conversion) can be used with CSL single buffer mode or with CSL double buffer mode. If using CSL double buffer mode, CSL swapping is performed by issuing a Restart Event with bit LDOK set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 375: Introduction
During stop mode operation the path from the VSUP pin through the resistor chain to ground is opened and the low and high voltage sense features are disabled. The content of the conﬁguration register is unchanged. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 376: Block Diagram
This pin is the chip supply. It can be internally connected for voltage measurement. The voltage present at this input is scaled down by an internal voltage divider, and can be routed to the internal ADC or to a comparator. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 377: Memory Map And Register Deﬁnition
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register diagrams, in bit order. Unused bits read back zero. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 378 + two bus cycles the measured value is invalid. EN_UNC This is to let internal nodes be charged to correct value. BVHIE, BVLIE might be cleared for this time period to avoid false interrupts. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 379 (falling edge) or V (rising edge) measured LBI_A measured LBI_D < V < V (falling edge) or V (rising edge) measured LBI_A measured LBI_D Figure 10-5. BATS Voltage Sensing HBI_A HBI_D LBI_D LBI_A MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 380 BATS Interrupt Flag Register (BATIF) 10.3.2.4 Module Base + 0x0003 Access: User read/write BVHIF BVLIF Reset = Unimplemented Figure 10-7. BATS Interrupt Flag Register (BATIF) 1. Read: Anytime Write: Anytime, write 1 to clear MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 381: Functional Description
Entering and exiting CPU stop mode has no effect on the interrupt ﬂags. To make sure the interrupt generation works properly the bus clock frequency must be higher than the Voltage Warning Low Pass Filter frequency (f VWLP_ﬁlter MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 382 ﬂag BVLIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVLIE the module requests an interrupt to MCU (BATI). 10.4.2.2 BATS Voltage High Condition Interrupt (BVHI) To use the Voltage High Interrupt the Level Sensing must be enabled (BSUSE=1). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 383 Interrupt ﬂag (BVHIF) is set to 1 when a Voltage High Condition (BVHC) changes state. The Interrupt ﬂag BVHIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVHIE the module requests an interrupt to MCU (BATI). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 384 Chapter 10 Supply Voltage Sensor - (BATSV3) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 385: Introduction
Timer counter keeps on running, unless TSFRZ in TSCR1 is set to 1. Wait: Counters keeps on running, unless TSWAI in TSCR1 is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR1 is cleared to 0. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 386: Block Diagrams
Set CnF Interrupt TCn Input Capture Reg. Figure 11-2. Interrupt Flag Setting 11.2 External Signal Description The TIM16B4CV3 module has a selected number of external pins. Refer to device speciﬁcation for exact number. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 387: Ioc3 - Ioc0 — Input Capture And Output Compare Channel 3-0
0x0009 TCTL2 0x000A R RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE TCTL3 0x000B EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A TCTL4 Figure 11-3. TIM16B4CV3 Register Summary (Sheet 1 of 2) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 388 11.3.2.1 Timer Input Capture/Output Compare Select (TIOS) Module Base + 0x0000 RESERVED RESERVED RESERVED RESERVED IOS3 IOS2 IOS1 IOS0 Reset Figure 11-4. Timer Input Capture/Output Compare Select (TIOS) Read: Anytime Write: Anytime MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 389 ﬂag won’t get set. 11.3.2.3 Timer Count Register (TCNT) Module Base + 0x0004 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 Reset Figure 11-6. Timer Count Register High (TCNTH) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 390 0 Allows the timer module to continue running during wait. 1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. TSWAI also affects pulse accumulator. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 391 TOV[3:0] in output compare mode. When set, it takes precedence over forced output compare 0 Toggle output compare pin on overﬂow feature disabled. 1 Toggle output compare pin on overﬂow feature enabled. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 392 Table 11-7. Compare Result Output Action Action No output compare action on the timer output signal Toggle OCx output line Clear OCx output line to zero Set OCx output line to one MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 393 Input Capture Edge Control — These four pairs of control bits conﬁgure the input capture edge detector EDGnB circuits. EDGnA Table 11-9. Edge Detector Circuit Conﬁguration EDGnB EDGnA Conﬁguration Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge (rising or falling) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 394 1 Hardware interrupt requested when TOF ﬂag set. Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the PR[2:0] Bus Clock as shown in Table 11-12. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 395 Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel (0x0010–0x001F) will cause the corresponding channel ﬂag CxF to be cleared. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 396 Timer Overﬂow Flag — Set when 16-bit free-running timer overﬂows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 is set to one (See also TCRE control bit explanation.) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 397 All timer input capture/output compare registers are reset to 0x0000. NOTE Read/Write access in byte mode for high byte should take place before low byte otherwise it will give a different result. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 398 11.3.2.14 Precision Timer Prescaler Select Register (PTPSR) Module Base + 0x002E PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Reset Figure 11-21. Precision Timer Prescaler Select Register (PTPSR) Read: Anytime Write: Anytime All bits reset to zero. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 399: Functional Description
PTPS2 PTPS1 PTPS0 Factor 11.4 Functional Description This section provides a complete functional description of the timer TIM16B4CV3 block. Please refer to the detailed timer block diagram in Figure 11-22 as necessary. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 400: Prescaler
2 (TSCR2) are set to deﬁne a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the PRNT bit in TSCR1 is disabled. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 401: Input Capture
OCPDx and TEN bits set to one. Set OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=1 and OCPDx=1 Clear OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=0 and OCPDx=1 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 402: Resets
Timer Overﬂow Interrupt (TOF) This active high output will be asserted by the module to request a timer overﬂow interrupt. The TIM block only generates the interrupt and does not service it. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 403: Introduction
EMI environment of a vehicle, cost-effectiveness, and required bandwidth. MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simpliﬁed application software. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 404: Glossary
Receive/ Transmit Engine TXCAN Transmit Interrupt Req. Message Receive Interrupt Req. Control Filtering Errors Interrupt Req. Status Buffering Wake-Up Interrupt Req. Conﬁguration Registers Wake-Up Low Pass Filter Figure 12-1. MSCAN Block Diagram MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 405: Features
For a description of the speciﬁc MSCAN modes and the module operation related to the system operating modes refer to Section 12.4.4, “Modes of Operation”. 1. Depending on the actual bit timing and the clock jitter of the PLL. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 406: External Signal Description
CAN bus and has current protection against defective CAN or defective stations. CAN node 2 CAN node n CAN node 1 CAN Controller (MSCAN) TXCAN RXCAN Transceiver CANH CANL CAN Bus Figure 12-2. CAN System MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 407: Memory Map And Register Deﬁnition
MCU level when the MCU is deﬁned. The register decode map is ﬁxed and begins at the ﬁrst address of the module address offset. The detailed register descriptions follow in the order they appear in the register map. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 408 0x000B IDHIT2 IDHIT1 IDHIT0 IDAM1 IDAM0 CANIDAC 0x000C Reserved 0x000D BOHOLD CANMISC 0x000E R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 CANRXERR = Unimplemented or Reserved Figure 12-3. MSCAN Register Summary MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 409: Register Descriptions
The CANCTL0 register provides various control bits of the MSCAN module as described below. Module Base + 0x0000 Access: User read/write RXACT SYNCH RXFRM CSWAI TIME WUPE SLPRQ INITRQ Reset: = Unimplemented Figure 12-4. MSCAN Control Register 0 (CANCTL0) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 410 0 Wake-up disabled — The MSCAN ignores trafﬁc on CAN 1 Wake-up enabled — The MSCAN is able to restart MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 411 9. RSTAT1 and RSTAT0 are not affected by initialization mode. 12.3.2.2 MSCAN Control Register 1 (CANCTL1) The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 412 0 MSCAN wakes up on any dominant level on the CAN bus 1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of T MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 413 Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing BRP[5:0] (see Table 12-6). Table 12-5. Synchronization Jump Width SJW1 SJW0 Synchronization Jump Width 1 Tq clock cycle 2 Tq clock cycles 3 Tq clock cycles 4 Tq clock cycles MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 414 (see Figure 12-44). Time segment 1 (TSEG1) values are programmable as shown in Table 12-9. 1. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 415 A ﬂag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. Every ﬂag has an associated interrupt enable bit in the CANRIER register. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 416 96 ≤ receive error counter < 128 01 RxWRN: 128 ≤ receive error counter 10 RxERR: : 256 ≤ transmit error counter 11 Bus-off 1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 417 The CANRIER register is held in the reset state when the initialization mode is active (INITRQ=1 and INITAK=1). This register is writable when not in initialization mode (INITRQ=0 and INITAK=0). The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization mode. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 418 RXSTAT[1:0] ﬂags deﬁne an additional bus-off state for the receiver (see Section 12.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). 12.3.2.7 MSCAN Transmitter Flag Register (CANTFLG) The transmit buffer empty ﬂags each have an associated interrupt enable bit in the CANTIER register. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 419 0 The associated message buffer is full (loaded with a message due for transmission) 1 The associated message buffer is empty (not scheduled) 12.3.2.8 MSCAN Transmitter Interrupt Enable Register (CANTIER) This register contains the interrupt enable bits for the transmit buffer empty interrupt ﬂags. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 420 The CANTARQ register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 421 1 The message was aborted. 12.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL) The CANTBSEL register allows the selection of the actual transmit message buffer, which then will be accessible in the CANTXFG register space. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 422 If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers. 12.3.2.12 MSCAN Identiﬁer Acceptance Control Register (CANIDAC) The CANIDAC register is used for identiﬁer acceptance control as described below. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 423 The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 424 This register provides additional features. Module Base + 0x000D Access: User read/write BOHOLD Reset: = Unimplemented Figure 12-17. MSCAN Miscellaneous Register (CANMISC) 1. Read: Anytime Write: Anytime; write of ‘1’ clears ﬂag; write of ‘0’ ignored MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 425 Reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 426 Module Base + 0x0010 to Module Base + 0x0013 Access: User read/write Reset Figure 12-20. MSCAN Identiﬁer Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 427 CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.” Module Base + 0x0014 to Module Base + 0x0017 Access: User read/write Reset Figure 12-22. MSCAN Identiﬁer Mask Registers (First Bank) — CANIDMR0–CANIDMR3 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 428: Programmer's Model Of Message Storage
This feature is only available for transmit and receiver buffers, if the TIME bit is set (see Section 12.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 429 All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation All reserved or unused bits of the receive and transmit buffers always read ‘x’. 1. Exception: The transmit buffer priority registers are 0 out of reset. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 430 ID15 IDR1 0x00X2 ID14 ID13 ID12 ID11 ID10 IDR2 0x00X3 IDR3 0x00X4 DSR0 0x00X5 DSR1 0x00X6 DSR2 0x00X7 DSR3 0x00X8 DSR4 0x00X9 DSR5 0x00XA DSR6 0x00XB DSR7 0x00XC DLC3 DLC2 DLC1 DLC0 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 431 The identiﬁer registers for an extended format identiﬁer consist of a total of 32 bits: ID[28:0], SRR, IDE, and RTR. The identiﬁer registers for a standard format identiﬁer consist of a total of 13 bits: ID[10:0], RTR, and IDE. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 432 Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the ID[17:15] most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an identiﬁer is deﬁned to be highest for the smallest binary number. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 433 In the case of a transmit buffer, this ﬂag deﬁnes the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 434 ﬂag is set as received and indicates to the CPU how to process the buffer identiﬁer registers. In the case of a transmit buffer, the ﬂag indicates to the MSCAN what type of identiﬁer to send. 0 Standard format (11 bit) 1 Extended format (29 bit) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 435 Module Base + 0x00X4 to Module Base + 0x00XB Reset: Figure 12-34. Data Segment Registers (DSR0–DSR7) — Extended Identiﬁer Mapping Table 12-32. DSR0–DSR7 Register Field Descriptions Field Description Data bits 7-0 DB[7:0] MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 436 MSCAN and is deﬁned to be highest for the smallest binary number. The MSCAN implements the following internal prioritization mechanisms: • All transmission buffers with a cleared TXEx ﬂag participate in the prioritization immediately before the SOF (start of frame) is sent. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 437 Section 12.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers: Anytime when RXF is set. Write: Unimplemented MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 438 Section 12.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers: Anytime when RXF is set. Write: Unimplemented MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 439: Functional Description
Message Storage CAN Receive / Transmit Engine Memory Mapped I/O MSCAN CPU bus Receiver TXE0 PRIO TXE1 CPU bus MSCAN PRIO TXE2 Transmitter PRIO Figure 12-39. User Model for Message Buffer Organization MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 440 (CANTBSEL)”). This makes the respective buffer accessible within the CANTXFG address space (see Section 12.3.3, “Programmer’s Model of Message Storage”). The algorithmic feature associated with the CANTBSEL register simpliﬁes the transmit buffer selection. In addition, this scheme makes the handler MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 441 MSCAN shifts the content of RxBG into the receiver FIFO, sets the RXF ﬂag, and 1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 442: Identiﬁer Acceptance Filter
Although this mode can be used for standard identiﬁers, it is recommended to use the four or eight identiﬁer acceptance ﬁlters. 1. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 443 IDR3 CAN 2.0A/B ID10 IDR0 IDR1 ID10 IDR2 ID10 IDR3 Standard Identiﬁer CANIDMR0 CANIDMR1 CANIDMR2 CANIDMR3 CANIDAR0 CANIDAR1 CANIDAR2 CANIDAR3 ID Accepted (Filter 0 Hit) Figure 12-40. 32-bit Maskable Identiﬁer Acceptance Filter MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 444 IDR1 ID10 IDR2 ID10 IDR3 Standard Identiﬁer CANIDMR0 CANIDMR1 CANIDAR0 CANIDAR1 ID Accepted (Filter 0 Hit) CANIDMR2 CANIDMR3 CANIDAR2 CANIDAR3 ID Accepted (Filter 1 Hit) Figure 12-41. 16-bit Maskable Identiﬁer Acceptance Filters MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 445 ID Accepted (Filter 0 Hit) CIDMR1 CIDAR1 ID Accepted (Filter 1 Hit) CIDMR2 CIDAR2 ID Accepted (Filter 2 Hit) CIDMR3 CIDAR3 ID Accepted (Filter 3 Hit) Figure 12-42. 8-bit Maskable Identiﬁer Acceptance Filters MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 446 If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 447 (PROP_SEG + PHASE_SEG1) (PHASE_SEG2) 4 ... 16 2 ... 8 8 ... 25 Time Quanta = 1 Bit Time Transmit Point Sample Point (single or triple sampling) Figure 12-44. Segments within the Bit Time MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 448: Modes Of Operation
0 .. 3 12.4.4 Modes of Operation 12.4.4.1 Normal System Operating Modes The MSCAN module behaves as described within this speciﬁcation in all normal system operating modes. Write restrictions exist for some registers. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 449 CANTAAK, and CANTBSEL registers to their default values. In addition, the MSCAN enables the conﬁguration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR, CANIDMR message ﬁlters. See Section 12.3.2.1, “MSCAN Control Register 0 (CANCTL0),” for a detailed description of the initialization mode. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 450: Low-Power Options
Table 12-37 summarizes the combinations of MSCAN and CPU modes. A particular combination of modes is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 451 This is a non-power-saving mode. Enabling the MSCAN puts the module from disabled mode into normal mode. In this mode the module can either be in initialization mode or out of initialization mode. See Section 12.4.4.5, “MSCAN Initialization Mode”. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 452 RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO (RxFG) does not take place while in sleep mode. It is possible to access the transmit buffers and to clear the associated TXE ﬂags. No message abort takes place while in sleep mode. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 453 In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. This causes some ﬁxed delay before the module enters normal mode again. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 454: Reset Initialization
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXEx ﬂag of the empty message buffer is set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 455 For this reason, bit manipulation instructions (BSET) must not be used to clear interrupt ﬂags. These instructions may cause accidental clearing of interrupt ﬂags which are set after entering the current interrupt service routine. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 456: Initialization/Application Information
128 occurrences of 11 consecutive recessive bits on the CAN bus have been monitored • BOHOLD in MSCAN Miscellaneous Register (CANMISC) has been cleared by the user These two events may occur in any order. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 457: Introduction
One 16 bit counter as time base for all trigger events • Two independent trigger generators (TG0 and TG1) • Up to 32 trigger events per trigger generator • Global Load OK support, to guarantee coherent update of all control loop modules MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 458: Modes Of Operation
Depends on the PTUFRZ register bit setting the internal counter is stopped and no trigger events will be generated. 4. Stop mode The PTU is disabled and the internal counter is stopped; no trigger events will be generated. The content of the conﬁguration register is unchanged. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 459: Block Diagram
PTUT0 — PTU Trigger 0 If enabled (PTUT0PE is set) this pin shows the internal trigger_0 event. 13.2.2 PTUT1 — PTU Trigger 1 If enabled (PTUT1PE is set) this pin shows the internal trigger_1 event. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 460: Pture — Ptue Reload Event
TG0DIE PTUIEL 0x0004 PTUDEEF PTUROIF PTUIFH 0x0005 TG1AEIF TG1REIF TG1TEIF TG1DIF TG0AEIF TG0REIF TG0TEIF TG0DIF PTUIFL 0x0006 TG0LIST TG0LIST 0x0007 TG0TNUM[4:0] TG0TNUM 0x0008 TG0TV[15:8] TG0TVH = Unimplemented Figure 13-2. PTU Register Summary MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 461 PTUCNT[7:0] PTUCNTL 0x0010 Reserved 0x0011 PTUPTR[23:16] PTUPTRH 0x0012 PTUPTR[15:8] PTUPTRM 0x0013 PTUPTR[7:1] PTUPTRL 0x0014 TG0L10DX[6:0] TG0L0IDX 0x0015 TG0L1IDX[6:0] TG0L1IDX 0x0016 TG1L0IDX[6:0] TG1L0IDX 0x0017 TG1L1IDX[6:0] TG1L1IDX = Unimplemented Figure 13-2. PTU Register Summary MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 462: Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register diagrams, in bit order. Unused bits read back zero. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 463 Module Base + 0x0001 Access: User read/write PTULDOK Reset = Unimplemented Figure 13-4. PTU Module Control Register (PTUC) 1. Read: Anytime Write: write 1 anytime, write 0 if TG0EN and TG1EN is cleared MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 464 At the next reload event this bit is cleared by control logic. Write 0 is only possible if TG0EN and TG1EN is cleared. The PTULDOK can be used by other module as global load OK (glb_ldok). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 465 Trigger Generator 1 Reload Error Interrupt Enable — Enables trigger generator reload error interrupt. TG1REIE 0 No interrupt will be requested whenever TG1REIF is set 1 Interrupt will be requested whenever TG1REIF is set MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 466 Trigger Generator 0 Done Interrupt Enable — Enables trigger generator done interrupt. TG0DIE 0 No interrupt will be requested whenever TG0DIF is set 1 Interrupt will be requested whenever TG0DIF is set MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 467 Module Base + 0x0005 Access: User read/write TG1AEIF TG1REIF TG1EIF TG1DIF TG0AEIF TG0REIF TG0EIF TG0DIF Reset = Unimplemented Figure 13-8. PTU Interrupt Flag Register Low (PTUIFL) 1. Read: Anytime Write: Anytime, write 1 to clear MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 468 Trigger Generator 0 Done Interrupt Flag —This bit is set if the trigger generator receives the end of list symbol TG0DIF or the maximum number of generated trigger events was reached. 0 Trigger generator 0 is running 1 Trigger generator 0 is done MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 469 Trigger Generator 0 Trigger Number — This register shows the number of generated triggers since the last TG0TNUM[4:0] reload event. After the generation of 32 triggers this register shows zero. The next reload event clears this register. See also Figure 13-22. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 470 Trigger Generator 1 List Register (TG1LIST) 13.3.2.10 Module Base + 0x000A Access: User read/write TG1LIST Reset = Unimplemented Figure 13-12. Trigger Generator 1 List Register (TG1LIST) 1. Read: Anytime Write: Anytime, if TG1EN bit is cleared MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 471 Trigger Generator 1 List — This bit shows the number of the current used list. TG1LIST 0 Trigger generator 1 is using list 0 1 Trigger generator 1 is using list 1 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 472 Access: User read only TG1TV[15:8] Reset Module Base + 0x000D Access: User read only TG1TV[7:0] Reset = Unimplemented Figure 13-14. Trigger Generator 1 Trigger Value Register (TG1TVH, TG1TVL) 1. Read: Anytime Write: Never MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 473 (EOL) symbol then this value is visible inside this register. If the last generated trigger was trigger number 32 then the last used trigger value is visible inside this register. See also Figure 13- MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 474 PTUCNT[15:0] PTU Time Base Counter value — This register contains the current status of the internal time base counter. If both TG are done with the execution of the trigger list then the counter also stops. The counter is restarted by the next reload event. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 475 PTU Pointer — This register cannot be modiﬁed if TG0EN or TG1EN bit is set. This register deﬁnes the start [23:0] address of the used list area inside the global memory map. For more information see Section 13.4.2, “Memory based trigger event list”. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 476 Trigger Generator 0 List 1 Index Register — This register cannot be modiﬁed after the TG0EN bit is set. This TG0L1IDX register deﬁnes offset of the start point for the trigger event list 1 used by trigger generator 0. For more [6:0] information see Section 13.4.2, “Memory based trigger event list”. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 477 Trigger Generator 1 List 1 Index Register — This register cannot be modiﬁed after the TG1EN bit is set. This TG1L1IDX register deﬁnes offset of the start point for the trigger event list 1 used by trigger generator 1. For more [6:0] information see Section 13.4.2, “Memory based trigger event list”. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 478: Functional Description
The PTU module consists of two trigger generators (TG0 and TG1). For each TG a separate enable bit is available, so that both TGs can be enabled independently. If both trigger generators are disabled then the PTU is disabled, the trigger generation stops and the memory accesses are disabled. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 479 ﬂag will be visible. During this time the PTU loads the next trigger value from the memory to evaluate the EOL symbol. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 480: Memory Based Trigger Event List
Delay T0 Delay T1 0x0000 (EOL symbol) unused PTUPTR + TG1L1IDX start address TG1 trigger event list 1 Delay T0 Delay T1 0x0000 (EOL symbol) max accessible unused memory area: 256 byte MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 481: Reload Mechanism
If the reload and reload_is_async are active at the same time then an async reload event happens. The PTU behavior on an async reload event is the same like on the reload event described in Section 13.4.3, “Reload MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 482: Interrupts And Error Handling
The trigger generator reload error ﬂag (TGxREIF) is set if a new reload event occurs before the trigger generator reaches the EOL symbol or the maximum number of generated triggers. Independent from this MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 483: Debugging
To generate a reload event or trigger event independent from the PWM status the debug register bits PTUFRE or TGxFTE can be used. A write one to this bits will generate the associated event. This behavior is not available during stop or freeze mode. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 484 Chapter 13 Programmable Trigger Unit (PTUV2) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 485: Chapter 14
PWM logic level low causing external power device not to conduct or disabled state Inverted output Negative polarity PWM clock Clock supplied to PWM and deadtime generators. Based on core clock. Rate depends on prescaler setting. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 486: Introduction
Edge-aligned or center-aligned mode • Features of complementary channel operation: — Deadtime insertion — Separate top and bottom pulse width correction via current status inputs or software — Three variants of PWM output: MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 487: Modes Of Operation
Table 14-3. Modes When PWM Operation is Restricted Mode Description STOP PWM outputs are disabled WAIT PWM outputs are disabled as a function of the PMFWAI bit FREEZE PWM outputs are disabled as a function of the PMFFRZ bit MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 488: Block Diagram
RELOAD C INTERRUPT REQUEST FIF2 QSMP2 FIE0-5 INTERRUPT FAULT0-5 INTERRUPT REQUEST CONTROL FIF3 QSMP3 FIF0-5 FIF4 QSMP4 PMFROIE FIF5 QSMP5 PMFROIF RELOAD OVERRUN A or B or C INTERRUPT REQUEST Figure 14-1. PMF Block Diagram MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 489: Signal Descriptions
(preferably timer output compare channel) at integration level. The commutation event input must be enabled to take effect (ENCE=1). When this bit is set the PMFOUTC, PMFOUT, and MSKx registers switch from non-buffered to async_event triggered double MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 490: Commutation Event Edge Select Signal — Async_Event_Edge_Sel[1:0]
Whenever the async_event signal causes pmf_reloada output to assert also the pmf_reload_is_async output asserts for the same duration, except if asynchronous event and generated PWM reload event occur in the same cycle. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 491: Memory Map And Registers
FIF3 FIF2 FIF1 FIF0 0x0008 PMFQSMP0 QSMP5 QSMP4 0x0009 PMFQSMP1 QSMP3 QSMP2 QSMP1 QSMP0 0x000A- Reserved 0x000B = Unimplemented or Reserved Figure 14-2. Quick Reference to PMF Registers (Sheet 1 of 5) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 492 PMFVAL2 PMFVAL2 0x0016 PMFVAL3 PMFVAL3 0x0017 PMFVAL3 PMFVAL3 0x0018 PMFVAL4 PMFVAL4 0x0019 PMFVAL4 PMFVAL4 0x001A PMFVAL5 PMFVAL5 = Unimplemented or Reserved Figure 14-2. Quick Reference to PMF Registers (Sheet 2 of 5) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 493 PMFDTMA 0x0027 PMFDTMA PMFDTMA 0x0028 PMFENCB PWMENB GLDOKB RSTRTB LDOKB PWMRIEB 0x0029 PMFFQCB LDFQB HALFB PRSCB PWMRFB = Unimplemented or Reserved Figure 14-2. Quick Reference to PMF Registers (Sheet 3 of 5) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 494 PMFDTMB 0x002F PMFDTMB PMFDTMB 0x0030 PMFENCC PWMENC GLDOKC RSTRTC LDOKC PWMRIEC 0x0031 PMFFQCC LDFQC HALFC PRSCC PWMRFC = Unimplemented or Reserved Figure 14-2. Quick Reference to PMF Registers (Sheet 4 of 5) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 495 PMFDMP5 DMP55 DMP54 DMP53 DMP52 DMP51 DMP50 0x003E PMFOUTF OUTF5 OUTF4 OUTF3 OUTF2 OUTF1 OUTF0 0x003F Reserved = Unimplemented or Reserved Figure 14-2. Quick Reference to PMF Registers (Sheet 5 of 5) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 496: Register Descriptions
PWMs or complementary PWMs. This bit cannot be modiﬁed after the WP bit is set. 0 PWM4 and PWM5 are complementary PWM pair 1 PWM4 and PWM5 are independent PWMs MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 497 Pair C Bottom-Side PWM Polarity — This bit determines the polarity for Pair C bottom-side PWM (PWM5). This BOTNEGC bit cannot be modiﬁed after the WP bit is set. 0 Positive PWM5 polarity 1 Negative PWM5 polarity MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 498 These bits select if timebase generator A, B or C provides the reload event on output signal pmf_reloada. 00 Reload event generation disabled 01 PWM generator A generates reload event 10 PWM generator B generates reload event 11 PWM generator C generates reload event MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 499 PWM registers. This bit cannot be modiﬁed after the WP bit is set. 0 PMF continues to run in FREEZE mode 1 PMF is disabled in FREEZE mode MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 500 This register cannot be modiﬁed after the WP bit is set. 0 FAULTm input is disabled 1 FAULTm input is enabled for fault protection m is 0, 1, 2, 3, 4 and 5 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 501 PWM outputs are disabled or switched to output control according to the PMF Disable Mapping registers. 0 FAULTm CPU interrupt requests disabled 1 FAULTm CPU interrupt requests enabled m is 0, 1, 2, 3, 4 and 5. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 502 Address: Module Base + 0x0009 Access: User read/write QSMP3 QSMP2 QSMP1 QSMP0 Reset Figure 14-12. PMF Fault Qualifying Samples Register (PMFQSMP1) 1. Read: Anytime Write: This register cannot be modiﬁed after the WP bit is set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 503 That is OUTCTL0 and OUTCTL1 must have the same value; OUTCTL2 and OUTCTL3 must have the same value; and OUTCTL4 and OUTCTL5 must have the same value. 0 Software control disabled 1 Software control enabled n is 0, 1, 2, 3, 4 and 5. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 504 0 — PWM5 is inactive 0 — PWM5 is inactive 14.3.2.12 PMF Deadtime Sample Register (PMFDTMS) Address: Module Base + 0x000E Access: User read/write Reset Figure 14-15. PMF Deadtime Sample Register (PMFDTMS) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 505 Current Polarity — This buffered bit selects the PMF Value register for PWM0 and PWM1 in top/bottom software IPOLA correction in complementary mode. 0 PMF Value 0 register in next PWM cycle 1 PMF Value 1 register in next PWM cycle MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 506 Module Base + 0x0014 PMFVAL2 Module Base + 0x0016 PMFVAL3 Module Base + 0x0018 PMFVAL4 Module Base + 0x001A PMFVAL5 PMFVALn Reset Figure 14-17. PMF Value n Register (PMFVALn) 1. Read: Anytime Write: Anytime MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 507 14.3.2.16 PMF Interrupt Flag Register (PMFROIF) Address: Module Base + 0x001D Access: User read/write PMFROIFC PMFROIFB PMFROIFA Reset Figure 14-19. PMF Interrupt Flag Register (PMFROIF) 1. Read: Anytime Write: Anytime. Write 1 to clear MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 508 PECx bits overrides the ICCx settings. This allows the PWM pulses generated by both the odd and even PWM value registers to be ANDed together prior to the complementary logic and deadtime insertion. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 509 14.3.2.18 PMF Compare Invert Register (PMFCINV) Address: Module Base + 0x001F Access: User read/write CINV5 CINV4 CINV3 CINV2 CINV1 CINV0 Reset Figure 14-22. PMF Compare Invert Register (PMFCINV) 1. Read: Anytime Write: Anytime MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 510 GLDOKA RSTRTA LDOKA PWMRIEA Reset Figure 14-24. PMF Enable Control A Register (PMFENCA) 1. Read: Anytime Write: Anytime except GLDOKA and RSTRTA which cannot be modiﬁed after the WP bit is set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 511 14.3.2.20 PMF Frequency Control A Register (PMFFQCA) Address: Module Base + 0x0021 Access: User read/write LDFQA HALFA PRSCA PWMRFA Reset Figure 14-25. PMF Frequency Control A Register (PMFFQCA) 1. Read: Anytime Write: Anytime MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 512 Every 15 PWM opportunities 0111 Every 8 PWM opportunities 1111 Every 16 PWM opportunities Table 14-27. PWM Prescaler A PRSCA[1:0] Prescaler Value P PWM Clock Frequency f PWM_A core core core core MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 513 The 12-bit value written to this register is the number of PWM clock cycles in complementary channel operation. A reset sets the PWM deadtime register to the maximum value of 0x0FFF, selecting a deadtime MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 514 PWM Reload Interrupt Enable B — If MTG is clear, this bit reads zero and cannot be written. PWMRIEB If MTG is set, this bit enables the PWMRFB ﬂag to generate CPU interrupt requests. 0 PWMRFB CPU interrupt requests disabled 1 PWMRFB CPU interrupt requests enabled MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 515 Every 12 PWM opportunities 0100 Every 5 PWM opportunities 1100 Every 13 PWM opportunities 0101 Every 6 PWM opportunities 1101 Every 14 PWM opportunities 0110 Every 7 PWM opportunities 1110 Every 15 PWM opportunities MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 516 LDOKB bit or global load OK is set and the next PWM load cycle begins. Reading PMFMODB returns the value in the buffer. It is not necessarily the value the PWM generator B is currently using. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 517 This bit cannot be modiﬁed after the WP bit is set. 0 No PWM generator C restart at the next commutation event 1 PWM generator C restart at the next commutation event MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 518 Note: Reading the PRSCC ﬁeld reads the buffered value and not necessarily the value currently in effect. The PRSCC ﬁeld takes effect at the beginning of the next PWM cycle and only when the LDOKC bit or global load OK is set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 519 Access: User read/write PMFCNTC Reset Figure 14-36. PMF Counter C Register (PMFCNTC) 1. Read: Anytime. Returns zero if MTG is clear. Write: Never This register displays the state of the 15-bit PWM C counter. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 520 4095 PWM clock cycles. Deadtime is affected by changes to the prescaler value. The deadtime duration is determined as follows: = PMFDTMC × P × T = PMFDTMC / f Eqn. 14-3 DEAD_C PWM_C core MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 521 0 event. Disabling PWMn has priority over forcing PWMn to OUTFn. This bit cannot be modiﬁed after the WP bit is set. FAULT3-0 have priority over FAULT5-4. 0 PWMn unaffected by FAULT3-0 event 1 PWMn disabled on FAULT3-0 event n is 0, 1, 2, 3, 4 and 5. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 522 0 — PWM4 is inactive 0 — PWM4 is inactive OUTF5 1 — PWM5 is complement of PWM4 1 — PWM5 is active 0 — PWM5 is inactive 0 — PWM5 is inactive MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 523: Functional Description
Section 14.3.2.2, “PMF Conﬁgure 1 Register (PMFCFG1)” for the description of TOPNEG and BOTNEG bits, and Section 14.3.2.3, “PMF Conﬁgure 2 Register (PMFCFG2)” for the description of the MSK0 and MSK1 bits. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 524: Prescaler
PWM counter, and PWM counter is counting upwards if the corresponding channel CINVn=0. Or, the PWM compare output is driven to high state if the corresponding channel CINVn=1. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 525 PWM period = (PWM modulus) × (PWM clock period) × 2 Eqn. 14-4 COUNTER UP/DOWN COUNTERER MODULUS = 4 PWM CLOCK PERIOD PWM PERIOD = 8 x PWM CLOCK PERIOD Figure 14-44. Center-Aligned PWM Period MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 526 A PWM value less than or equal to zero deactivates the PWM output for the entire PWM period. A PWM value greater than or equal to the modulus activates the PWM output for the entire PWM period when CINVn=0, and vice versa if CINVn=1. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 527 PWM VALUE = 4 4/4 = 100% Figure 14-46. Center-Aligned PWM Pulse Width Edge-aligned operation is illustrated in Figure 14-47. PWM pulse width = (PWM value) × (PWM clock period) Eqn. 14-7 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 528: Independent Or Complementary Channel Operation
PWM CHANNELS 0 AND 1 BOTTOM PMFVAL2 PMFVAL3 REGISTER REGISTER PAIR B PWM CHANNELS 2 AND 3 BOTTOM PMFVAL4 PMFVAL5 REGISTER REGISTER PAIR C PWM CHANNELS 4 AND 5 BOTTOM Figure 14-48. Complementary Channel Pairs MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 529: Deadtime Generators
Every time the deadtime generator inputs changes state, deadtime is inserted. Deadtime forces both PWM outputs in the pair to the inactive state. A method of correcting this, adding to or subtracting from the PWM value used, is discussed next. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 530 OUTCTL4 Figure 14-50. Deadtime Generators MODULUS = 4 PWM VALUE = 2 PWM0, NO DEADTIME PWM1, NO DEADTIME PWM0, DEADTIME = 1 PWM1, DEADTIME = 1 Figure 14-51. Deadtime Insertion, Center Alignment MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 531: Top/Bottom Correction
See Figure 14- 54. On AC induction motors running open-loop, the distortion typically manifests itself as poor low-speed performance, such as torque ripple and rough operation. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 532 The direction of PWM counter if ICC bits in the PMFICCTL register are set to ones To correct deadtime distortion, software can decrease or increase the value in the appropriate PMFVAL register. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 533 Table 14-41. Top/Bottom Manual Correction Logic state Output Control IPOLA PMFVAL0 controls PWM0/PWM1 pair PMFVAL1 controls PWM0/PWM1 pair IPOLB PMFVAL2 controls PWM2/PWM3 pair PMFVAL3 controls PWM2/PWM3 pair IPOLC PMFVAL4 controls PWM4/PWM5 pair PMFVAL5 controls PWM4/PWM5 pair MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 534 However, under low-current, the output voltage of the complementary circuit during deadtime is somewhere between the high and low levels. The current cannot free-wheel through the opposition anti- body diode, regardless of polarity, giving additional distortion when the current crosses zero. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 535 Deadtime does not exist at the 100 percent and zero percent duty cycle boundaries. Therefore, the second automatic mode must be used for correction, ISENS = 11, where current status is sampled at the half cycle MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 536 ﬁve initially control the three PWM pairs when conﬁgured for current status correction. DESIRED LOAD VOLTAGE TOP PWM BOTTOM PWM LOAD VOLTAGE Figure 14-60. Correction with Positive Current MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 537: Asymmetric Pwm Output
PWM period. ICCx bits take effect at the end of each PWM cycle regardless of the state of the related LDOKx bit or global load OK. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 538: Variable Edge Placement Pwm Output
In contrast to asymmetric PWM output mode, the PWM phase shift can pass the PWM cycle boundary. CINV0 PECA=1 PINVA GENERATOR 0 to complement logic and dead time CINV1 insertion COMPSRC GENERATOR 1 Figure 14-63. Logic AND Function with Signal Inversions MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 539: Double Switching Pwm Output
(Figure 14-65, Figure 14-66). By setting the non-inverted value register greater or equal to the PWM modulus the output function can be switched to single pulse generation on PWM reload cycle basis. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 540 Figure 14-65. Double-Switching PWM Output VAL0<VAL1 (Center-Aligned) EDGEA=0 PECA=1 Up/Down Counter Modulus = 9 PMFVAL0 = 6; CINV0 =1 PMFVAL1 = 3; CINV1 =0 PWM0 (PINV=0) PWM0 (PINV=1) 100% Figure 14-66. Double-Switching PWM Output VAL0>VAL1 (Center-Aligned) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 541: Output Polarity
NOTE During software output control, TOPNEG and BOTNEG still control output polarity. It will take up to 3 core clock cycles to see the effect of output control on the PWM outputs. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 542 MODULUS = 4 PWM VALUE = 2 DEADTIME = 2 PWM0 PWM1 PWM0 WITH DEADTIME PWM1 WITH DEADTIME OUTCTL0 OUT0 OUT1 PWM0 PWM1 Figure 14-68. Setting OUT0 with OUTCTL Set in Complementary Mode MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 543 MODULUS = 4 PWM VALUE = 2 DEADTIME = 2 PWM0 PWM1 PWM0 WITH DEADTIME PWM1 WITH DEADTIME OUTCTL0 OUT0 OUT1 PWM0 PWM1 Figure 14-70. Setting OUTCTL with OUT0 Set in Complementary Mode MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 544: Pwm Generator Loading
PWM reload event. See Figure 14-72. bus clock LDOK write LDOK bit PWM reload bus clock LDOK write LDOK bit PWM reload Figure 14-71. Setting cleared LDOK bit at PWM reload event MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 545 Half cycle reloads are possible only in center-aligned mode. Enabling or disabling half-cycle reloads in edge-aligned mode will have no effect on the reload rate. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 546 HALF = 0, LDFQ[3:0] = 0000 = RELOAD EVERY CYCLE UP/DOWN COUNTERER LDOK = 1 MODULUS = 3 PWM VALUE = 1 PWMRF = 1 Figure 14-76. Full-Cycle Center-Aligned PWM Value Loading MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 547 Figure 14-78. Half-Cycle Center-Aligned PWM Value Loading HALF = 1, LDFQ[3:0] = 0000 = RELOAD EVERY HALF-CYCLE UP/DOWN COUNTERER LDOK = 1 MODULUS = 2 PWM VALUE = 1 PWMRF = 1 Figure 14-79. Half-Cycle Center-Aligned Modulus Loading MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 548 (PMFROIFx). If the PWM reload overrun interrupt enable bit PMFROIEx is set, the PMFROIFx ﬂag generates a CPU interrupt request allowing software to handle the error condition. WRITE 1 TO PMFROIF RESET PMFROIF CPU INTERRUPT REQUEST PMFROIE PWM RELOAD Figure 14-82. PMFROIF Reload Overrun Interrupt Request MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 549: Fault Protection
1. The active input level may be deﬁned or programmable at SoC level. The default for internally connected resources is active- high. For availability and conﬁgurability of fault inputs on pins refer to the device overview section. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 550 — The ﬁlter detects a logic zero on the fault input at the start of the next PWM half cycle boundary. Figure 14-86. FAULT0 OR FAULT2 PWMS ENABLED PWMS ENABLED PWMS DISABLED FIFm CLEARED Figure 14-84. Manual Fault Recovery (Faults 0 and 2) — QSMP = 00 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 551: Resets
The gated system core clock is the clock source for all PWM generators. The system clock is used as a clock source for any other logic in this module. The system bus clock is used as clock for speciﬁc control registers and ﬂags (LDOKx, PWMRFx, PMFOUTB). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 552: Interrupts
The PWM generator uses the last values loaded if PWMEN is cleared and then set while LDOK equals zero. Initializing the deadtime register, after setting PWMEN or OUTCTLn, can cause an improper deadtime insertion. However, the deadtime can never be shorter than the speciﬁed value. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 553: Bldc 6-Step Commutation
Make sure to set the write protection bit WP in PMFCFG0 after conﬁguring and prior to enabling PWM outputs and fault inputs. 14.8.2 BLDC 6-Step Commutation 14.8.2.1 Unipolar Switching Mode Unipolar switching mode uses registers PMFOUTC and PMFOUTB to perform commutation. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 554 = 0x30; // Branch A<->B, mask C // 0˚ PMFCFG3[PINVC,PINVB,PINVA] = 0x2; // Invert B The commutation sequence is: PMFCFG2[MSK5:MSK0] = 0x03; // Branch C<->B, mask A // 60˚ PMFCFG3[PINVC,PINVB,PINVA] = 0x2; // Invert B MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 555 PWM0 PWMgen Masked PWMgen Masked PWMgen PWM1 PWMgen Masked PWMgen Masked PWMgen PWM2 PWMgen Masked PWMgen Masked PWM3 PWMgen Masked PWMgen Masked PWM4 Masked PWMgen Masked PWMgen PWM5 Masked PWMgen Masked PWMgen MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 556 Chapter 14 Pulse Width Modulator with Fault Protection (PMF15B6CV3) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 557: Introduction
The SCI allows asynchronous serial communications with peripheral devices and other CPUs. 15.1.1 Glossary IR: InfraRed IrDA: Infrared Design Associate IRQ: Interrupt Request LIN: Local Interconnect Network LSB: Least Signiﬁcant Bit MSB: Most Signiﬁcant Bit NRZ: Non-Return-to-Zero RZI: Return-to-Zero-Inverted MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 558: Features
— Parity error — Receive wakeup on active edge — Transmit collision detect supporting LIN — Break Detect supporting LIN • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 559: Modes Of Operation
RXEDG BERR Data Format Control Transmit TDRE Interrupt Transmit Transmit Control 1/16 Generation Baud Rate Generator Infrared Data Out TXD Transmit Shift Register Encoder SCI Data Register Figure 15-1. SCI Block Diagram MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 560: External Signal Description
15-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the SCI module and the address offset for each register. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 561: Register Descriptions
1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero. 2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one. = Unimplemented or Reserved Figure 15-2. SCI Register Summary MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 562 Note: . User should write SCIBD by word access. The updated SCIBD may take effect until next RT clock start, write SCIBDH or SCIBDL separately may cause baud generator load wrong data at that time,if second write later then RT clock. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 563 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 0 Idle character bit count begins after start bit 1 Idle character bit count begins after stop bit MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 564 0 Even parity 1 Odd parity Table 15-4. Loop Functions LOOPS RSRC Function Normal operation Loop mode with transmitter output internally connected to receiver input Single-wire mode with TXD pin connected to receiver input MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 565 If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing a “1” to it. 0 No break signal was received 1 A break signal was received MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 566 1 BERRIF interrupt requests enabled Break Detect Interrupt Enable — BKDIE enables the break detect interrupt ﬂag, BKDIF, to generate interrupt BKDIE requests. 0 BKDIF interrupt requests disabled 1 BKDIF interrupt requests enabled MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 567 Receive input sampling occurs during the 9th time tick of a transmitted bit (refer to Figure 15-19) Receive input sampling occurs during the 13th time tick of a transmitted bit (refer to Figure 15-19) Reserved MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 568 BRK13 is set). Toggling implies clearing the SBK bit before the break character has ﬁnished transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits). 0 No break characters 1 Transmit break characters MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 569 0 Receiver input is either active now or has never become active since the IDLE ﬂag was last cleared 1 Receiver input has become idle Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE ﬂag. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 570 (PT). PF bit is set during the same cycle as the RDRF ﬂag but does not get set in the case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low (SCIDRL). 0 No parity error 1 Parity error MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 571 Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character. 0 No reception in progress 1 Reception in progress MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 572 If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.The same value is transmitted until T8 is rewritten In 8-bit data format, only SCI data register low (SCIDRL) needs to be accessed. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 573 Chapter 15 Serial Communication Interface (S12SCIV6) When transmitting in 9-bit data format and using 8-bit write instructions, write ﬁrst to SCI data register high (SCIDRH), then SCIDRL. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 574: Functional Description
BKDIF Shift Register Break Detect BKDIE SCI Data BKDFE Register LIN Transmit BERRIF Collision SCTXD Detect BERRIE R16XCLK BERRM[1:0] Infrared Transmit Ir_TXD Encoder R32XCLK TNP[1:0] IREN Figure 15-14. Detailed SCI Block Diagram MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 575: Infrared Interface Submodule
LIN software to distinguish a break character from an incoming data stream. As a further addition is supports a collision detection at the bit level as well as cancelling pending transmissions. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 576: Data Format
(SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it. A frame with nine data bits has a total of 11 bits. Table 15-15. Example of 9-Bit Data Formats Start Data Address Parity Stop Bits Bits Bits MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 577: Baud Rate Generation
76,804.9 4800.3 4,800 .006 10417 38,398.8 2399.9 2,400 .003 20833 19,200.3 1200.02 1,200 41667 9599.9 600.0 65535 6103.6 381.5 1. 16x faster then baud rate 2. divide 1/16 form transmit baud generator MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 578: Transmitter
TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 579 If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE ﬂag generates a transmitter interrupt request. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 580 Does not clear the SCI data registers (SCIDRH/L) • May set noise ﬂag NF, or receiver active ﬂag RAF. 1. A Break character in this context are either 10 or 11 consecutive zero received bits MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 581 TDRE ﬂag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 582 If the bit error detect feature is disabled, the bit error interrupt ﬂag is cleared. NOTE The RXPOL and TXPOL bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt ﬂag may be set incorrectly. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 583: Receiver
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full ﬂag, RDRF, in SCI status register 1 (SCISR1) becomes set, MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 584 Table 15-17. Start Bit Veriﬁcation RT3, RT5, and RT7 Samples Start Bit Veriﬁcation Noise Flag If start bit veriﬁcation is not successful, the RT clock is reset and a new search for a start bit begins. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 585 To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 15-19 summarizes the results of the stop bit samples. Table 15-19. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 586 RT8, RT9, and RT10 are within the bit time and data recovery is successful. Perceived Start Bit Actual Start Bit Samples RT Clock RT Clock Count Reset RT Clock Figure 15-23. Start Bit Search Example 2 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 587 ﬂag. Perceived and Actual Start Bit Samples RT Clock RT Clock Count Reset RT Clock Figure 15-25. Start Bit Search Example 4 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 588 ﬂag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE ﬂag because a break character has no stop bit. The FE ﬂag is set at the same time that the RDRF ﬂag is set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 589 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 – 160) / 167) X 100 = 4.19% MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 590 (SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will still load the receive data into the SCIDRH/L registers, but it will not set the RDRF ﬂag. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 591: Single-Wire Operation
Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 592: Loop Operation
NOTE In loop operation data from the transmitter is not recognized by the receiver if RXPOL and TXPOL are not the same. 15.5 Initialization/Application Information 15.5.1 Reset Initialization Section 15.3.2, “Register Descriptions”. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 593: Modes Of Operation
Active high level. The RDRF interrupt indicates that received data is available in the SCI data register. SCISR1[3] Active high level. This interrupt indicates that an overrun condition has occurred. IDLE SCISR1[4] ILIE Active high level. Indicates that receiver input has become idle. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 594 Active high level. Indicates that a mismatch between transmitted and received data in a single wire application has happened. BKDIF SCIASR1[0] BRKDIE Active high level. Indicates that a break character has been received. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 595 Once the IDLE is cleared, a valid frame must again set the RDRF ﬂag before an idle condition can set the IDLE ﬂag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 596: Recovery From Wait Mode
The SCI interrupt request can be used to bring the CPU out of wait mode. 15.5.5 Recovery from Stop Mode An active edge on the receive input can be used to bring the CPU out of stop mode. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 597: Introduction
Double-buffered data register • Serial clock with programmable polarity and phase • Control of SPI operation during wait mode 16.1.3 Modes of Operation The SPI functions in three modes: run, wait, and stop. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 598: Block Diagram
Figure 16-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 599: External Signal Description
MISO — Master In/Slave Out Pin This pin is used to transmit data out of the SPI module when it is conﬁgured as a slave and receive data when it is conﬁgured as master. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 600: Ss — Slave Select Pin
SPC0 SPICR2 0x0002 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 SPIBR 0x0003 SPIF SPTEF MODF SPISR 0x0004 SPIDRH 0x0005 SPIDRL 0x0006 Reserved 0x0007 Reserved = Unimplemented or Reserved Figure 16-2. SPI Register Summary MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 601: Register Descriptions
SPI system into idle state. 0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock. 1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 602 Module Base +0x0001 XFRW MODFEN BIDIROE SPISWAI SPC0 Reset = Unimplemented or Reserved Figure 16-4. SPI Control Register 2 (SPICR2) Read: Anytime Write: Anytime; writes to the reserved bits have no effect MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 603 Master In Master Out Bidirectional MISO not used by SPI Master In Master I/O Slave Mode of Operation Normal Slave Out Slave In Bidirectional Slave In MOSI not used by SPI Slave I/O MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 604 Baud Rate SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor 12.5 Mbit/s 6.25 Mbit/s 3.125 Mbit/s 1.5625 Mbit/s 781.25 kbit/s 390.63 kbit/s 195.31 kbit/s 97.66 kbit/s 6.25 Mbit/s 3.125 Mbit/s 1.5625 Mbit/s MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 605 39.06 kbit/s 1280 19.53 kbit/s 2.08333 Mbit/s 1.04167 Mbit/s 520.83 kbit/s 260.42 kbit/s 130.21 kbit/s 65.10 kbit/s 32.55 kbit/s 1536 16.28 kbit/s 1.78571 Mbit/s 892.86 kbit/s 446.43 kbit/s 223.21 kbit/s 111.61 kbit/s MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 606 (SPICR2)”. The ﬂag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 607 2. Data in SPIDRH is undeﬁned in this case. 3. SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by writing to SPIDRL after reading SPISR with SPTEF == 1. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 608 If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a third transmission, the data in the receive shift register has become invalid and is not transferred into the SPIDR (see Figure 16-10). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 609: Functional Description
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated SPI port pins are dedicated to the SPI function as: • Slave select (SS) • Serial clock (SCK) • Master out/slave in (MOSI) • Master in/slave out (MISO) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 610: Master Mode
If the SS input becomes low this indicates a mode fault error where another master tries to 1. n depends on the selected transfer width, please refer to Section 16.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 611: Slave Mode
SPI data in a slave mode. For these simpler devices, there is no serial data out pin. NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 612: Transmission Formats
Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity. 1. n depends on the selected transfer width, please refer to Section 16.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 613 SPI. 1. n depends on the selected transfer width, please refer to Section 16.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 614 , and t are guaranteed for the master mode and required for the slave mode. Figure 16-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 615 A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. 1. n depends on the selected transfer width, please refer to Section 16.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 616 = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers Figure 16-14. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width selected (XFRW = 0) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 617: Spi Baud Rate Generation
The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 16-3. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 618: Special Features
The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 619: Error Conditions
In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 620: Low Power Mode Options
SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 621 The MODF interrupt is reﬂected in the status register MODF ﬂag. Clearing the ﬂag will also clear the interrupt. This interrupt will stay active while the MODF ﬂag is set. MODF has an automatic clearing process which is described in Section 16.3.2.4, “SPI Status Register (SPISR)”. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 622 SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process, which is described in Section 16.3.2.4, “SPI Status Register (SPISR)”. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 623: Introduction
Charge pump for static high-side driver operation • Phase voltage measurement with internal ADC • Two low-side current measurement ampliﬁers for DC phase current measurement • Phase comparators for BEMF zero crossing detection in sensorless BLDC applications MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 624: Modes Of Operation
GDU charge pump clock is not running. This means device can not be put in stop mode if FETS needs to be in speciﬁc state to protect the system from external energy supply (e.g. externally driven motor- generator). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 625: Block Diagram
GDU module. Boost Converter Charge Option Pump VBS[2:0] Control HG[2:0] Error HS[2:0] Channels Pre-Drivers VLS[2:0] Channels LG[2:0] IP Bus LS[2:0] Voltage Two Current Sense Regulator Ampliﬁers Figure 17-1. GDU Block Diagram MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 626: External Signal Description
LS[2:0] — Low-Side Source Pins The pins are the low-side source connections for the low-side power FETs. The pins are the power ground pins used to return the gate currents from the low-side power FETs. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 627 =11V. The input voltage to the voltage regulator is the VSUP pin. NOTE A 4.7uF or 10uF capacitor should be connected to this pin for stability of the the voltage regulator output. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 628: Memory Map And Register Deﬁnition
GHHDS GLVLSS GDUSTAT 0x0005 GSRCHS[2:0] GSRCLS[2:0] GDUSRC 0x0006 GSUF GHHDF GLVLSF GOCIF[1:0] GHHDIF GLVLSIF GDUF 0x0007 GBOCD[4:0] GBODC[1:0] GDUCLK1 0x0008 GBCL[3:0] GDUBCL 0x0009 GPHMX[1:0] GDUPHMUX = Unimplemented Figure 17-2. GDU Register Summary MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 629: Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register diagrams, in bit order. Unused bits read back zero. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 630 GDU Current Sense Ampliﬁer 0 Enable— This bit enables the current sense ampliﬁer. See Section 17.4.8, GCSE0 “Current Sense Ampliﬁer and Overcurrent Comparator Current sense ampliﬁer 0 is disabled Current sense ampliﬁer 0 is enabled MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 631 FET pre-drivers. In order to switch on and off the FET pre-drivers the PMF module has to be used to mask and un-mask the PWM channels. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 632 GBKTIM1 & GBKTIM2 must not change. If a different blanking time is required, the PWM channel has to be turned off before new values to GBKTIM1 & GBKTIM2 are written. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 633 GDU Desaturation Error Flag Register (GDUDSE) 17.3.2.4 Module Base + 0x0003 Access: User read/write GDHSIF[2:0] GDLSIF[2:0] Reset = Unimplemented Figure 17-6. GDU Desaturation Error Flag Register (GDUDSE) 1. Read: Anytime Write: Anytime, write 1 to clear MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 634 LS[2:0] occurs. If the GDSEIE bit is set an interrupt is requested. Writing a logic “1” to the bit ﬁeld clears the ﬂag. 0 No desaturation error on low-side driver 1 Desaturation error on low-side driver MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 635 1 Voltage on pin VLS_OUT is less than V LVLSA GDU Slew Rate Control Register (GDUSRC) 17.3.2.6 Module Base + 0x0005 Access: User read/write GSRCHS[2:0] GSRCLS[2:0] Reset = Unimplemented Figure 17-8. GDU Slew Rate Control Register (GDUSRC) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 636 GDU Slew Rate Control Bits Low-Side FET Pre-Drivers — These bits control the slew rate on the LG[2:0] GSRCLS[2:0] pins (see FET Pre-Driver Details). These bits cannot be modiﬁed after GWP bit is set. 000 : slowest 111 : fastest MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 637 FET pre-drivers are turned off and fault[4] is asserted. If GOCAx is set all high-side and low-side FET pre-drivers are turned off and fault[2:0] are asserted. 0 Voltage on overcurrent comparator input is less than V 1 Voltage on overcurrent comparator is greater than V MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 638 The GBODC & GBOCD register bits must be set to the required value before GBOE bit is set. If a different boost clock frequency and duty cycle is required GBOE has to be cleared before new values to GBODC & GBOCD are written. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 639 / 16 10001 / 24 10010 / 32 10011 / 48 10100 / 64 10101 / 96 10110 / 100 10111 / 128 11000 / 192 11001 / 200 11010 / 256 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 640 Chapter 17 Gate Drive Unit (GDUV4) Table 17-10. Boost Option Clock Divider Factors k = BOOST GBOCD[4:0] BOOST 11011 / 384 11100 / 400 11101 / 512 11110 / 768 11111 / 800 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 641 01 Pin HS0 selected , V / 6 connected to ADC channel 10 Pin HS1 selected , V / 6 connected to ADC channel 11 Pin HS2 selected, V / 6 connected to ADC channel MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 642 110 Offset is -10mV 111 Offset is -5mV 17.3.2.12 GDU Desaturation Level Register (GDUDSLVL) Module Base + 0x000B Access: User read/write GDSLHS[2:0] GDSLLS[2:0] Reset = Unimplemented Figure 17-14. GDU Desaturation Level Register (GDUDSLVL) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 643 = 0.45V desatls 010 V = 0.60V desatls 011 V = 0.75V desatls 100 V = 0.90V desatls 101 V = 1.05V desatls 110 V = 1.20V desatls 111 V = 1.35V desatls MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 644 The GCPCD bits must be set to the required value before GCPE bit is set. If a different charge pump clock frequency is required GCPE has to be cleared before new values to GCPCD bits are written. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 645 / 96 0110 / 100 0111 / 128 1000 / 192 1001 / 200 1010 / 256 1011 / 384 1100 / 400 1101 / 512 1110 / 768 1111 / 800 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 646 GDU Overcurrent Register 1 (GDUOC1) 17.3.2.16 Module Base + 0x000F Access: User read/write GOCA1 GOCE1 GOCT1[3:0] Reset = Unimplemented Figure 17-18. GDU Overcurrent Register 1 (GDUOC1) 1. Read: Anytime Write: Only if GWP=0 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 647: Functional Description
FET C is drawn from the output of the voltage regulator VLS. Figure . The register bits GSRCLS[2:0] in the GDUSRC Register (see Figure 17-8) control the slew MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 648: High-Side Fet Pre-Driver
V ~ 0V and V ~ 0V so that the external FETs are turned off. NOTE The PWM channel outputs for high-side and low-side drivers are delayed by two core clock cycles. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 649 Figure 17-19. FET Pre-Driver Circuit and Voltage Regulator NOTE Optional charge pump input RC ﬁlter can be used to avoid overpumpimg effect when voltage spikes are present on the high-side drains. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 650: Charge Pump
CP is V The output voltage on pin CP typically switches between 0 and VLS. 11V. The charge pump clock frequency depends on the setting of GCPCD bits. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 651: Desaturation Error
Figure 17-20. Desaturation Comparators and Phase Comparators GDSLHS[2:0] Desat. Comp. High-Side Driver Desaturation Error High-Side desaths High-Side FET Pre-Driver hs_on Phase Comp. Phase Status Low-Side FET Pre-Driver ls_on Desat. Comp. Low-Side Driver Desaturation Error Low-Side. sense GDSLLS[2:0] desatls MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 652: Phase Comparators
[2]) | ( [0] & 0) | ( [1] & GDLSIF GDHSIF GOCIF GOCA GOCIF GOCA Fault[3] GLVLSIF Fault[4] [0] & ~ 0) | ( [1] & ~ GHHDIF GOCIF GOCA GOCIF GOCA MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 653 Table 17-22. Fault Protection Features Summary Prior GDHSIF GDLSIF Condition GSUF GHHDF GOCIF0 GOCIF1 GLVLSF [2:0] [2:0] normal operation,no error condition, FET pre-driver driven by PMF module startup condition after reset deassert, no error condition overvoltage on HD pin GOCA1=0 overcurrent condition comparator 0 GOCA0=0 overcurrent condition comparator 1...
Page 654 If such operating condition exist the application must make sure that VBSX levels are clamped below maximum ratings for example by using clamping diodes. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 655 HSx fault Phase Status correct Desat. Error Figure 17-22. Short to Ground Detection BLANK correct voltage on HSx 0.5 V HSx shorted to ground correct Phase Status fault Desat. Error MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 656: Current Sense Ampliﬁer And Overcurrent Comparator
Figure 17-23. Current Sense Ampliﬁer Connected as Differential Ampliﬁer GOCEx GOCTx[3:0] Overcurrent Condition < V sense 6 bit GCSE0 GCSO0[2:0] Output Voltage to ADC AMPP[0] = a V sense offset AMP[0] AMPM[0] sense sense MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 657: Gdu Dc Link Voltage Monitor
Section 17.3.2.10, “GDU Phase Mux Register (GDUPHMUX) voltage on pin HD divide by 5 is routed to an ADC channel. See SOC section for ADC channel number. This feature is only available if GFDE is set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 658: Boost Converter
Clock Frequency & Duty Cycle Output Voltage Control COIL Current Limitation Enable Disable GBCL[3:0] GBOE refcl GBOCD[4:0] GBODC[1:0] VSSB 1. Diode D2 shown is optional if coil is connected behind reverse battery protection. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 659: Interrupts
GDU low voltage condition on pin VLS GLVLSIE = 1 detection and overcurrent (GLVLSIF) detection interrupt GDU high voltage condition on pin HD GHHDIE = 1 (GHHDIF) GDU Overcurrent Condition GOCIE[1:0]=11 (GOCIF[1:0]) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 660: Application Information
HSpul • = k I OUT1 OUT2 • ) (1+k) OUT1 OUT2 • Figure 17-25. FET Pre-Driver Concept for High-Side Driver out2 out1 gduon Driver On GSRCHS[2:0] Driver Off HSpul gduoffn gduoffp MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 661: Calculation Of Bootstrap Capacitor
Eqn. 17-1 Q BS V BS ------------------------- - ------------------- - C BS ---------- - C BS For example if C = 20 C then the resulting gate voltage is V = 0.95 V MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 662 Chapter 17 Gate Drive Unit (GDUV4) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 663: Introduction
The LIN Physical Layer is designed to meet the LIN Physical Layer 2.2 speciﬁcation from LIN consortium. 18.1.1 Features The LIN Physical Layer module includes the following distinctive features: • Compliant with LIN Physical Layer 2.2 speciﬁcation. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 664: Modes Of Operation
LIN Physical Layer sends a wake-up pulse to the SCI, which requests a wake-up interrupt. (This feature is only available if the LIN Physical Layer is routed to the SCI). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 665: Block Diagram
Figure 18-1. LIN Physical Layer Block Diagram NOTE The external 220 pF capacitance between LIN and LGND is strongly recommended for correct operation. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 666: External Signal Description
In standby mode this output is disabled, and sends only a short pulse in case the wake-up functionality is enabled and a valid wake-up pulse was received in the LIN Bus. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 667: Memory Map And Register Deﬁnition
Reserved Reserved 0x0003 LPDTDIS LPSLR1 LPSLR0 LPSLRM 0x0004 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LPDT 0x0005 LPSR 0x0006 LPDTIE LPOCIE LPIE 0x0007 LPDTIF LPOCIF LPIF Figure 18-2. Register Summary MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 668: Register Descriptions
The routing of the LPTxD input is done in the Port Inetrgation Module (PIM). Please refer to the PIM chapter of the device Reference Manual for more info. Port LP Data Bit 0 — Read-only bit. The LIN Physical Layer LPRxD output state can be read at any time. LPDR0 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 669 LIN Pullup Resistor Enable — Selects pullup resistor. LPPUE 0 The pullup resistor is high ohmic (330 kΩ). 1 The 34 kΩ pullup is switched on (except if LPE=0 or when in standby mode with LPWUE=0) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 670 LIN Slew Rate Mode Register (LPSLRM) Module Base + Address 0x0003 Access: User read/write LPDTDIS LPSLR1 LPSLR0 Reset = Unimplemented Figure 18-6. LIN Slew Rate Mode Register (LPSLRM) 1. Read: Anytime Write: Only in shutdown mode (LPE=0) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 671 Table 18-6. Reserved Register Field Description Field Description These reserved bits are used for test purposes. Writing to these bits can alter the module functionality. Reserved MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 672 LPTDIF is set again after attempting to clear it. 0 If there was a TxD-dominant timeout, LPTxD has ceased to be dominant after the timeout. 1 LPTxD is still dominant after a TxD-dominant timeout. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 673 0 Interrupt request is disabled. 1 Interrupt is requested if LPDTIF bit is set. LIN transmitter Overcurrent Interrupt Enable — LPOCIE 0 Interrupt request is disabled. 1 Interrupt is requested if LPOCIF bit is set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 674 If the overcurrent is still present or LPTxD is dominant after clearing the ﬂag, the transmitter stays disabled and this ﬂag is set again (see18.4.4.1 Overcurrent Interrupt). If interrupt requests are enabled (LPOCIE= 1), LPOCIF causes an interrupt request. 0 No overcurrent event has occurred. 1 Overcurrent event has occurred. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 675: Functional Description
A stronger external pullup resistor might be necessary to sustain communication speeds up to 250 kbit/s. The LIN signal (and therefore the receive LPRxD signal) might not be symmetrical for high baud rates with high loads on the bus. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 676: Modes
If LPWUE is not set, no wake up feature is available and the standby mode has the same electrical properties as the shutdown mode. This allows a low-power consumption of the device in stop mode if the wake-up feature is not needed. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 677 SCI interrupt, then the SCI interrupt will execute ﬁrst). It is up to the software to decide what to do in this case because the LIN Physical Layer can not guarantee it was a valid wake-up pulse. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 678 Chapter 18 LIN Physical Layer (S12LINPHYV2) Figure 18-11. LIN Physical Layer Mode Transitions MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 679: Interrupts
2 IRC periods (2 us) + 3 bus periods If the bit LPOCIE is set in the LPIE register, an interrupt is requested. Figure 18-12 shows the different scenarios for overcurrent interrupt handling. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 680 To re-enable the transmitter then, the LPDTIF ﬂag must be cleared (by writing a 1). NOTE Please make sure that LPDTIF=1 before trying to clear it. It is not allowed to try to clear LPDTIF if LPDTIF=0 already. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 681 2 IRC periods (2 us) + 3 bus periods If the bit LPDTIE is set in the LPIE register, an interrupt is requested. Figure 18-13 shows the different scenarios of TxD-dominant timeout interrupt handling. Figure 18-13. TxD-dominant timeout interrupt handling MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 682: Application Information
— If the receiver must remain enabled, set the LIN Physical Layer into receive only mode instead. 2. Do all required conﬁgurations (SCI, etc.) to re-enable the transmission. 3. Wait for a transmit bit (this is needed to successfully re-enable the transmitter). MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 683 7. Wait for a minimum of a transmit bit before beginning transmission again. If there is a problem re-enabling the transmitter, then the error ﬂag will be set again during step 3 and the ISR will be called again. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 684 Chapter 18 LIN Physical Layer (S12LINPHYV2) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 685: Chapter 19
- Standardized nomenclature in references to memory sizes V02.07 24 May 2013 - Revised references to NVM Resource Area to improve readability V02.8 12 Jun 2013 - Changed MLOADU Section 19.4.7.12 and MLOADF Section 19.4.7.13 FCCOB1 to FCCOB2 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 686: Introduction
EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data. EEPROM Sector — The EEPROM sector is the smallest portion of the EEPROM memory that can be erased. The EEPROM sector consists of 4 bytes. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 687: Features
No external high-voltage power supply required for Flash memory program and erase operations • Interrupt generation on Flash command completion and Flash error detection • Security mechanism to prevent unauthorized access to the Flash memory MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 688: Block Diagram
Interrupt Request sector 255 Security Clock Clock Divider FCLK Memory Controller EEPROM 256x22 sector 0 sector 1 sector 127 19.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 689: Memory Map And Registers
19.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0xFF_8000 in the Flash memory (called the lower region), one growing downward from global address MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 690 Section 19.3.2.2, “Flash Security Register (FSEC)” 1. 0xFF_FE08-0xFF_FE0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0xFF_FE0A - 0xFF_FE0B reserved ﬁeld should be programmed to 0xFF. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 691 Protection Fixed End Flash Protected/Unprotected Higher Region 0xFF_E000 2, 4, 8, 16 KB 0xFF_F000 0xFF_F800 Flash Conﬁguration Field P-Flash END = 0xFF_FFFF 16 bytes (0xFF_FE00 - 0xFF_FE0F) Figure 19-2. P-Flash Memory Map MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 692 Reserved 0x1F_9800 – 0x1F_BFFF 10,240 Reserved 0x1F_C000 – 0x1F_C0FF P-Flash IFR (see Table 19-5) 0x1F_C100 – 0x1F_C1FF Reserved. 0x1F_C200 – 0x1F_FFFF 15,872 Reserved. 1. See Section 19.4.4 for NVM Resources Area description. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 693: Register Descriptions
& Name FDIVLD 0x0000 FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 FCLKDIV KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0x0001 FSEC 0x0002 CCOBIX2 CCOBIX1 CCOBIX0 FCCOBIX Figure 19-4. FTMRZ128K512 Register Summary MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 694 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 FCCOB1HI 0x000F CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 FCCOB1LO 0x0010 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 FCCOB2HI Figure 19-4. FTMRZ128K512 Register Summary (continued) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 695 All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV ﬁeld in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 696 39.6 0x26 13.6 14.6 0x0D 39.6 40.6 0x27 14.6 15.6 0x0E 40.6 41.6 0x28 15.6 16.6 0x0F 41.6 42.6 0x29 16.6 17.6 0x10 42.6 43.6 0x2A 17.6 18.6 0x11 43.6 44.6 0x2B MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 697 Flash security byte during the reset sequence, all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 698 Offset Module Base + 0x0002 CCOBIX[2:0] Reset = Unimplemented or Reserved Figure 19-7. FCCOB Index Register (FCCOBIX) CCOBIX bits are readable and writable while remaining bits read 0 and are not writable. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 699 1 Wait-State switch is complete, Flash reads are already working according to the value set on FCNFG[WSTAT] 19.3.2.5 Flash Conﬁguration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt, control generation of wait-states and forces ECC faults on Flash array read access from the CPU. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 700 19.4.3. The WSTAT[1:0] bits should not be updated while the Flash is executing a command (CCIF=0); if that happens the value of this ﬁeld will not change and no action will take place. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 701 The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. Offset Module Base + 0x0005 SFDIE Reset = Unimplemented or Reserved Figure 19-10. Flash Error Conﬁguration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 702 Memory Controller Busy Flag — The MGBUSY ﬂag reﬂects the active state of the Memory Controller MGBUSY 0 Memory Controller is idle 1 Memory Controller is busy executing a Flash command (CCIF = 0) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 703 2. There is a one cycle delay in storing the ECC DFDF and SFDIF fault ﬂags in this register. At least one NOP is required after a ﬂash memory read before checking FERSTAT for the occurrence of ECC errors. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 704 Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area FPHS[1:0] in P-Flash memory as shown inTable 19-21. The FPHS bits can only be written to while the FPHDIS bit is set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 705 Flash memory at global address 0xFF_FE0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 706 FLASH START 0xFF_8000 0xFF_FFFF Protected region with size Unprotected region defined by FPLS Protected region Protected region with size not defined by FPLS, FPHS defined by FPHS Figure 19-14. P-Flash Protection Scenarios MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 707 EEPROM protection byte in the Flash configuration field at global address 0xFF_FE0D located in P-Flash memory (see Table 19-4) as indicated by reset condition F in Table 19-25. To change the MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 708 The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. 1111 0x10_0000 – 0x10_01FF 512 bytes 19.3.2.11 Flash Option Register (FOPT) The FOPT register is the Flash option register. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 709 All bits in the FRSV1 register read 0 and are not writable. 19.3.2.13 Flash Common Command Object Registers (FCCOB) The FCCOB is an array of six words. Byte wide reads and writes are allowed to the FCCOB registers. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 710 Offset Module Base + 0x000F CCOB[7:0] Reset Figure 19-21. Flash Common Command Object 1 Low Register (FCCOB1LO) Offset Module Base + 0x0010 CCOB[15:8] Reset Figure 19-22. Flash Common Command Object 2 High Register (FCCOB2HI) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 711 Offset Module Base + 0x0014 CCOB[15:8] Reset Figure 19-26. Flash Common Command Object 4 High Register (FCCOB4HI) Offset Module Base + 0x0015 CCOB[7:0] Reset Figure 19-27. Flash Common Command Object 4 Low Register (FCCOB4LO) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 712 Table 19-27. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Register Byte FCCOB Parameter Fields (NVM Command Mode) FCMD[7:0] deﬁning Flash command FCCOB0 Global address [23:16] Global address [15:8] FCCOB1 Global address [7:0] Data 0 [15:8] FCCOB2 Data 0 [7:0] MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 713: Functional Description
Reference Manual for details). Forcing the DFDF status bit by setting FDFD (see Section 19.3.2.5) has effect only on the DFDF status bit value and does not result in an invalid access. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 714: Internal Nvm Resource
IFR is an internal NVM resource readable by CPU . The IFR ﬁelds are shown in Table 19-5. The NVM Resource Area global address map is shown in Table 19-6. 19.4.5 Flash Command Operations Flash command operations are used to modify Flash memory contents. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 715 Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The ﬂow for a generic command write sequence is shown in Figure 19-30. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 716 More Parameters? Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 19-30. Generic Flash Command Write Sequence Flowchart MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 717 Erase EEPROM Sector ∗ ∗ ∗ ∗ 0x13 Protection Override 1. Unsecured Normal Single Chip mode 2. Unsecured Special Single Chip mode. 3. Secured Normal Single Chip mode. 4. Secured Special Single Chip mode. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 718 Supports a mode to temporarily override Protection conﬁguration (for P-Flash and/or 0x13 Override EEPROM) by verifying a key. 19.4.5.5 EEPROM Commands Table 19-31 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 719: Allowed Simultaneous P-Flash And Eeprom Operations
Even if the simultaneous operation is marked as not allowed the Flash will report an illegal access only in the cycle the read collision actually happens, maximizing the time the array is available for reading. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 720: Flash Command Description
(see Section 19.3.2.7). CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 721 P-Flash or EEPROM block is erased. The CCIF ﬂag will set after the Erase Verify Block operation has completed.If the block is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 722 Set if any errors have been encountered during the read or if blank check failed. Set if any non-correctable errors have been encountered during the read or if MGSTAT0 blank check failed. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 723 The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an embedded algorithm. CAUTION A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 724 Flash block containing the Program Once reserved field to avoid code runaway. Table 19-43. Program Once Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters FCCOB0 0x07 Not Required FCCOB1 Program Once phrase index (0x0000 - 0x0007) FCCOB2 Program Once word 0 value MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 725 During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF ﬂag will set after the Erase All Blocks operation has completed. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 726 Set if any errors have been encountered during the erase verify operation, or MGSTAT1 FSTAT during the program verify operation Set if any non-correctable errors have been encountered during the erase verify MGSTAT0 operation, or during the program verify operation MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 727 Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF ﬂag will be set after the Erase P-Flash Sector operation has completed. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 728 FSEC register (see Table 19-10). The Verify Backdoor Access Key command releases security if user- supplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 19- MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 729 P-Flash or EEPROM block. Table 19-56. Set User Margin Level Command FCCOB Requirements Register FCCOB Parameters Global address [23:16] to identify Flash FCCOB0 0x0D block FCCOB1 Global address [15:0] to identify Flash block MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 730 User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 731 Return to Normal Level 0x0001 User Margin-1 Level 0x0002 User Margin-0 Level 0x0003 Field Margin-1 Level 0x0004 Field Margin-0 Level 1. Read margin to the erased state 2. Read margin to the programmed state MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 732 EEPROM memory is erased. The CCIF ﬂag will set after the Erase Verify EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 733 Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF ﬂag is set when the operation has completed. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 734 Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 735 (i.e. 16’hFFFF) the Protection Override feature is permanently disabled. If the command execution is ﬂagged as an error (ACCERR being set for incorrect command launch) the values of FPROT and DFPROT will not be modiﬁed. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 736: Interrupts
(FSTAT register) (FCNFG register) ECC Single Bit Fault on Flash Read SFDIF SFDIE I Bit (FERSTAT register) (FERCNFG register) NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 737: Wait Mode
MCU reset. The following subsections describe these security-related subjects: • Unsecuring the MCU using Backdoor Key Access • Unsecuring the MCU in Special Single Chip Mode using BDM MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 738: Unsecuring The Mcu Using Backdoor Key Access
Reference Manual. Alternatively, a similar (non-automated) procedure to unsecure the MCU in special single chip mode can be done by using the following method to erase the P-Flash and EEPROM memory: 1. Reset the MCU into special single chip mode MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 739: Mode And Security Effects On Flash Command Availability
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 740 Chapter 19 128 KB Flash Module (S12ZFTMRZ128K512V2) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 741: A.1 General
T: These parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. • D: These parameters are derived mainly from simulations. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 742 These consist of the LIN, BST, HD, VCP, CP, VLS_OUT, VLS[2:0], VBS[2:0], HG[2:0], HS[2:0], LG[2:0] pins. These pins are intended to interface to external components operating in the automotive battery range. They have nominal voltages above the standard 5V I/O voltage range. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 743 Figure A-1. Current Injection on GPIO Port if V > V VSUP Voltage Regulator Pad Driver VDDX Load Load > V VSSX VSSA MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 744 TEST input –0.3 10.0 TEST Instantaneous current. Single pin limit for all digital I/O pins –25 Instantaneous maximum current on EVDD1 EVDD1 Instantaneous maximum current. Single pin limit for EXTAL, XTAL –25 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 745 Minimum Input Voltage Limit HD/VCP/ Maximum Input Voltage Limit BST/LIN/ BCTL/BCTLC Latch-up for Minimum Input Voltage Limit HG,HS Maximum Input Voltage Limit (VBS=10V) Latch-up for Minimum Input Voltage Limit LG,LS Maximum Input Voltage Limit (VLS=10V) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 746 3. 4.7µF ceramic or 10µF tantalum 4. Can be placed anywhere on the 5V supply node (VDDA, VDDX) 5. One capacitor per each VLS[2:0] pin 6. Can be placed anywhere on the VLS node MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 747 T 4. Refer to f for minimum ADC operating frequency. This is derived from the bus clock. ATDCLK NOTE Operation is guaranteed when powering down until low voltage reset assertion. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 748 Power dissipation of LINPHY = (-V ) + (V Power dissipation of FET-Predriver without the outputs VLS_OUT VLS_OUT ) + (V switching VLSn VLSn 1. No switching. GDU power consumption is very load dependent. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 749 JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal. 3. Junction to ambient thermal resistance, θ was simulated to be equivalent to the JEDEC speciﬁcation JESD51-6 with the board (JESD51-7) horizontal. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 750 6. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface resistance 7. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 751 8°C to 12°C in the temperature range from 50°C to 125°C. 2. For better ADC accuracy, the application should avoid current injection into pin PAD8/VREFH. Refer to Section A.1.3, “Current Injection” for more details MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 752 Run, Wait and Stop current measurement. Table A-11. CPMU Conﬁguration for Pseudo Stop Current Measurement CPMU REGISTER Bit settings/Conditions CPMUCLKS PLLSEL=0, PSTP=1, CSAD=0, PRE=PCE=RTIOSCSEL=1 COPOSCSEL[1:0]=01 CPMUOSC OSCE=1, Quartz oscillator f =4MHz EXTAL CPMURTI RTDEC=0, RTR[6:4]=111, RTR[3:0]=1111 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 753 LDO enabled. Charge pump enabled. Current sense0 enabled. Boost disabled. No output activity (too load dependent) COP & RTI Enabled BATS Enabled LINPHY connected to SCI and continuously transmit data (0x55) at speed of 19200 baud MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 754 IFR are the average of eight consecutive conversions at Tj=150 ˚C and eight consecutive conversions at Tj=-40 ˚C. The code is executed from RAM. The result is programmed to the IFR, otherwise there is no ﬂash activity. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 755 Supply Voltage at VDDX and VDDA DDX,A ADC reference voltage high ADC reference voltage low ADC clock ATDCLK ADC sample time ADC clock cycles Bus clock frequency °C Junction temperature -40 and 150 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 756 Appendix A MCU Electrical Speciﬁcations MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 757 Full Performance Mode 5.5V <= V <=6V 4.50 5.15 Full Performance Mode 3.5V <= V <=5.5V 3.13 — 5.15 Reduced Performance Mode (stop) V > =3.5V 5.75 Load Current VDDC Reduced Performance Mode (stop mode) — MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 758 8. The ACLK trimming must be set that the minimum period equals to 0.2ms 9. VREGHTTR=0x88 10. This is the minimum base current that can be guaranteed when the external PNP is delivering maximum current. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 759: B.3 Phase Locked Loop
VCOCLK frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure B-1.. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 760 ⋅ ⎝ ⎠ The following equation is a good ﬁt for the maximum jitter: ------------------------------------------------- - N POSTDIV J(N) Figure B-2. Maximum Bus Clock Jitter Approximation (N = number of bus cycles) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 761 T Jitter ﬁt parameter 1 150 C < T < 175 — — M PLL Clock Monitor Failure assert frequency 0.45 PMFA 1. % deviation from target frequency 2. f = 1MHz, f = 50MHz MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 762 Appendix B CPMU Electrical Speciﬁcations (VREG, OSC, IRC, PLL) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 763: C.1 Adc Operating Characteristics
Source resistance, source capacitance and current injection have an inﬂuence on the accuracy of the ADC .Figure C-1. A further factor is that PortAD pins that are conﬁgured as output drivers switching. MC9S12ZVM Family Reference Manual Rev. 1.2 Freescale Semiconductor...
Page 764 The additional input voltage error on the converted channel can be calculated as: = K * R with I being the sum of the currents injected into the two pins adjacent to the converted channel. MC9S12ZVM Family Reference Manual Rev. 1.2 Freescale Semiconductor...
Page 765 Cstray < 1.8pF VSSA (incl parasitics) bottom connected to low ohmic supply during sampling Switch resistance depends on input voltage, corner ranges are shown. Leakage current is guaranteed by speciﬁcation. =150 jmax Figure C-1. MC9S12ZVM Family Reference Manual Rev. 1.2 Freescale Semiconductor...
Page 766 ------------------------- - 1 – 1LSB The integral non-linearity (INL) is deﬁned as the sum of all DNLs: ∑ – INL n ( ) DNL i ( ) -------------------- - n – 1LSB MC9S12ZVM Family Reference Manual Rev. 1.2 Freescale Semiconductor...
Page 767 $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 $3F3 Ideal Transfer Curve 10-Bit Transfer Curve 8-Bit Transfer Curve 95 100 105 110 115 120 5000 + Figure C-2. ADC Accuracy Deﬁnitions MC9S12ZVM Family Reference Manual Rev. 1.2 Freescale Semiconductor...
Page 768 1. The 8-bit and 10-bit mode operation is structurally tested in production test. Absolute values are tested in 12-bit mode. 2. These values include the quantization error which is inherently 1/2 count for any A/D converter. MC9S12ZVM Family Reference Manual Rev. 1.2 Freescale Semiconductor...
Page 769: D.1 Static Electrical Characteristics
LINSUP ° 3. At temperatures above 25 C the current may be naturally limited by the driver, in this case the limitation circuit is not engaged and the ﬂag is not set. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 770: D.2 Dynamic Electrical Characteristics
= 0.251 x V HDom(min) LINSUP = 7.6V...18V LINSUP = 96us D4 = t / (2 x t Bus_rec(max) LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST MODE SLEW RATE - 100KBIT/S UP TO 250KBIT/S MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 771 Rising/falling edge time (min to max / max to min) — — rise µs Over-current masking window (IRC trimmed at 1MHz) — OCLIM 1. For 3.5V<=V <7V, the LINPHY is still working but with degraded parametrics. LINSUP MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 772 Appendix D LINPHY Electrical Speciﬁcations MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 773: Appendix E
P HGx to HSx, LGx to LSx RDSon (driver off state) — gduoffn nmos part, -40°C < T < 150°C (10) Ω M HGx to HSx, LGx to LSx RDSon (driver off state) nmos — gduoffn part, 150°C < T < 175°C MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 774: Appendix E
5. Total gate charge spec is only a recommendation. FETs with higher gate charge can be used when resulting slew rates are tolerable by the application and resulting power dissipation does not lead to thermal overload. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 775: Appendix E
11. V(VBSx) - V(VLSx) > 9V, resp VLSx > 9V, pmos branch only 12. VLS > 6V 13. Output current range for which the effective output resistance speciﬁcation applies 14. Av=10, no frequency compensation in feedback network, 90% output swing MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 776: Appendix E
Appendix E GDU Electrical Speciﬁcations MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 777: F.1 Nvm Timing Parameters
ﬂash commands. All timing parameters are a function of the bus clock frequency, f . All NVMBUS program and erase times are also a function of the NVM operating frequency, f . A summary of key NVMOP timing parameters can be found in Table F-1. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 778 NVMOP NVMBUS 4. Worst times are based on minimum f and minimum f plus aging NVMOP NVMBUS 5. Affected by Pﬂash size 6. Affected by EEPROM size MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 779 NVMOP NVMBUS 4. Worst times are based on minimum f and minimum f plus aging NVMOP NVMBUS 5. Affected by Pﬂash size 6. Affected by EEPROM size MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 780: F.2 Nvm Reliability Parameters
Devices are shipped from the factory with ﬂash and EEPROM in the erased state. Data retention speciﬁcations begin at time of this erase operation. For additional information on how Freescale deﬁnes Typical Data Retention, please refer to Engineering Bulletin EB618. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 781: G.1 Static Electrical Characteristics
Analog Input Matching – +-2% +-5% – Matching Absolute Error on V - compared to V / Ratio VSUP 1. T : Ambient Temperature 2. V : Voltage accessible at the ADC input channel MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 782: G.2 Dynamic Electrical Characteristics
T = 25˚C under nominal conditions.. Ratings Symbol Unit Enable Uncertainty Time – – EN_UNC Voltage Warning Low Pass Filter – – VWLP_ﬁlter 1. T : Ambient Temperature MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 783: H.1 Master Mode
2. LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure H-2. SPI Master Timing (CPHA=0) In Figure H-3. the timing diagram for master mode with transmission format CPHA=1 is depicted. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 784 -1.2 — — Rise and Fall Time Inputs — — rﬁ Rise and Fall Time Outputs — — 1. See Figure H-4. °C 2. f max is 40MHz at temperatures above 150 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 785 BIT 6 . . . 1 SLAVE LSB OUT SLAVE MSB (OUTPUT) note note MOSI MSB IN BIT 6 . . . 1 LSB IN (INPUT) NOTE: Not defined! Figure H-5. SPI Slave Timing (CPHA=0) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 786 Rise and Fall Time Inputs — — rﬁ Rise and Fall Time Outputs — — °C 1. f max is 40MHz at temperatures above 150 2. 0.5t added due to internal synchronization delay MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 787 Conditions are 4.5 V < V < 5.5 V, unless otherwise noted. Num C Rating Symbol Unit µs MSCAN wake-up dominant pulse ﬁltered — — µs MSCAN wake-up dominant pulse pass — — MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 788 Appendix I MSCAN Electrical Speciﬁcations MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 789 Appendix J Package Information Appendix J Package Information Figure J-1. 64LQFP-EP Mechanical Information MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 790 Appendix J Package Information MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 791 Appendix J Package Information Freescale’s Package Reﬂow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reﬂow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number and review parametrics. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 792 Controller Family Main Memory Type: 9 = Flash Status / Partnumber type: S or SC = Maskset specific partnumber MC = Generic / mask-independent partnumber P or PC = prototype status (pre qualification) MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 793: L.1 0X0000–0X0003 Part Id
0x0000–0x0003 Part ID Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0000 PARTID0 0x0001 PARTID1 0x0002 PARTID2 Revision Dependent 0x0003 PARTID3 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 794: L.2 0X0010–0X001F S12Zint
PRIOLVL[2:0] 0x001D INT_CFDATA5 PRIOLVL[2:0] 0x001E INT_CFDATA6 PRIOLVL[2:0] 0x001F INT_CFDATA7 PRIOLVL[2:0] 0x0070-0x00FF S12ZMMC Address Name Bit 7 Bit 0 0x0070 MODE MODC 0x0071- Reserved 0x007F 0x0080 MMCECH ITR[3:0] TGT[3:0] 0x0081 MMCECL ACC[3:0] ERR[3:0] MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 795: L.4 0X0100-0X017F S12Zdbg
0x0104 DBGTBH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0105 DBGTBL 0x0106 DBGCNT 0x0107 DBGSCR1 C3SC1 C3SC0 C2SC1 C2SC0 C1SC1 C1SC0 C0SC1 C0SC0 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 796 Bit 7 Bit 0 0x011C DBGADM0 Bit 31 Bit 24 0x011D DBGADM1 Bit 23 Bit 16 0x011E DBGADM2 Bit 15 Bit 8 0x011F DBGADM3 Bit 7 Bit 0 0x0120 DBGBCTL INST reserved COMPE MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 797 Bit 7 Bit 0 0x013C DBGCDM0 Bit 31 Bit 24 0x013D DBGCDM1 Bit 23 Bit 16 0x013E DBGCDM2 Bit 15 Bit 8 0x013F DBGCDM3 Bit 7 Bit 0 0x0140 DBGDCTL INST reserved COMPE MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 798 Appendix L Detailed Register Address Map 0x0100-0x017F S12ZDBG Address Name Bit 7 Bit 0 0x0141- Reserved 0x0144 0x0145 DBGDAH DBGDA[23:16] 0x0146 DBGDAM DBGDA[15:8] 0x0147 DBGDAL DBGDA[7:0] 0x0148- Reserved 0x017F MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 799: L.5 0X0200-0X02Ff Pim
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x020F Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0210– Reserved 0x025F 0x0260 PTE1 PTE0 0x0261 Reserved PTIE1 PTIE0 0x0262 PTIE 0x0263 Reserved MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 800 DDRADL7 DDRADL6 DDRADL5 DDRADL4 DDRADL3 DDRADL2 DDRADL1 DDRADL0 0x0286 PERADH PERADH0 0x0287 PERADL PERADL7 PERADL6 PERADL5 PERADL4 PERADL3 PERADL2 PERADL1 PERADL0 0x0288 PPSADH PPSADH0 0x0289 PPSADL PPSADL7 PPSADL6 PPSADL5 PPSADL4 PPSADL3 PPSADL2 PPSADL1 PPSADL0 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 801 0x02C0 PTT3 PTT2 PTT1 PTT0 PTIT3 PTIT2 PTIT1 PTIT0 0x02C1 PTIT 0x02C2 DDRT DDRT3 DDRT2 DDRT1 DDRT0 0x02C3 PERT PERT3 PERT2 PERT1 PERT0 0x02C4 PPST PPST3 PPST2 PPST1 PPST0 0x02C5– Reserved 0x02CF MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 802 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 0x02E0– Reserved 0x02EF 0x02F0 PTP2 PTP1 PTP0 PTIP2 PTIP1 PTIP0 0x02F1 PTIP 0x02F2 DDRP DDRP2 DDRP1 DDRP0 0x02F3 PERP PERP2 PERP1 PERP0 0x02F4 PPSP PPSP2 PPSP1 PPSP0 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 803: L.6 0X0380-0X039F Ftmrz128K512
FCNFG CCIE IGNSF WSTAT[1:0] FDFD FSFD 0x0385 FERCNFG SFDIE MGBUSY RSVD MGSTAT1 MGSTAT0 0x0386 FSTAT CCIF ACCERR FPVIOL 0x0387 FERSTAT DFDF SFDIF RNV6 0x0388 FPROT FPOPEN FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 804: L.7 0X03C0-0X03Cf Sram_Ecc_32D7P
CCOB1 CCOB0 0x0396 FCCOB5HI CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 0x0397 FCCOB5LO CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0x03C0-0x03CF SRAM_ECC_32D7P Address Name Bit 7 Bit 0 0x03C0 ECCSTAT MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 805: L.8 0X0500-X053F Pmf15B6C
BOTNEGC TOPNEGC BOTNEGB TOPNEGB BOTNEGA TOPNEGA 0x0502 PMFCFG2 REV1 REV0 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 0x0503 PMFCFG3 PMFWAI PMFFRZ VLMODE PINVC PINVB PINVA 0x0504 PMFFEN FEN5 FEN4 FEN3 FEN2 FEN1 FEN0 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 806 OUT2 OUT1 OUT0 0x050E PMFDTMS 0x050F PMFCCTL ISENS IPOLC IPOLB IPOLA 0x0510 PMFVAL0 PMFVAL0 0x0511 PMFVAL0 PMFVAL0 0x0512 PMFVAL1 PMFVAL1 0x0513 PMFVAL1 PMFVAL1 0x0514 PMFVAL2 PMFVAL2 0x0515 PMFVAL2 PMFVAL2 0x0516 PMFVAL3 PMFVAL3 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 807 CINV0 0x0520 PMFENCA PWMENA GLDOKA RSTRTA LDOKA PWMRIEA 0x0521 PMFFQCA LDFQA HALFA PRSCA PWMRFA PMFCNTA 0x0522 PMFCNTA PMFCNTA 0x0523 PMFCNTA 0x0524 PMFMODA PMFMODA 0x0525 PMFMODA PMFMODA 0x0526 PMFDTMA PMFDTMA 0x0527 PMFDTMA PMFDTMA MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 808 PWMRFB PMFCNTB 0x052A PMFCNTB PMFCNTB 0x052B PMFCNTB 0x052C PMFMODB PMFMODB 0x052D PMFMODB PMFMODB 0x052E PMFDTMB PMFDTMB 0x052F PMFDTMB PMFDTMB 0x0530 PMFENCC PWMENC GLDOKC RSTRTC LDOKC PWMRIEC 0x0531 PMFFQCC LDFQC HALFC PRSCC PWMRFC MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 809: L.9 0X0580-0X059F Ptu
DMP40 0x053D PMFDMP5 DMP55 DMP54 DMP53 DMP52 DMP51 DMP50 0x053E PMFOUTF OUTF5 OUTF4 OUTF3 OUTF2 OUTF1 OUTF0 0x053F Reserved 0x0580-0x059F PTU Address Name Bit 7 Bit 0 0x0580 PTUE PTUFRZ TG1EN TG0EN MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 810 TG0TNUM[4:0] 0x0587 TG0TNUM TG0TV[15:8] 0x0588 TG0TVH TG0TV[7:0] 0x0589 TG0TVL TG1LIST 0x058A TG1LIST TG1TNUM4:0] 0x058B TG1TNUM TG1TV[15:8] 0x058C TG1TVH TG1TV[7:0] 0x058D TG1TVL PTUCNT[15:8] 0x058E PTUCNTH PTUCNT[7:0] 0x058F PTUCNTL 0x0590 Reserved 0x0591 PTUPTRH PTUPTR[23:16] MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 811: L.10 0X05C0-0X05Ff Tim0
0x05C4 TIM0TCNTH TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 0x05C5 TIM0TCNTL TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 0x05C6 TIM0TSCR1 TSWAI TSFRZ TFFCA PRNT 0x05C7 TIM0TTOV TOV3 TOV2 TOV1 TOV0 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 812 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0x05D7 TIM0TC3L Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x05D8– Reserved 0x05DF 0x05E0 Reserved MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 813: L.11 0X0600-0X063F Adc0
0x0606 ADC0EIE IA_EIE CMD_EIE EOL_EIE Reserved TRIG_EIE LDOK_EIE R SEQAD_I CONIF_OI 0x0607 ADC0IE Reserved RSTAR_EI 0x0608 ADC0EiF IA_EIF CMD_EIF EOL_EIF Reserved TRIG_EIF LDOK_EIF R SEQAD_I CONIF_OI 0x0609 ADC0IF Reserved 0x060A ADC0CONIE_0 CON_IE[15:8] MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 814 0x0618 Reserved Reserved 0x0619 Reserved Reserved 0x061A Reserved Reserved 0x061B Reserved CMD_IDX[5:0] 0x061C ADC0CIDX 0x061D ADC0CBP_0 CMD_PTR[23:16] 0x061E ADC0CBP_1 CMD_PTR[15:8] 0x061F ADC0CBP_2 CMD_PTR[7:2] RES_IDX[5:0] 0x0620 ADC0RIDX 0x0621 ADC0RBP_0 RES_PTR[19:16] 0x0622 ADC0RBP_1 RES_PTR[15:8] MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 815: L.12 0X0640-0X067F Adc1
LDOK_EIE R SEQAD_I CONIF_OI 0x0647 ADC1IE Reserved RSTAR_EI 0x0648 ADC1EiF IA_EIF CMD_EIF EOL_EIF Reserved TRIG_EIF LDOK_EIF R SEQAD_I CONIF_OI 0x0649 ADC1IF Reserved 0x064A ADC1CONIE_0 CON_IE[15:8] 0x064B ADC1CONIE_1 CON_IE[7:1] EOL_IE 0x064C ADC1CONIF_0 CON_IF[15:8] MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 816 0x0659 Reserved Reserved 0x065A Reserved Reserved 0x065B Reserved CMD_IDX[5:0] 0x065C ADC1CIDX 0x065D ADC1CBP_0 CMD_PTR[23:16] 0x065E ADC1CBP_1 CMD_PTR[15:8] 0x065F ADC1CBP_2 CMD_PTR[7:2] RES_IDX[5:0] 0x0660 ADC1RIDX 0x0661 ADC1RBP_0 RES_PTR[19:16] 0x0662 ADC1RBP_1 RES_PTR[15:8] 0x0663 ADC1RBP_2 RES_PTR[7:2] MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 817: L.13 0X06A0-0X06Bf Gdu
0x06A3 GDUDSE GDHSIF[2:0] GDLSIF[2:0] GPHS[2:0] GOCS[1:0] GHHDS GLVLSS 0x06A4 GDUSTAT 0x06A5 GDUSRC GSRCHS[2:0] GSRCLS[2:0] 0x06A6 GDUF GSUF GHHDF GLVLSF GOCIF[1:0] GHHDIF GLVLSIF 0x06A7 GDUCLK1 GBOCD[4:0] GBODC[1:0] 0x06A8 GDUBCL GBCL[3:0] 0x06A9 GDUPHMUX GPHMX[1:0] MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 818: L.14 0X06C0-0X06Df Cpmu
VCOFRQ[1:0] SYNDIV[5:0] SYNR CPMU 0x06C5 REFFRQ[1:0] REFDIV[3:0] REFDIV CPMU 0x06C6 POSTDIV[4:0] POSTDIV LOCK UPOSC 0x06C7 CPMUIFLG RTIF LOCKIF OSCIF 0x06C8 CPMUINT RTIE LOCKIE OSCIE 0x06C9 CPMUCLKS PLLSEL PSTP CSAD OSCSEL1 OSCSEL OSCSEL0 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 819 APIR0 RESERVED 0x06D6 CPMUTEST3 0x06D7 CPMUHTTR HTOE HTTR3 HTTR2 HTTR1 HTTR0 CPMU 0x06D8 TCTRIM[4:0] IRCTRIM[9:8] IRCTRIMH CPMU 0x06D9 IRCTRIM[7:0] IRCTRIML 0x06DA CPMUOSC OSCE Reserved Reserved Reserved 0x06DB CPMUPROT PROT RESERVED 0x06DC CPMUTEST2 MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 820: L.15 0X06F0-0X06F7 Bats
SBR12 SBR11 SBR10 SBR9 SBR8 0x0701 SCI0BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0x0702 SCI0CR1 LOOPS SCISWAI RSRC WAKE BERRV 0x0700 SCI0ASR1 RXEDGIF BERRIF BKDIF 0x0701 SCI0ACR1 RXEDGIE BERRIE BKDIE MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 821 1 These registers are accessible if the AMAP bit in the SCISR2 register is set to zero. 2 These registers are accessible if the AMAP bit in the SCISR2 register is set to one. MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 822: L.17 0X0710-0X0717 Sci1
Bit 0 Name 0x0780 SPI0CR1 SPIE SPTIE MSTR CPOL CPHA SSOE LSBFE 0x0781 SPI0CR2 XFRW MODFEN BIDIROE SPISWAI SPC0 0x0782 SPI0BR SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 SPIF SPTEF MODF 0x0783 SPI0SR MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 823: L.19 0X0800–0X083F Can0
ABTRQ1 ABTRQ0 ABTAK2 ABTAK1 ABTAK0 0x0809 CAN0TAAK 0x080A CAN0TBSEL IDHIT2 IDHIT1 IDHIT0 0x080B CAN0IDAC IDAM1 IDAM0 0x080C Reserved 0x080D CAN0MISC BOHOLD R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 0x080E CAN0RXERR MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 824: L.20 0X0980-0X0987 Linphy0
Reserved Reserved Reserved Reserved Reserved R LPDTDIS 0x0983 LP0SLRM LPSLR1 LPSLR0 0x0984 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LPDT 0x0985 LP0SR 0x0986 LP0IE LPDTIE LPOCIE 0x0987 LP0IF LPDTIF LPOCIF MC9S12ZVM Family Reference Manual Rev. 1.3 Freescale Semiconductor...
Page 825 Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. MagniV is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2014 Freescale Semiconductor, Inc.

Freescale Semiconductor MC9S12ZVM series Reference Manual

Device Overview Mc9S12Zvm-Family

Chapter 1 Functional Differences between 1N95G and 0N95G Masksets

1.13.3.2 Control Loop Timing Considerations

Chapter 2

Chapter 5

Chapter 3

Chapter 16

4.3.2 Register Descriptions

Chapter 4

Chapter 6

Chapter 7

Chapter 8

Chapter 9

9.4 Memory Map and Register Deﬁnition

Chapter 10

Chapter 11

Chapter 18

Chapter 12

Chapter 13

Chapter 14

Chapter 15

Chapter 17

Chapter 19

Appendix A

Appendix E

Appendix B Appendix E

Appendix E

Appendix E

Appendix F

Appendix G

Appendix H

Appendix I

Appendix J

Appendix K

Appendix L

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Summary of Contents for Freescale Semiconductor MC9S12ZVM series