Freescale Semiconductor 56F800 User Manual page 574

Application:
SSI
arch.h: ArchIO.Ssi.TxControlReg
registers.h: ArchIO_Ssi_TxControlReg
Prescaler Range
Divide-by-eight prescaler is operational
Used to select the length of the data words*
SSI Transmit
Control Register
(STXCR)
SSI_BASE+$0x04
C
80
PSR
1
Prescaler is bypassed 0
WL
*See Table below.
Bits 15 14 13 12
Read
PSR WL1 WL0 DC4 DC3 DC2 DC1 DC0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0
Write
Reset 0 0 0 0
WL0 WL1
0
1
0
1
56F826/827 User Manual, Rev. 3
SSI Transmit Control Register (STXCR)
Frame Rate Divider Control DC
Control the divide ratio for programmable frame rate
dividers. The divide ratio ranges from 1 to 32 in
normal mode and from 2 to 32 in Network mode.
Specify the divide ratio of the prescale divider in the
SSI clock generator. A divide ratio from 1 to 256
(PM[7:0] = $00 to $FF) can be selected.
11 10 9 8 7
0 0 0 0 0
Number of Bits/Word
0 8
0 10
1 12
1 16
Date:
Programmer:
Sheet
Prescale Module Select PM
6 5 4 3 2 1
0 0 0 0 0 0
Freescale Semiconductor
5 of 9
0
0