Iic Bus Transmission Signals; Quick Reference - Freescale Semiconductor DSP56800E User Manual

For the Write transactions, the Master remains in transmitting mode and continues with the data
bytes transmission being continuously acknowledged by the Slave. The master finishes the
transaction either by releasing the bus by reverting to the Slave mode (generates the STOP
condition on the bus), or by re-starting a new transaction to a different slave (repeated START
condition). Slave may abort the Master Write transaction by not acknowledging a data byte
received - master is then required either to STOP or re-START the transaction.
For the Read transactions, the Master switches to a Receive mode immediately after the address
byte is transmitted and acknowledged by the Slave. Then the Master waits and acknowledges a
Slave transmission. The Master finishes the transaction by not-acknowledging the last byte
received from the Slave. Slave then releases the bus for the Master, which in-turn generates the
STOP or repeated START condition.
Figure 5-2. IIC Bus Transmission Signals
5.17.2

Quick Reference

This section defines the terms and formulas used later in Section 5.17.3.
Table 5-643. IIC Module Base Address
Module base address
MC56F800x MC56F801x MC56F802x/3x MC56F83xx
of / for
IIC (IIC_BASE) 0xF120 0xF0D0 N/A (different module) N/A
5-774 Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR