Pll Recommended Range Of Operation; Relationship Of Ipbus Clock And Zclk; On-Chip Clock States - Freescale Semiconductor 56F800 User Manual

Register Definitions
.
OSC_CLOCK
4MHz
EXTAL
Crystal
Prescaler
Osc.
div. by 1,2,4,6
XTAL
*Divided by (PLLDB + 1)
Figure 4-11. Relationship of IPBus Clock and ZCLK
Note: The maximum frequency of ZCLK operation is 80MHz correlating to a 40MHz IPBus
clock frequency.
The following table summarizes the state of the on-chip clocks in typical operating frequencies
during the various power-down modes.
Note: All peripherals, except the COP/Watchdog Timer and TOD, run off the IPBus clock
frequency. That frequency is the chip operating frequency divided by two. The
maximum frequency of operation is 80MHz, correlates to a 40MHz IPBus clock
frequency.

4.6.6 PLL Recommended Range of Operation

The PLL's Voltage Controlled Oscillator (VCO) has a characterized operating range extending
from 80MHz to 240MHz. The output of the PLL, F
wired, divide-by two, circuit yielding a 40MHz to 120MHz clock at the input of the postscaler.
The PLL is programmable via a divide-by n+1 register, capable of taking on values varying
between 1 and 128. PLLDB bits determine this value, referenced in
values of n, PLL lock time becomes an issue. It is recommended to avoid values of n resulting in
the VCO frequency greater than 240MHz or less than 80MHz.
16
PRESCALER
CLOCK
FOUT
PLLCID
FOUT/2
PLL
160MHz
PLLDB
Table 4-3. On-Chip Clock States
State ZCLK
Run 80MHz
Wait 80MHz
Stop Off
56F826/827 User Manual, Rev. 3
POSTSCALER
CLOCK
PLLCOD
Sync
Postscaler
MUX
div. by 1,2,4,8
ZSRC
Loss of
IRQ
Lock
Loss of
IRQ
Clock
IPBus_CLK
40MHz
40MHz
Off
in Figure 4-11
OUT
Section
Figure 4-13
COP
SIM
COP
IRQ
Peripheral
DSP
Core
Peripheral
en
IP_Bus
Bridge
Peripheral
div.by 2
Peripheral
is followed by a hard
4.6.2.5. For higher
shows the
Freescale Semiconductor