Freescale Semiconductor 56F800 Manuals

Manuals and User Guides for Freescale Semiconductor 56F800. We have 3 Freescale Semiconductor 56F800 manuals available for free PDF download: User Manual

Freescale Semiconductor 56F800 User Manual (630 pages)

16-bit Digital Signal Controllers

Brand: Freescale Semiconductor | Category: Controller | Size: 10 MB

Table of Contents
3
Pin Conventions
28
Chapter 1 56F826/827 Overview

29
- Introduction
  31
- 56800 Family Description
  32
- 56800 Core Description
  33
- 56800 Core Block Diagram
  33
  - Core Block Diagram
    34
  - Bus Block Diagram
    35
- Architectural Overview
  36
- 56F826 Description
  36
- 56F826 Features
  37
- 56F826 Benefits
  37
- 56F827 Description
  38
- 56F826 Block Diagram
  38
- 56F827 Features
  39
- 56F827 Benefits
  40
- 56F827 Block Diagram
  41
- 56F826/827 Features
  42
- Data Arithmetic Logic Unit (Data ALU)
  42
- Feature Matrix
  42
- Address Generation Unit (AGU)
  43
- Program Controller and Hardware Looping Unit
  43
- Bit Manipulation Unit (BMU)
  44
- Address and Data Buses
  44
  - Address and Data Buses
    45
- On-Chip Emulation (Once) Module
  46
- On-Chip Clock Synthesis (OCCS) Block
  46
- Oscillators
  46
- Phase Locked Loop (PLL)
  46
- Resets
  47
- Energy Supply Voltages
  47
- Ipbus Bridge
  47
- Memory Modules
  48
- Program Flash
  48
- Program RAM
  48
- Data Flash
  49
- Data RAM
  49
- 56F826/827 Peripheral Blocks
  49
- Peripheral Descriptions
  50
- External Memory Interface (EMI)
  50
- Programmable Chip Select
  50
- General-Purpose Input/Output Port (GPIO)
  51
- Serial Peripheral Interface (SPI)
  51
- Cop/Watchdog Timer and Modes of Operation Module
  51
- Jtag/Once Port
  52
- Quad Timer Module (TMR)
  52
- Analog-To-Digital Converter (ADC)
  53
- Serial Communications Interface (SCI)
  53
- Synchronous Serial Interface (SSI)
  53
- Time-Of-Day (TOD)
  54
- Peripheral Interrupts
  54
Chapter 2 Pin Descriptions

55
Chapter 3 Memory and Operating Modes

73
Chapter 4 On-Chip Clock Synthesis (OCCS)

107
- Introduction
  109
- Features
  109
- Block Diagram
  110
- Functional Description
  110
- OCCS Block Diagram
  110
- Reference Clock Sources
  110
- Timing
  112
- Pin Descriptions
  112
- Oscillator Inputs (XTAL, EXTAL)
  112
- External Crystal Design Considerations
  112
- Changing Clock Sources
  112
- Crystal Oscillator
  113
- External Crystal Oscillator Circuitexternal Clock Source
  113
- Connecting an External Clock Signal Using XTAL
  113
- Register Definitions
  114
- OCCS Register Map
  114
- OCCS Memory Map
  114
- OCCS Register Summary
  114
- PLL Control Register (PLLCR)
  115
- PLL Divide-By Register (PLLDB)
  117
- PLL Status Register (PLLSR)
  119
- CLKO Select Register (CLKOSR)
  120
- Clock Operation in the Power-Down Modes
  121
- PLL Recommended Range of Operation
  122
- Relationship of Ipbus Clock and ZCLK
  122
- On-Chip Clock States
  122
- Recommended Design Regions of OCCS PLL Operation
  123
- PLL Output Frequency Vs. Input Frequency
  123
- PLL Lock Time Specification
  124
- Lock Time Definition
  124
- PLL Frequency Lock Detector Block
  124
Chapter 5 Interrupt Controller (ITCN)

127
- Introduction
  129
- Interrupt Source
  129
- Interrupt Control
  129
- Priority Level Register (PLR)
  129
- Interrupt Exceptions
  129
- Interrupt Enable
  130
- Interrupt Priority Register (IPR)
  130
- Interrupt Programming
  131
- Interrupt Request Signals
  132
- Synchronous Serial Interface (SSI)
  132
- Serial Peripheral Interface (SPI0)
  132
- Serial Peripheral Interface (SPI1)
  132
- Extension to the Interrupt Controller
  132
- Serial Communications Interface (SCI0)
  133
- Serial Communications Interface (SCI1)
  133
- Serial Communications Interface (SCI2) (56F827 Only)
  133
- Analog-To-Digital Converter (ADC) (56F827 Only)
  133
- Timer Module (TMR A)
  133
- Time-Of-Day Module (TOD)
  133
- Combined Interrupt Requests for Port a (GPIOA)
  134
- Combined Interrupt Requests for Port B (GPIOB)
  134
- Combined Interrupt Requests for Port C (GPIOC)
  134
- Combined Interrupt Requests for Port D (GPIOD)
  134
- Combined Interrupt Requests for Port E (GPIOE) (56F826 Only)
  134
- Combined Interrupt Requests for Port F (GPIOF)
  134
- Combined Interrupt Requests for Port G (GPIOG) (56F827 Only)
  134
- Data Flash Interface Unit (DFIU)
  134
- Program Flash Interface Unit (PFIU)
  134
- Upper Program Flash Interface Unit (PFIU2) (56F827 Only)
  134
- ITCN Register Summary
  135
- Priority Level and Vector Assignments
  135
- Interrupt Vector Source and Addresses
  135
- Register Definitions
  137
- ITCN Memory Map
  137
- ITCN Register Summary
  137
- ITCN Register Map Summary
  138
- Register Definitions (GPR2-GPR15)
  139
- Group Priority Register 0 (GPR0)
  139
Chapter 6 Flash Memory Interface (FLASH)

143
- Introduction
  145
- Features
  145
- Flash Description
  146
- Truth Table
  146
- Program Flash (PFLASH)
  147
- IFREN Truth Table
  147
- Internal FLASH Timing Variables FLASH Timing Relationships
  147
- Program Flash Block Integration
  148
- Program Flash Main Block Organization
  148
- Program Flash Information Block Organization
  148
- Data Flash (DFLASH)
  149
- Data Flash Block Integration
  149
- Data Flash Main Block Organization
  149
- Data Flash Information Block Organization
  149
- Boot Flash (BFLASH) 56F826 Only
  150
- Program/Data/Boot Flash Interface Unit Features
  150
- Boot Flash Block Integration
  150
- Boot Flash Main Block Organization
  150
- Boot Flash Main Information Organization
  150
- Program/Data/Boot Flash Modes
  151
- Functional Description of the PFIU, PFIU2, DFIU and BFIU
  152
- Flash Programming and Erase Models
  152
- Intelligent Word Programming
  153
- Dumb Word Programming
  154
- Flash Program Cycle
  154
- Intelligent Erase Operation
  155
- FLASH Page Erase Cycle
  156
- Flash Mass Erase Cycle
  156
- Register Definitions
  157
- Flash Memory Map
  157
- FLASH Register Summary
  158
- FLASH Register Map Summary
  159
- IFREN Bit Effect
  160
- Flash Control Register (FIU_CNTL)
  160
- Flash Program Enable Register (FIU_PE)
  161
- Flash Erase Enable Register (FIU_EE)
  162
- Flash Address Register (FIU_ADDR)
  164
- Flash Interrupt Enable Register (FIU_IE)
  165
- Flash Interrupt Pending Register (FIU_IP)
  167
- Flash TRCV Limit Register (FIU_TRCVL)
  173
- Flash Interface Unit Timeout Registers
  174
- Reset
  174
- Interrupts
  174
Chapter 7 External Memory Interface (EMI)

175
- Introduction
  177
- External Memory Port Architecture
  177
- Pin Descriptions
  177
- Register Description
  178
- Bus Control Register (BCR)
  178
- EMI Register Summary
  178
- Programming WSP[3:0] and WSX[3:0] Bits for Wait States
  179
- Bus Operation (Read/Write-Zero Wait States)
  180
- Bus Operation (Read/Write-Four Wait States)
  180
- State of Pins in Different Processing States
  181
- Programmable Chip-Select (56F827 Only)
  182
- Chip Select Features (56F827 Only)
  182
- Programmability
  183
- Default Function of PCS0 and PCS1 (56F827 Only)
  183
- Register Definitions
  184
- EMI Memory Map
  184
- PCS Registers Summary
  185
- PCS Registers Map Summary
  186
- PCS Base Address Registers (PCSBAR0, ... ,PCSBAR7)
  186
- PCSBAR Encoding of the BLKSZ Field
  188
- PCS Option Registers (PCSOR0, PCSOR1,..., PCSOR7)
  189
- PCSOR Encoding of PCS PS / DS Functionality
  191
Chapter 8 General Purpose Input/Output (GPIO)

193
- Introduction
  195
- Features
  195
- Operating Modes
  195
- Chip Specific Configurations
  195
- GPIO Assignments
  196
- Block Diagram Showing GPIO Port Connections for 56F826
  197
- Block Diagram Showing GPIO Port Connections for 56F827
  198
- Bit-Slice View of the GPIO Logic
  199
- GPIO Interrupts
  200
- Edge Detector Circuit
  200
- Register Summary
  201
- GPIO Interrupt Assert Functionality
  201
- GPIO Registers with Reset Values
  201
- GPIO Programming Algorithms
  202
- GPIO Pull-Up Enable Functionality
  202
- Register Definitions
  204
- GPIO Memory Map
  204
- GPIO Register Summary
  205
- GPIO Pull-Up Enable Register (PUR)
  206
- GPIO Register Map Summary
  206
- Data Register (DR)
  207
- Data Direction Register (DDR)
  208
- Peripheral Enable Register (PER)
  208
- Interrupt Assert Register (IAR)
  209
- Interrupt Enable Register (IENR)
  209
- Interrupt Polarity Register (IPOLR)
  210
- GPIO Interrupt Pending Register (GPIO_IPR)
  211
- Interrupt Edge Sensitive Register (IESR)
  211
- GPIO Data Transfers between I/O Pad and Ipbus
  212
Chapter 9 Analog-To-Digital Converter (ADC)

213
- Introduction
  215
- Features
  215
- Block Diagram
  216
- Functional Description
  216
- ADC Block Diagram
  216
- Operating Modes
  217
- Normal Mode
  217
- Low Power Mode
  218
- STOP Mode
  218
- Timing
  219
- ADC Timing
  219
- Pin Descriptions
  220
- Analog Input Pins (AN[0-9])
  220
- Register Definitions
  221
- ADC Memory Map
  221
- ADC Register Summary
  222
- ADC Register Map Summary
  223
- ADC Control Register 1 (ADCR1)
  225
- ADC Control Register 2 (ADCR2)
  229
- Zero Crossing Control Register (ADZCC1 and ADZCC2)
  229
- ADC Channel List Registers (ADLST1-ADLST5)
  230
- ADC Input Conversion for Sample Bits
  231
- ADC Sample Disable Register (ADSDIS)
  233
- ADC Core
  233
- ADC Status Registers (ADSTAT1 and ADSTAT2)
  234
- ADC High and Low Limit Status Registers (ADHLSTAT and ADLLSTAT)
  237
- ADC Interrupts
  237
- ADC Zero Crossing Status Register (ADZCSTAT)
  238
- ADC Result Registers (ADRSLT0,...,ADRSLT9)
  239
- Result Register Data Manipulation
  240
- Low and High Limit Registers (ADLLMT0-9
  241
- ADC Offset Registers (ADOFS0-9)
  242
Chapter 10 Serial Communications Interface (SCI)

243
- Introduction
  245
- Features
  245
- Block Diagram
  246
- Functional Description
  246
- SCI Block Diagram
  246
- Data Frame Format
  247
- SCI Data Frame Formats
  247
- Example 8-Bit Data Frame Formats
  247
- Example 9-Bit Data Frame Formats
  247
- Baud Rate Generation
  248
- Transmitter
  248
- Example Baud Rates (Module Clock = 40Mhz)
  248
- SCI Transmitter Block Diagram
  249
- Receiver
  251
- SCI Receiver Block Diagram
  252
- Receiver Data Sampling
  253
- Start Bit Verification
  253
- Data Bit Recovery
  254
- Stop Bit Recovery
  254
- Slow Data
  255
- Fast Data
  256
- Special Operating Modes
  258
- Single-Wire Operation
  258
- Loop Functions
  258
- Loop Operation
  259
- Low-Power Options
  259
- Single-Wire Operation (LOOP = 1, RSRC = 1)
  259
- Loop Operation (LOOP = 1, RSRC = 0)
  259
- SCI Memory Map
  260
- Register Descriptions
  261
- SCI Baud Rate Register (SCIBR)
  261
- SCI Register Map
  261
- SCI Register Summary
  261
- SCI Control Register (SCICR)
  262
- SCI Status Register (SCISR)
  265
- SCI Data Register (SCIDR)
  267
- Clocks
  268
- Resets
  268
- Interrupts
  268
- SCI Interrupt Sources
  268
- Transmitter Empty Interrupt
  269
- Transmitter Idle Interrupt
  269
- Receiver Full Interrupt
  269
- Receive Error Interrupt
  269
Chapter 11 Serial Peripheral Interface (SPI)

271
- Introduction
  273
- Block Diagram
  274
- SPI Block Diagram
  274
- Operating Modes
  275
- Master Mode
  275
- Slave Mode
  276
- Full Duplex Master/Slave Connections
  276
- Pin Descriptions
  277
- Master In/Slave out (MISO)
  277
- Master Out/Slave in (MOSI)
  277
- External I/O Signals
  277
- Serial Clock (SCLK)
  278
- Slave Select (SS)
  278
- SPI I/O Configuration
  278
- Transmission Formats
  279
- Data Transmission Length
  279
- Data Shift Ordering
  279
- Clock Phase and Polarity Controls
  279
- Transmission Format When CPHA = 0
  280
- Transmission Format (CPHA = 0)
  280
- Transmission Format When CPHA = 1
  281
- CPHA/SS Timing
  281
- Transmission Initiation Latency
  282
- Transmission Format (CPHA = 1)
  282
- Transmission Data
  283
- Transmission Start Delay (Master)
  283
- SPRF/SPTE Interrupt Timing
  284
- Error Conditions
  285
- Overflow Error
  285
- Missed Read of Overflow Condition
  286
- Clearing SPRF When OVRF Interrupt Is Not Enabled
  286
- Mode Fault Error
  287
- Register Definitions
  288
- SPI Memory Map
  288
- SPI Status and Control Register (SPSCR)
  289
- SPI Register Map Summary
  289
- SPI Register Summary
  289
- SPI Master Baud Rate Selection
  292
- SPI Data Size Register (SPDSR)
  293
- Data Size
  293
- SPI Data Receive Register (SPDRR)
  294
- SPI Data Transmit Register (SPDTR)
  294
- Resets
  295
- Interrupts
  296
- SPI Interrupt Request Generation
  296
- SPI Interrupts
  296
Chapter 12 Synchronous Serial Interface (SSI)

297
- Introduction
  299
- SSI Architecture
  300
- SSI Input/Output Block Diagram
  300
- SSI Block Diagram
  301
- SSI Clocking
  302
- SSI Clock and Frame Sync Generation
  302
- SSI Transmit Clock Generator Block Diagram
  303
- SSI Transmit Frame Sync Generator Block Diagram
  303
- Programming Model
  304
- Register Definitions
  304
- SSI Memory Map
  304
- SSI Register Map Summary
  305
- SSI Register Summary
  305
- SSI Transmit Register (STX)
  306
- SSI Transmit FIFO Register
  306
- SSI Transmit Shift Register (TXSR)
  306
- Transmit Data Path (TSHFD=0)
  307
- Transmit Data Path (TSHFD=1)
  307
- SSI Receive Data Register (SRX)
  308
- SSI Receive FIFO Register
  308
- SSI Receive Shift Register (RXSR)
  308
- SSI Control/Status Register 1 (SCSR)
  309
- Receive Data Path (RSHFD = 0)
  309
- Receive Data Path (RSHFD = 1)
  309
- SSI Control/Status Register 1 (SCSR1)
  310
- SSI Receive Control Register 2 (SCR2)
  314
- SSI Receive Data Interrupts
  315
- SSI Transmit Data Interrupts
  315
- Frame Sync and Clock Pin Configuration
  317
- SSI Transmit and Receive Control Registers
  319
- SSI Receive Control Register (SRXCR)
  319
- SSI Data Word Lengths
  320
- SSI Bit Clock Equation
  321
- SSI Time Slot Register (STSR)
  322
- Chip Clock Rates as a Function of SSI
  322
  - Bit Clock Frequency and Prescale Modulus
    322
- SSI FIFO Control/Status Register (SFCSR)
  323
- SSI Time Slot Register (STSR)
  323
- Number of Data Words Available
  323
- Data FIFO Transmit
  324
- Receive FIFO Watermark
  324
- Transmit FIFO Empty Flag
  325
- TFWM Settings
  325
- SSI Option Register (SOR)
  326
- SSI Data and Control Pins
  327
- Asynchronous (SYN=0) SSI Configurations-Continuous Clock
  328
- Synchronous SSI Configuration-Continuous and Gated Clock
  329
- Configuration of the SSI Pins
  330
- Operating Modes
  331
- Serial Clock and Frame Sync Timing
  331
- SSI Operating Modes
  332
- Normal Mode
  333
- Normal Mode Timing-Continuous Clock
  334
- Network Mode
  335
- Normal Mode Timing-Gated Clock
  335
- Gated Clock Operation
  338
- Network Mode Timing-Continuous Clock
  338
- Reset and Initialization Procedure
  339
- SSI Control Bits Requiring Reset before Change
  340
Quad Timer Module (TMR)

341
- Introduction
  343
- 56F826 Counter/Timer Block Diagram
  344
- 56F827 Counter/Timer Block Diagram
  344
- Features
  345
- Pin Descriptions
  345
- Register Summary
  345
- Functional Description
  346
- Counting Options
  346
- External Inputs
  346
- OFLAG Output Signal
  346
- Master Signal
  347
- Counting Mode Definitions
  347
- Stop Mode
  347
- Count Mode
  347
- Edge Count Mode
  347
- Gated Count Mode
  347
- Quad Count Mode
  348
- Signed Count Mode
  348
- Triggered Count Mode
  348
- One-Shot Mode
  348
- Timing Diagram
  348
- Cascade Count Mode
  349
- Pulse Output Mode
  349
- Fixed-Frequency PWM Mode
  350
- Variable Frequency PWM Mode
  350
- Compare Registers Use
  350
- Capture Register Use
  351
- Register Definitions
  351
- TMR Memory Map
  351
- TMR Register Summary
  351
- TMR Register Map Summary
  352
- TMR Control Registers (CTRL)
  353
- TMR Status and Control Registers (SCR)
  356
- Capture Register Operation
  357
- TMR Compare Register 1 (CMP1)
  358
- TMR Compare Register 2 (CMP2)
  359
- TMR Capture Register (CAP)
  359
- TMR Load Register (LOAD)
  359
- TMR Hold Register (HOLD)
  360
- TMR Counter Register (CNTR)
  360
- TMR Comparator Load Register 1 (CMPLD1)-56F827 Only
  360
- TMR Comparator Load Register 2 (CMPLD2)-56F827 Only
  361
- TMR Comparator Status and Control Register (COMSCR)- 56F827 Only
  361
- Timer Group a Functionality
  362
- Timer Group a
  363
Chapter 13 Time-Of-Day (TOD)

365
- Introduction
  367
- Features
  367
- Counter Operation Block Diagram
  368
- Functional Description
  368
- Scaler
  368
- Time-Of-Day Counter Operation
  368
- Time Registers
  369
- Operating Modes
  369
- Stop Mode
  369
- TOD Alarms
  370
- Alarm Interrupt Flag and Outputs
  370
- One-Second Interrupt Flag and Outputs
  371
- Register Map
  371
- Register Definitions
  371
- TOD Registers
  371
- TOD Memory Map
  371
- TOD Register Summary
  372
- TOD Control Status (TODCS)
  373
- TOD Register Map Summary
  373
- TOD Clock Scaler (TODCSL)
  375
- TOD Seconds Counter (TODSEC)
  375
- TOD Seconds Alarm Register (TODSAL)
  376
- TOD Minutes Counter (TODMIN)
  376
- TOD Minutes Alarm Register (TODMAL)
  377
- TOD Hours Counter (TODHR)
  377
- TOD Hours Alarm Register (TODHAL)-Bits 4-0
  377
- TOD Days Counter (TODDAY)
  378
- TOD Days Alarm Register (TODDAL)
  378
Chapter 15 Reset, Low Voltage, Stop and Wait Operations

379
- Introduction
  381
- Sources of Reset
  381
- Power-On Reset and Low Voltage Interrupt
  382
- External Reset
  383
- POR and Low Voltage Detection
  383
- Computer Operating Properly (COP) Module
  384
- POR Vs. Low-Voltage Interrupts
  384
- COP Functional Description
  385
- Timeout Specifications
  385
- COP after Reset
  385
- COP in Wait Mode
  385
- COP in Stop Mode
  385
- Register Definitions
  386
- COP/SIM Memory Map
  386
- COP/SIM Register Summary
  386
- COP Control Register (COPCTL)
  387
- COP Timeout Register (COPTO)
  388
- COP Service Register (COPSRV)
  388
- Stop and Wait Mode Disable Function
  389
- Stop/Wait Disable Circuit
  389
- System Control Register (SYS_CNTL)
  390
- System Status Register (SYS_STS)
  391
- Memory Map Controls
  391
- Most Significant Half of JTAG ID (MSH_ID)
  392
- Least Significant Half of JTAG ID (LSH_ID)
  393
Chapter 16 Once Module

395
- Introduction
  397
- Features
  397
- Combined Jtag/Once Interface Overview
  399
- Jtag/Once Port Pin Descriptions
  399
- Jtag/Once Port Block Diagram
  399
- Jtag/Once Pin Descriptions
  400
- Once Module Architecture
  401
- 56F80X Once Block Diagram
  402
- Register Summary
  403
- Once Module Registers Accessed from the Core
  406
- Command, Status, and Control Registers
  407
- Once Shift Register (OSHR)
  407
- Once Command Register (OCMDR)
  408
- Register Select Encoding
  408
- Once Decoder (ODEC)
  409
- EX Bit Definition
  409
- GO Bit Definition
  409
- R/W Bit Definition
  409
- Once Control Register (OCR)
  410
- COP Timer Disable (COPDIS)-Bit 15
  410
- OCR Programming Model
  410
- Breakpoint Configuration Bits Encoding-Two Breakpoints
  411
- Event Modifier Selection
  413
- BS[1:0] Bit Definition
  415
- Breakpoint Programming with the BS[1:0] and BE[1:0] Bits
  416
- BE[1:0] Bit Definition
  416
- Once Status Register (OSR)
  417
- Once Breakpoint Control Register 2 (OBCTL2)
  417
- Core Status Bit Description
  418
- Breakpoint and Trace Registers
  419
- Once Breakpoint/Trace Counter Register (OCNTR)
  419
- Once Memory Address Latch Register (OMAL)
  420
- Once Breakpoint Address Register (OBAR)
  420
- Once Memory Address Comparator (OMAC)
  420
- Once Breakpoint and Trace Section
  420
- Once Breakpoint Address Register 2 (OBAR2)
  420
- Pipeline Registers
  421
- Once PAB Fetch Register (OPABFR)
  422
- Once PAB Decode Register (OPABDR)
  422
- Once PAB Execute Register (OPABER)
  423
- Once PAB Change-Of-Flow FIFO (OPFIFO)
  423
- Once PDB Register (OPDBR)
  423
- Once PAB Decode Register (OPABDR)
  423
- Once PDB Register (OPDBR)
  424
- Once PGDB Register (OPGDBR)
  425
- Once PDGB Register (OPGDBR)
  425
- Once FIFO History Buffer
  426
- Once FIFO History Buffer
  427
- Breakpoint 2 Architecture
  428
- Breakpoint Configuration
  429
- Breakpoint and Trace Counter Unit
  429
- Once Breakpoint Programming Model
  430
- Breakpoint 1 Unit
  431
- Breakpoint 2 Unit
  432
- Programming the Breakpoints
  433
- Once Trace Logic Operation
  434
- The Debug Processing State
  435
- Once Normal, Debug, and Stop Modes
  436
- Entering Debug Mode
  437
- Accessing the Once Module
  439
- Primitive JTAG Sequences
  439
- Entering the JTAG Test-Logic-Reset State
  439
- Entering the JTAG Test-Logic-Reset State
  440
- Holding TMS High to Enter Test-Logic-Reset State
  440
- Loading the JTAG Instruction Register
  441
- Bit Order for Jtag/Once Shifting
  441
- Loading DEBUG_REQUEST
  442
- Accessing a JTAG Data Register
  443
- Shifting Data through the BYPASS Register
  443
- Once Shifter Selection State Diagram
  445
- Executing a Once Command by Reading the OCR
  446
- Executing a Once Command by Writing the OCNTR
  447
- OSR Status Polling
  448
- JTAGIR Status Polling
  449
- Once Module Low Power Operation
  450
- Resetting the Chip Without Resetting the Once Unit
  450
Chapter 17 JTAG Port

453
- Introduction
  455
- Features
  455
- Pin Descriptions
  456
- JTAG Pin Descriptions
  456
- JTAG Port Architecture
  457
- JTAG Block Diagram
  457
- Register Summary
  458
- JTAG Instruction Register (JTAGIR) and Decoder
  458
- JTAGIR Register
  459
- JTAGIR Encodings
  459
- JTAGIR Bypass
  460
- JTAG Chip Identification (CID) Register
  463
- JTAG Chip Identification Register (CID)
  463
- Chip Identification Register Configuration
  464
- JTAG D Codes
  464
  - JTAG ID Code Is Expressed in Hex Form, and Is Calculated as (Version, Design_Center, Part_Number, Manufacturer_Id,%1)
    464
- Device ID Register Bit Assignment
  464
- JTAG Boundary Scan Register (BSR)
  465
- Boundary Scan Register for 56F826 (BSR)
  465
- BSR Contents for 56F80X
  465
- JTAG Bypass Register (JTAGBR)
  475
- TAP Controller
  476
- JTAG Bypass Register (JTAGBR)
  476
- TAP Controller State Diagram
  477
- 56F826/827 Restrictions
  478
Appendix A Glossary

479
- A.1 Glossary
  481
Appendix B Programmer's Sheets

495
- Introduction
  497
- Instruction Set Summary
  497
- Interrupt, Vector, and Address Tables
  506
- Programmer's Sheets
  507
- List of Programmer's Sheets
  507
- Flash T NVH1 Limit Register (FIU_TNVH1L)
  534

Freescale Semiconductor 56F800 User Manual (56 pages)

Evaluation Module 16-bit Digital Signal Controllers

Brand: Freescale Semiconductor | Category: Computer Hardware | Size: 0 MB

Table of Contents
3
Preface
9
Audience
9
Organization
9
Suggested Reading
9
Notation Conventions
10
Definitions, Acronyms, and Abbreviations
11
References
12
Chapter 1 Introduction

13
Chapter 2 Technical Summary

17

Freescale Semiconductor 56F800 User Manual (56 pages)

Evaluation Module, 16-bit Digital Signal Controllers

Brand: Freescale Semiconductor | Category: Control Unit | Size: 0 MB

Table of Contents
3
Preface
9
Audience
9
Organization
9
Suggested Reading
9
Notation Conventions
10
Definitions, Acronyms, and Abbreviations
11
References
12
Chapter 1 Introduction

13
Chapter 2 Technical Summary

17

Freescale Semiconductor Categories

Motherboard Computer Hardware Microcontrollers Control Unit Controller

More Freescale Semiconductor Manuals

Freescale Semiconductor 56F800 Manuals

Freescale Semiconductor 56F800 User Manual (630 pages)

Table of Contents

Chapter 1 56F826/827 Overview

Chapter 2 Pin Descriptions

Chapter 3 Memory and Operating Modes

Chapter 4 On-Chip Clock Synthesis (OCCS)

Chapter 5 Interrupt Controller (ITCN)

Chapter 6 Flash Memory Interface (FLASH)

Chapter 7 External Memory Interface (EMI)

Chapter 8 General Purpose Input/Output (GPIO)

Chapter 9 Analog-To-Digital Converter (ADC)

Chapter 10 Serial Communications Interface (SCI)

Chapter 11 Serial Peripheral Interface (SPI)

Chapter 12 Synchronous Serial Interface (SSI)

Quad Timer Module (TMR)

Chapter 13 Time-Of-Day (TOD)

Chapter 15 Reset, Low Voltage, Stop and Wait Operations

Chapter 16 Once Module

Chapter 17 JTAG Port

Appendix A Glossary

Appendix B Programmer's Sheets

Freescale Semiconductor 56F800 User Manual (56 pages)

Table of Contents

Chapter 1 Introduction

Chapter 2 Technical Summary

Freescale Semiconductor 56F800 User Manual (56 pages)

Table of Contents

Chapter 1 Introduction

Chapter 2 Technical Summary

Related Products

Freescale Semiconductor Categories