Freescale Semiconductor 56F800 User Manual page 488

16-bit digital signal controllers

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Table of Contents

Program Enable

Parity Enable Bit

Peripheral Enable Register

Parity Error Flag

Program Flash Interface Unit

Program Flash

Peripheral Global Data Bus

Phase Locked Loop

PLL Clock In Divide

PLL Clock Out Divide

PLL Divide-by

PLL Control Register

PLL Power Down

PLL Status Register

Priority Level Register

PWM Channel Control Register

PWM Configuration Register

PWM Counter Register

PWM Control Register

PWM Deadtime Register

PWM Disable Mapping Registers

PWM Fault Control Register

PWM Fault Status Acknowledge

PWM Output Control Register

PWM Port Register

Power on Reset

Program Cycle

Processor Status Register

Peripheral Test Mode

56F826/827 Peripheral User Manual, Rev. 3

Freescale Semiconductor

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