56800 Family Description - Freescale Semiconductor 56F800 User Manual

56800 Family Description

• Fuel management systems
• Voice enabled appliances
• Cable test equipment
• Electric energy meter with embedded power line modem
• Underwater acoustics
• Glass breakage detection and security systems
• Traffic light control
• Identification tag readers
• Servo drives
1.2 56800 Family Description
The 56800 core is based on a Harvard-style architecture consisting of three execution units
operating in parallel. The Microcontroller Unit (MCU) style programming model and optimized
instruction set provide straightforward generation of efficient, compact, and control code. The
instruction set is highly efficient for C-compilers, facilitating rapid development of optimized
control applications.
The 56800 chips support program execution from either internal or external memories, providing
two external dedicated interrupt lines and up to 32-General-Purpose Input/Output (GPIO) lines.
The controller includes Program Flash and Data Flash, each programmable through the Joint Test
Action Group (JTAG) port, with Program RAM and Data RAM. The controller also supports
program execution for external memory. The 56800 core is capable of accessing two data
operands from the on-chip Data RAM per instruction cycle.
The controller also provides a full set of standard programmable peripherals: Serial
Communications Interface (SCI), Serial Peripheral Interface (SPI), and an additional Quad Timer
(TMR). Any of these interfaces can be used as a General-Purpose In/Out (GPIO) if those
functions are not required. An internal Interrupt Controller and dedicated GPIO, are also included
on some of the parts.
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56F826/827 User Manual, Rev. 3
Freescale Semiconductor