56F827 Description; 56F826 Block Diagram - Freescale Semiconductor 56F800 User Manual

56F827 Description

Program Memory
Quad Timer
32252 x 16 Flash
or
512 x 16 SRAM
4
GPIO
2048 x 16 Flash
2048 x 16 Flash
SSI
4096 x 16 SRAM
or
6 GPIO
SCI0 & SCI1
or
SPI0
4
SPI1
or
GPIO
tion-Specific
4
Memory &
Dedicated
GPIO Peripherals
16
1.6 56F827 Description
The 56F827 is a member of the Harvard-style architecture 56800 core-based family of devices. It
combines the processing power of a controller and the functionality of a microcontroller with a
flexible set of peripherals, creating an extremely cost-effective solution for general-purpose
applications. Because of its low cost, configuration flexibility, and compact program code, the
56F827 is well-suited for many applications. Two data operands per instruction cycle can be
accessed from the on-chip Data RAM per instruction cycle. The 56F827 incorporates easy
customer field-programmable software routines used to develop the main program. The 56F827
is well-suited for many applications such as:
• Noise suppression
• Identification tag readers
• Sonic/subsonic detectors
• Security access devices
• Remote metering
10
EXTBOOT
RESET IRQB
IRQA
TOD
Timer
Program Controller
Interrupt
and
Controller
Hardware Looping Unit
PAB
PDB
Boot Flash
XDB2
CGDB
Data Memory
XAB1
XAB2
COP
RESET
COP/
Watchdog
Applica-
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
Figure 1-3. 56F826 Block Diagram
56F826/827 User Manual, Rev. 3
V V
V V
DDIO SSIO
DD SS
6
3 3 4 4
JTAG/ Low Voltage Supervisor
OnCE
Port
Data ALU
Address
16 x 16 + 36 → 36-Bit MAC
Generation
Three 16-bit Input Registers
Unit
Two 36-bit Accumulators
16-Bit
56800
Core
INTERRUPT IPBB
CONTROLS CONTROLS
16 16
External
IPBus Bridge
Bus
Interface
(IPBB)
Unit
V V
DDA SSA
Analog Reg
Bit
Manipulation
Unit
CLKO
PLL
XTAL
Clock Gen
.
EXTAL
External
A[00:15]
Address Bus
or
Switch
16
GPIO
External
D[00:15]
Data Bus
16
Switch
PS Select
Bus
DS Select
Control
WR Enable
RD Enable
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