Freescale Semiconductor 56F800 User Manual page 90

On-Chip Peripheral Memory Map
Table 3-17. 56F826 Boot Flash Interface Unit Registers Address Map
Register
Abbreviation
BFIU_IP
BFIU_CKDIVISOR
BFIU_TERASEL
BFIU_TMEL
BFIU_TNVSL
BFIU_TPGSL
BFIU_TPROGL
BFIU_TNVHL
BFIU_TNVHL1
BFIU_TRCVL
Table 3-18. Interrupt Controller Registers Address Map (
Register
Abbreviation
ITCN_GPR0
ITCN_GPR1
ITCN_GPR2
ITCN_GPR3
ITCN_GPR4
ITCN_GPR5
ITCN_GPR6
ITCN_GPR7
ITCN_GPR8
ITCN_GPR9
ITCN_GPR10
ITCN_GPR11
ITCN_GPR12
ITCN_GPR13
ITCN_GPR14
ITCN_GPR15
18
(
BFIU_BASE = $1080
Register Description
Boot Flash Interrupt Pending Register
Boot Flash Clock Divisor Register
Boot Flash Terase Limit Register
Boot Flash TME Limit Register
Boot Flash TNVS Limit Register
Boot Flash TPGS Limit Register
Boot Flash TPROG Limit Register
Boot Flash TNVH Limit Register
Boot Flash TNVH1 Limit Register
Boot Flash TRCV Limit Register
Register Description
Group Priority Register 0
Group Priority Register 1
Group Priority Register 2
Group Priority Register 3
Group Priority Register 4
Group Priority Register 5
Group Priority Register 6
Group Priority Register 7
Group Priority Register 8
Group Priority Register 9
Group Priority Register 10
Group Priority Register 11
Group Priority Register 12
Group Priority Register 13
Group Priority Register 14
Group Priority Register 15
56F826/827 User Manual, Rev. 3
)
Address Offset Base Address
$7
$8
$9
$A
$B
$C
$D
$E
$F
$10
ITCN_BASE = $1100
Address Offset Base Address
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
$E
$F
Freescale Semiconductor
BFIU_BASE
BFIU_BASE
BFIU_BASE
BFIU_BASE
BFIU_BASE
BFIU_BASE
BFIU_BASE
BFIU_BASE
BFIU_BASE
BFIU_BASE
)
ITCN_BASE
ITCN_BASE
ITCN_BASE
ITCN_BASE
ITCN_BASE
ITCN_BASE
ITCN_BASE
ITCN_BASE
ITCN_BASE
ITCN_BASE
ITCN_BASE
ITCN_BASE
ITCN_BASE
ITCN_BASE
ITCN_BASE
ITCN_BASE