Core Block Diagram - Freescale Semiconductor 56F800 User Manual

56800 Core Description
Program
Controller
SR OMR
LA LC
PC HWS
Bus and Bit
Manipulation
Unit
OnCE
The Program Controller, AGU and Data ALU each contain a discrete register set and control
logic so each can operate independently and in parallel with the others. Likewise, each functional
unit interfaces with other units, with memory, and with memory-mapped peripherals over the
core's internal address and data buses, illustrated in
6
AGU
M01 N
Instr. Decoder
and
Interrupt Unit
Data
Limiter
ALU
Y1 Y0 X0 A2 A1 A0
Figure 1-1. 56800 Core Block Diagram
56F826/827 User Manual, Rev. 3
SP
R0
MOD.
+/-
ALU
R1
R2
R3
XAB1
XAB2
PAB
PDB
CGDB
XDB2
PGDB
B2 B1 B0
MAC
and
ALU
Figure 1-2.
Program
Memory
Data
Memory
External
Bus
Interface
IPBus
Interface
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