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Freescale Semiconductor

MPC5604B/C Microcontroller

Reference Manual

This is the MPC5604B/C Reference Manual set consisting of the following files:

•

MPC5604B/C Reference Manual Addendum (MPC5604B/CRMAD), Rev. 2

•

MPC5604B/C Reference Manual (MPC5604B/CRM), Rev. 8

© Freescale Semiconductor, Inc., 2013. All rights reserved.

MPC5604BCRM

Rev. 8.2, 09/2013

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Page 1 Freescale Semiconductor MPC5604BCRM Rev. 8.2, 09/2013 MPC5604B/C Microcontroller Reference Manual This is the MPC5604B/C Reference Manual set consisting of the following files: • MPC5604B/C Reference Manual Addendum (MPC5604B/CRMAD), Rev. 2 • MPC5604B/C Reference Manual (MPC5604B/CRM), Rev. 8 © Freescale Semiconductor, Inc., 2013. All rights reserved.
Page 2 Revision History ......4 items are grouped by revision. Please check our website at http://www.freescale.com/powerarchitecture for the latest updates. The current version available of the MPC5604B/C Microcontroller Reference Manual is Revision 8.1. © Freescale Semiconductor, Inc., 2013. All rights reserved.
Page 3 APIVAL to the RTC clock, and APIVAL + 1 cycles for subsequent occurrences. After that, interrupts are periodic in nature. Because of synchronization issues, the minimum supported value of APIVAL is 4. MPC5604BRMAD, Rev. 2 Freescale Semiconductor...
Page 4 16 MHz fast internal RC oscillator, but the conversion still requires a 16 MHz clock (an 8 MHz clock is not fast enough). In all other cases, the ADC should use the clock divided by two internally. MPC5604BRMAD, Rev. 2 Freescale Semiconductor...
Page 5 Table 3. Revision History Table Rev. Number Substantive Changes Date of Release Add a note below Table 27-4, “CFlash TestFlash Structure” 09/2013 Initial release. 05/2012 MPC5604BRMAD, Rev. 2 Freescale Semiconductor...
Page 6 Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer...
Page 7 MPC5604BCRM Rev. 8.1, 05/2012 MPC5604B/C Microcontroller Reference Manual by: Microcontroller Solutions Group This is the MPC5604B/C Reference Manual set consisting of the following files: • MPC5604B/C Reference Manual Addendum (MPC5604B/CRMAD), Rev. 1 • MPC5604B/C Reference Manual (MPC5604B/CRM), Rev. 8 © Freescale Semiconductor, Inc., 2012. All rights reserved.
Page 8 MPC5604BCRM. For convenience, the addenda items are grouped by revision. Please check our website at http://www.freescale.com/powerarchitecture for the latest updates. The current version available of the MPC5604B/C Microcontroller Reference Manual is Revision 8. © Freescale Semiconductor, Inc., 2012. All rights reserved.
Page 9 In this case the latest message is always available to the application. • If the buffer lock function is enabled (LINCR1[RBLM] = 0) the most recent message is discarded and the previous message is available in the buffer. MPC5604B Reference Manual Errata, Rev. 1 Freescale Semiconductor...
Page 10 Note: The auto-clock-off feature cannot operate when the digital interface runs at the same rate as the analog interface. This means that when MCR.ADCCLKSEL = 1, the analog clock will not shut down in IDLE mode. MPC5604B Reference Manual Errata, Rev. 1 Freescale Semiconductor...
Page 11 Revision History Table 2 provides a revision history for this reference manual addendum document. Table 2. Revision History Table Rev. Number Substantive Changes Date of Release • Initial release. 05/2012 MPC5604B Reference Manual Errata, Rev. 1 Freescale Semiconductor...
Page 12 MPC5604B/C Microcontroller Reference Manual Devices Supported: MPC5602B MPC5602C MPC5603B MPC5603C MPC5604B MPC5604C MPC5604BCRM Rev. 8 5 May 2011 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 13 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 14: Table Of Contents
Preface Overview ............................19 Audience ............................19 Guide to this reference manual ......................19 Register description conventions ....................22 References ............................23 How to use the MPC5604B documents ..................23 1.6.1 The MPC5604B document set ..................23 1.6.2 Reference manual content ....................24 Using the MPC5604B ........................25 1.7.1 Hardware design ......................25...
Page 15 Register description ......................104 6.7.6 Functional description ....................107 6.7.7 Recommendations ......................110 Clock monitor unit (CMU) ......................110 6.8.1 Introduction ........................110 6.8.2 Main features ........................ 111 6.8.3 Block diagram ......................111 6.8.4 Functional description ....................112 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 16 Overview ........................187 9.1.2 Features .........................188 9.1.3 Modes of operation .......................189 External signal description ......................190 Memory map and register definition .....................190 9.3.1 Register descriptions ....................192 Functional Description ........................203 9.4.1 Reset State Machine .....................203 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 17 Wakeup Unit (WKPU) 12.1 Overview ............................229 12.2 Features ............................231 12.3 External signal description ......................231 12.4 Memory map and register description ...................231 12.4.1 Memory map ........................231 12.4.2 NMI Status Flag Register (NSR) ..................232 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 18 Sample register n (n = 0..11) ..................255 14.4 Functional description ........................256 14.4.1 Enabling/Disabling the CAN sampler ................256 14.4.2 Baud rate generation .....................257 Chapter 15 e200z0h Core 15.1 Overview ............................261 15.2 Microarchitecture summary ......................261 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 19 Crossbar Switch (XBAR) 17.1 Introduction ...........................301 17.2 Block diagram ..........................301 17.3 Overview ............................302 17.4 Features ............................302 17.5 Modes of operation ........................302 17.5.1 Normal mode ........................302 17.5.2 Debug mode ........................302 17.6 Functional description ........................302 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 20 General purpose input and output pads (GPIO) ............350 19.6.3 External interrupts ......................351 19.7 Pin muxing ............................352 Chapter 20 Inter-Integrated Circuit Bus Controller Module (I 20.1 Introduction ...........................355 20.1.1 Overview ........................355 20.1.2 Features .........................355 20.1.3 Block diagram ......................356 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 21 Memory map ........................383 21.8 Functional description ........................409 21.8.1 UART mode ........................409 21.8.2 LIN mode ........................411 21.8.3 8-bit timeout counter ....................419 21.8.4 Interrupts ........................421 Chapter 22 FlexCAN 22.1 Introduction ...........................423 22.1.1 Overview ........................423 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 22 Memory map ........................474 23.5.2 DSPI Module Configuration Register (DSPIx_MCR) ..........475 23.5.3 DSPI Transfer Count Register (DSPIx_TCR) ..............478 23.5.4 DSPI Clock and Transfer Attributes Registers 0–5 (DSPIx_CTARn) ......478 23.5.5 DSPI Status Register (DSPIx_SR) ................486 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 23 24.5 Periodic Interrupt Timer (PIT) ......................580 24.5.1 Introduction ........................580 24.5.2 Features .........................581 24.5.3 Signal description ......................581 24.5.4 Memory map and register description ................581 24.5.5 Functional description ....................586 24.5.6 Initialization and application information ..............587 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 24 Event Configuration Registers (CTU_EVTCFGRx) (x = 0...63) .........632 26.5 Functional description ........................633 26.5.1 Channel value .......................635 Chapter 27 Flash Memory 27.1 Introduction ...........................639 27.2 Main features ..........................640 27.3 Block diagram ..........................640 27.4 Functional description ........................641 27.4.1 Module structure ......................641 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 25 28.4 SRAM ECC mechanism ........................735 28.4.1 Access timing .......................736 28.4.2 Reset effects on SRAM accesses ..................737 28.5 Functional description ........................737 28.6 Initialization and application information ..................737 Chapter 29 Register Protection 29.1 Introduction ...........................741 29.2 Features ............................741 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 26 32.4 Features ............................788 32.5 Modes of operation ........................788 32.5.1 Reset ..........................788 32.5.2 IEEE 1149.1-2001 defined test modes .................788 32.6 External signal description ......................789 32.7 Memory map and register description ...................790 32.7.1 Instruction Register ......................790 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 27 33.7.5 Nexus Messaging ......................817 33.7.6 EVTO Sharing ......................817 33.7.7 Debug Mode Control ....................818 33.7.8 Ownership Trace ......................818 Appendix A Register Map Appendix B Revision History Changes between revisions 7 and 8 ...................903 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 28 Changes between revisions 5 and 7 ...................908 Changes between revisions 4 and 5 ....................910 Changes between revisions 2 and 4 ....................911 Changes between revisions 1 and 2 ....................920 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 29 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 30: Overview
This manual is intended for system software and hardware developers and applications programmers who want to develop products with the MPC5604B device. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the Power Architecture.
Page 31 System Integration Unit Lite How to configure the pins or ports for input or output Ports (SIUL) functions including external interrupts and DSI serialization. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 32 (with ECC), block sizes and the flash memory port configuration, including wait states, line buffer configuration and pre-fetch control. Static RAM (SRAM) Details the structure of the SRAM (with ECC). There are no user configurable registers associated with the SRAM. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 33: Revision History
Summarizes the changes between each successive Revision history revision of this reference manual information Register description conventions The register information for MPC5604B is presented in: • Memory maps containing: — An offset from the module’s base address — The name and acronym/abbreviation of each register —...
Page 34: References
Write 1 to clear field (field will always read 0) Figure 1-1. Register figure conventions The numbering of register bits and fields on MPC5604B is as follows: • Register bit numbers, shown at the top of each figure, use the standard Power Architecture bit ordering (0, 1, 2, ...) where bit 0 is the most significant bit (MSB).
Page 35: Reference Manual Content
There are special cases where a chapter may describe module functionality and some integration features for convenience — for example, the microcontroller input/output (SIUL) module. Integration and functional content is provided in the manual as shown in Table 1-2. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 36: Using The Mpc5604B
Using the MPC5604B There are many different approaches to designing a system using the MPC5604B so the guidance in this section is provided as an example of how the documents can be applied in this task.
Page 37: Input/Output Pins
The MPC5604B internal logic operates from 1.2 V (nominal) supplies that are normally supplied by the on-chip voltage regulator from a 5 V or 3.3 V supply. The 3.3–5 V (±10%) supply is also used to supply the input/output pins on the MCU.
Page 38: Software Design
Individual register settings can be protected from unintended writes using the features of the Register Protection module. The protected registers are shown in Chapter 29, Register Protection. Other integration functionality is provided by the System Status and Configuration Module (SSCM). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 39 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 40: The Mpc5604B Microcontroller Family
The MPC5604B microcontroller family ® The MPC5604B represents a new generation of 32-bit microcontrollers based on the Power Architecture It belongs to an expanding family of automotive-focused products targeted at addressing the next wave of body electronics applications within the vehicle.
Page 41 Table 2-3. MPC5604B device comparison Device Feature MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC560 02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL 4BxMG e200z0h Execution Static –...
Page 42 Table 2-3. MPC5604B device comparison (continued) Device Feature MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC560 02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL 4BxMG...
Page 43: Block Diagram
2.2.2 Block diagram Figure 2-1 shows a top-level block diagram of the MPC5604B family. SRAM Code Flash Data Flash JTAG 48 KB 512 KB 64 KB JTAG port Instructions Nexus port SRAM Flash e200z0h (Master) Nexus controller controller Data Nexus 2+...
Page 44: Chip-Level Features
Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus • Device/board boundary scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) • On-chip voltage regulator (VREG) for regulation of input supply for all internal levels MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 45: Packages
208 MAPBGA, 1mm ball pitch, 17mm x 17mm outline development package Developer support The MPC5604B MCU tools and third-party developers are similar to those used for the Freescale MPC5500 product family, offering a widespread, established network of tool and software vendors. It also features a high-performance Nexus debug interface.
Page 46 Chapter 3 Memory Map Table 3-1 shows the memory map for the MPC5604B. All addresses on the device, including those that are reserved, are identified in the table. The addresses represent the physical addresses assigned to each IP block. Table 3-1. MPC5604B memory map...
Page 47 Table 3-1. MPC5604B memory map (continued) Start address End address Size (KB) Region name 0xC3F9_4000 0xC3F9_7FFF WKPU 0xC3F9_8000 0xC3F9_FFFF Reserved 0xC3FA_0000 0xC3FA_3FFF eMIOS_0 0xC3FA_4000 0xC3FA_7FFF eMIOS_1 0xC3FA_8000 0xC3FD_7FFF Reserved 0xC3FD_8000 0xC3FD_BFFF SSCM 0xC3FD_C000 0xC3FD_FFFF MC_ME 0xC3FE_0000 0xC3FE_3FFF MC_CGM 0xC3FE_4000 0xC3FE_7FFF...
Page 48 Table 3-1. MPC5604B memory map (continued) Start address End address Size (KB) Region name 0xFFF4_4000 0xFFF4_7FFF Reserved 0xFFF4_8000 0xFFF4_BFFF INTC 0xFFF4_C000 0xFFF8_FFFF Reserved 0xFFF9_0000 0xFFF9_3FFF DSPI_0 0xFFF9_4000 0xFFF9_7FFF DSPI_1 0xFFF9_8000 0xFFF9_BFFF DSPI_2 0xFFF9_C000 0xFFFB_FFFF Reserved 0xFFFC_0000 0xFFFC_3FFF FlexCAN_0 0xFFFC_4000 0xFFFC_7FFF...
Page 49 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 50: Introduction
PA[3] VSS_HV PB[15] VDD_HV PB[14] VSS_HV 64 LQFP PB[13] RESET PB[12] VSS_LV Top view PB[11] VDD_LV PB[7] VDD_BV PB[6] PC[10] PB[0] PB[5] PB[1] VDD_HV_ADC PC[6] VSS_HV_ADC Figure 4-1. MPC560xB LQFP 64-pin configuration MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 51 VDD_LV PD[10] VDD_BV PD[9] PC[11] PB[7] PC[10] PB[6] PB[0] PB[5] PB[1] VDD_HV_ADC PC[6] VSS_HV_ADC Note: Availability of port pin alternate functions depends on product selection. Figure 4-3. LQFP 100-pin configuration (top view) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 52 PG[6] PD[10] PB[0] PD[9] PB[1] PB[7] PF[9] PB[6] PF[8] PB[5] PF[12] VDD_HV_ADC PC[6] VSS_HV_ADC Note: Availability of port pin alternate functions depends on product selection. Figure 4-4. LQFP 144-pin configuration (top view) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 53: Pad Configuration During Reset Phases
RESET pad is driven low. This is pull-up only after PHASE2 reset completion. • JTAG pads (TCK, TMS and TDI) are pull-up whilst TDO remains tristate. • Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 54: Voltage Supply Pins
1. See the I/O pad electrical characteristics in the device datasheet for details. 2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see PCR.SRC Section 19.5.3.8, “Pad Configuration Registers (PCR0–PCR122)). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 55: System Pins
Pin numbers apply to both the MPC560xB and MPC560xC packages. 208 MAPBGA available only as development package for Nexus2+ See the relevant section of the datasheet Functional ports The functional port pins are listed in Table 4-3. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 56 SIUL Tristate 119 D11 E0UC[6] eMIOS_0 — — — — — — — EIRQ[1] SIUL PA[7] PCR[7] GPIO[7] SIUL Tristate 104 D16 E0UC[7] eMIOS_0 LIN3TX LINFlex_3 — — — — EIRQ[2] SIUL MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 57 — — SIN_0 DSPI0 PA[13] PCR[13] GPIO[13] SIUL Tristate SOUT_0 DSPI_0 — — — — — — PA[14] PCR[14] GPIO[14] SIUL Tristate SCK_0 DSPI_0 CS0_0 DSPI_0 — — — — EIRQ[4] SIUL MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 58 GPIO[21] SIUL Tristate — — — — — — — — — — — GPI[1] PB[6] PCR[22] GPIO[22] SIUL Tristate — — — — — — — — — — — GPI[2] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 59 — ANS[3] PB[12] PCR[28] GPIO[28] SIUL Tristate — E0UC[4] eMIOS_0 — — — CS1_0 DSPI_0 — ANX[0] PB[13] PCR[29] GPIO[29] SIUL Tristate — E0UC[5] eMIOS_0 — — — CS2_0 DSPI_0 — ANX[1] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 60 — — — — CAN1RX FlexCAN_1 — CAN4RX FlexCAN_4 — EIRQ[6] SIUL PC[4] PCR[36] GPIO[36] SIUL Tristate — — — — — — — — — — SIN_1 DSPI_1 — CAN3RX FlexCAN_3 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 61 SIUL Tristate CAN1TX FlexCAN_1 CAN4TX FlexCAN_4 MA[1] PC[11] PCR[43] GPIO[43] SIUL Tristate — — — — — — — — — — — — CAN1RX FlexCAN_1 — CAN4RX FlexCAN_4 — WKUP[5] WKPU MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 62 Tristate — — — — — — — — — — — — GPI[6] PD[3] PCR[51] GPIO[51] SIUL Tristate — — — — — — — — — — — — GPI[7] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 63 Tristate — — — — — — — — — — — — GPI[14] PD[11] PCR[59] GPIO[59] SIUL Tristate — — — — — — — — — — — — GPI[15] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 64 PE[2] PCR[66] GPIO[66] SIUL Tristate — — E0UC[18] eMIOS_0 — — — — — — — SIN_1 DSPI_1 PE[3] PCR[67] GPIO[67] SIUL Tristate — — E0UC[19] eMIOS_0 SOUT_1 DSPI_1 — — — MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 65 — LIN3TX LINFlex_3 CS3_1 DSPI_1 — — — — EIRQ[10] SIUL PE[11] PCR[75] GPIO[75] SIUL Tristate — — — — — CS4_1 DSPI_1 — — — — LIN3RX LINFlex_3 — WKUP[14] WKPU MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 66 GPIO[82] SIUL Tristate — — — E0UC[12] eMIOS_0 CS0_2 DSPI_2 — — — — ANS[10] PF[3] PCR[83] GPIO[83] SIUL Tristate — — — E0UC[13] eMIOS_0 CS1_2 DSPI_2 — — — — ANS[11] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 67 — — — — — — — — — — — — PF[11] PCR[91] GPIO[91] SIUL Tristate — — — — — — — — — — — — — WKUP[15] WKPU MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 68 SIUL Tristate — — — E1UC[11] eMIOS_1 — — — — — — PG[3] PCR[99] GPIO[99] SIUL Tristate — — — E1UC[12] eMIOS_1 — — — — — — — WKUP[17] WKPU MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 69 SIUL Tristate — — — 115 B12 E0UC[25] eMIOS_0 — — — — — — PG[12] PCR[108] AF0 GPIO[108] SIUL Tristate — — — E0UC[26] eMIOS_0 — — — — — — MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 70 PCR[116] AF0 GPIO[116] SIUL Tristate — — — E1UC[6] eMIOS_1 — — — — — — PH[5] PCR[117] AF0 GPIO[117] SIUL Tristate — — — E1UC[7] eMIOS_1 — — — — — — MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 71 Be aware that this pad is used on the MPC5607B 100-pin and 144-pin to provide VDD_HV_ADC and VSS_HV_ADC1. Therefore, you should be careful in ensuring compatibility between MPC5604B and MPC5607B. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
Page 72: Nexus 2+ Pins
TDO pin and GND instead. Available only on MPC560xC versions and MPC5604B 208 MAPBGA devices Not available on MPC5602B devices Not available in 100 LQFP package...
Page 73 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 74: Boot Mechanism
The SSCM preforms a lot of the automated boot activity including reading the latched value of the FAB (PA[9]) pin to determine whether to boot from flash memory or serial boot mode. This is illustrated in Figure 5-1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 75: Flash Memory Boot
— A BOOT_ID field that must be correctly set to 0x5A in order to "validate" the boot sector • 32-bit reset vector (this is the start address of the user code) The location and structure of the boot sectors in flash memory are shown in Figure 5-2. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 76 BAM address and the core starts to execute the code to enter static mode as follows: • The core executes the "wait" instruction which halts the core. The sequence is illustrated in Figure 5-3. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 77: Serial Boot Mode
• JTAG / Nexus debug interface • Serial boot mode (which could otherwise be used to download and execute code to query or modify the flash memory) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 78 Each 32-bit register is split into an upper and lower 16-bit field. The upper 16 bits (the SC field) are used to control serial boot mode censorship. The lower 16 bits (the CW field) are used to control flash memory boot censorship. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 79 — to modify the CW field in both NVSCC0,1 registers so they match but do not equal 0x55AA. This will allow you to enter the private password in both serial and flash boot modes. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 80 NVSCC0,1 registers as well as detailing the correct way to enter the serial password. In the password examples, assume the 64-bit password has been programmed into the shadow flash memory in the order {NVPWD0, NWPWD1} and has a value of 0x01234567_89ABCDEF. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 81 Censored with True Enter password as Note: CW != 0x55AA private password {NVPWD1, NVPWD0} SC = 0x55AA over JTAG example – 0x89ABCDEF_01234567 False Uncensored Figure 5-4. Censorship control in flash memory boot mode MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 82: Boot Assist Module (Bam)
Places the microcontroller into static mode if flash memory boot mode is selected and a valid BOOT_ID is not located in one of the boot sectors by the SSCM 5.2.1 BAM software flow Figure 5-6 illustrates the BAM logic flow. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 83 In static mode a wait instruction is executed to halt the core. For the FlexCAN and LINFlex serial boot modes, the respective area of BAM code is executed to download the code to SRAM. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 84 1. Since the device supports only VLE code and not Book E code, this flag is used only for backward compatibility. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 85 BAM code. In this case the SSCM is used to obtain the private password from the flash memory of the censored device. When the SSCM reads the private password it inverts the order of {NVPWD0, NWPWD1} so the password entered over the serial download needs to be {NVPWD1, NVPWD0}. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 86 2. If the private password is used, the BAM code does a direct comparison between the serial password and the private password in flash memory, {NVPWD0, NVPWD1}. 3. If the password does not match, the BAM code immediately terminates the download and pushes the microcontroller into static mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 87 7. Finally, the BAM code reads SEC. If SEC = 0, execution is transferred to the code in the SRAM. If SEC = 1, the BAM code forces the microcontroller into static mode. Figure 5-8 shows this in more detail. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 88 With LINFlex, any receive error will result in static mode. With FlexCAN, the host will re-transmit data if there has been no acknowledgment from the microcontroller. However there could be a situation where the receiver configuration has an error which would result in static mode entry. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 89 Since the SRAM is protected by 32-bit wide Error Correction Code (ECC), the BAM code always writes bytes into SRAM grouped into 32-bit words. If the last byte received does not fall onto a 32-bit boundary, the BAM code fills any additional bytes with 0x0. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 90: Linflex (Rs232) Boot
1 stop bit. Byte field Start Stop Figure 5-10. LINFlex bit timing in UART mode 5.2.2.2 Protocol Table 5-8 summarizes the protocol and BAM action during this boot mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 91: Flexcan Boot
It uses the standard 11-bit identifier format detailed in FlexCAN 2.0A specification. FlexCAN controller bit timing is programmed with 10 time quanta, and the sample point is 2 time quanta before the end, as shown in Figure 5-11. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 92 SRAM starting from the “Load address”. binary data binary data “Load address” increments until the number of data received and stored matches the size as specified in the previous step. None None Branch to downloaded code MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 93: System Status And Configuration Module (Sscm)
— Microcontroller Mode and Security Status (including censorship and serial boot information) — Search Code Flash for bootable sector — Determine boot vector • Device identification information (MCU ID Registers) • Debug Status Port enable and selection • Bus and peripheral abort enable/disable MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 94: Modes Of Operation
PUB SEC BMODE Reset Figure 5-13. System Status Register (SSCM_STATUS) Table 5-11. SSCM_STATUS allowed register accesses Access type 8-bit 16-bit 32-bit Read Allowed Allowed Allowed Write Not allowed Not allowed Not allowed MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 95 The System Memory Configuration register is a read-only register that reflects the memory configuration of the system. Offset: 0x02 Access: Read PRSZ PVLB DTSZ DVLD Reset Figure 5-14. System Memory Configuration Register (SSCM_MEMCONFIG) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 96 5.3.4.3 Error Configuration (SSCM_ERROR) The Error Configuration register is a read-write register that controls the error handling of the system. Offset: 0x06 Access: Read/write PAE RAE Reset Figure 5-15. Error Configuration (SSCM_ERROR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 97 011 Mode 3 selected 100 Mode 4 selected 101 Mode 5 selected 110 Mode 6 selected 111 Mode 7 selected Table 5-18 describes the functionality of the Debug Status Port in each mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 98 All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC). 5.3.4.5 Password comparison registers These registers provide a means for the BAM code to unsecure the device via the SSCM if the password has been provided via serial download. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 99 Table 5-21. SSCM_PWCMPH/L allowed register accesses Access type 8-bit 16-bit 32-bit Read Allowed Allowed Allowed Write Not allowed Not allowed Allowed All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 100 SSCM_PWCMPH register, then the lower word to the SSCM_PWCMPL register. The SSCM compares the 64-bit password entered into the SSCM_PWCMPH / SSCM_PWCMPL registers with the NVPWM[1,0] private password stored in the shadow flash. If the passwords match then the SSCM temporarily uncensors the microcontroller. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 101 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 102 ——— Clocks and power ——— MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 103 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 104: Clock Architecture
Chapter 6 Clock Description This chapter describes the clock architectural implementation for MPC5604B. Clock architecture System clocks are generated from three sources: • Fast external crystal oscillator 4-16 MHz (FXOSC) • Fast internal RC oscillator 16 MHz (FIRC) • Frequency modulated phase locked loop (FMPLL) Additionally, there are two low power oscillators: •...
Page 105: Clock Gating
Figure 6-1. MPC5604B system clock generation Clock gating The MPC5604B provides the user with the possibility of gating the clock to the peripherals. Table 6-1 describes for each peripheral the associated gating register address. See the ME_PCTLn section in this reference manual.
Page 106: Fast External Crystal Oscillator (Fxosc) Digital Interface
Table 6-1. MPC5604B — Peripheral clock sources (continued) Register gating address offset Peripheral Peripheral set (base = 0xC3FDC0C0) FlexCAN_n 16+n (n = 0..5) LINFLEX_n 48+n(n = 0..3) CANS — SIUL — WKUP — eMIOS_n 72+n (n = 0..1) RTC/API —...
Page 107: Register Description
Figure 6-2. Fast External Crystal Oscillator Control Register (FXOSC_CTL) You can read this field, and you can write a value of “1” to it. Writing a “0” has no effect. A reset will also clear this bit. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 108: Slow External Crystal Oscillator (Sxosc) Digital Interface
The SXOSC can be controlled via the SXOSC_CTL register. The OSCON bit controls the powerdown while bit S_OSC provides the oscillator clock available status. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 109: Register Description
Figure 6-3. Slow External Crystal Oscillator Control Register (SXOSC_CTL) You can read this field, and you can write a value of “1” to it. Writing a “0” has no effect. A reset will also clear this bit. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 110: Slow Internal Rc Oscillator (Sirc) Digital Interface
The SIRC output frequency can be trimmed using SIRC_CTL[SIRCTRIM]. After a power-on reset, the SIRC is trimmed using a factory test value stored in test flash memory. However, after a power-on reset MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 111: Register Description
A –1 change in SIRCTRIM increases the current frequency by  (see the device data SIRCTRIM sheet). SIRCDIV SIRC clock division factor. This field specifies the SIRC oscillator output clock division factor. The output clock is divided by the factor SIRCDIV+1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 112: Fast Internal Rc Oscillator (Firc) Digital Interface
This is the last step in the standby entry sequence. On any system wake-up event, the device exits STANDBY mode and switches on the FIRC. The actual powerdown status of the FIRC when the device is in standby is provided by RC_CTL[FIRCON_STDBY] bit. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 113: Register Description
Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor and output clock divider ratio are all software configurable. MPC5604B has one FMPLL that can generate the system clock and takes advantage of the FM mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8...
Page 114: Features
Memory map Table 6-8 shows the memory map of the FMPLL. 1. Spread spectrum should be programmed in line with maximum datasheet frequency figures. 2. FMPLL_x are mapped through the ME_CGM register slot MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 115: Register Description
0 Progressive clock switching disabled. 1 Progressive clock switching enabled. Note: Progressive clock switching should not be used if a non-changing clock is needed, such as for serial communications, until the division has finished. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 116 Divide by 8 1000 Divide by 9 1001 Divide by 10 1010 Divide by 11 1011 Divide by 12 1100 Divide by 13 1101 Divide by 14 1110 Divide by 15 1111 Clock Inhibit MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 117 0100010 Divide by 34 1011111 Divide by 95 1100000 Divide by 96 1100001–1111111 — 6.7.5.2 Modulation Register (MR) Offset: 0x4 Access: Supervisor read/write MOD_PERIOD RESET: INC_STEP RESET: Figure 6-8. Modulation Register (MR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 118: Functional Description
 clkin NDIV --------------------------------- -  IDF ODF where the value of IDF, NDIV and ODF are set in the CR and can be derived from Table 6-10, Table 6-11 Table 6-12. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 119 (FMPLL output clock frequency)/4 (FMPLL output clock frequency)/2 onward FMPLL output clock frequency FMPLL output clock Division factors of 8, 4, 2 or 1 FMPLL_clk Figure 6-9. FMPLL output clock division flow during progressive switching MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 120   100 5 INCSTEPxMODPERIOD -------------------------------------------------------------------------------------------- - ModulationDepth     MDF  – NOTE The user must ensure that the product of INCTEP and MODPERIOD is less than (2 -1). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 121: Recommendations
The main task is to permanently supervise the integrity of the various clock sources, for example a crystal oscillator or FMPLL. In case the FMPLL leaves an upper or lower frequency boundary MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 122: Main Features
External oscillator clock monitoring with respect to FIRC_clk/n clock • FMPLL clock frequency monitoring for a high and low frequency range with FIRC as reference clock • Event generation for various failures detected inside monitoring unit 6.8.3 Block diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 123: Functional Description
Figure 6-11. Clock Monitor Unit diagram 6.8.4 Functional description The clock and frequency names referenced in this block are defined as follows: • FXOSC_clk: clock coming from the fast external crystal oscillator MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 124 The internal RC oscillator is used as reliable reference clock for the clock supervision. In order to avoid false events, proper programming of the dividers is required. These have to take into account the accuracy and frequency deviation of the internal RC oscillator. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 125: Memory Map And Register Description
0x00000000 on page 117 Interrupt Status Register (CMU_ISR) 0x10 0x00000000 on page 117 Reserved 0x14 0x00000000 — Measurement Duration Register (CMU_MDR) 0x18 0x00000000 on page 118 1. x = FIRC,SIRC or SXOSC MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 126: Firc_Clk
00 Clock divided by 1 (No division) 01 Clock divided by 2 10 Clock divided by 4 11 Clock divided by 8 CME_A FMPLL_0 clock monitor enable. 0 FMPLL_0 monitor disabled. 1 FMPLL_0 monitor enabled. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 127: Frequency Display Register (Cmu_Fdr)
Field Description HFREF High Frequency reference value. This field determines the high reference value for the FMPLL clock. The reference value is given by: (HFREF  16) × (f  4). FIRC MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 128: Low Frequency Reference Register Fmpll (Cmu_Lfrefr)
HFREF value and FMPLL_clk is ‘ON’ FMPLL_clk as signalled by the MC_ME. It can be cleared by software by writing ‘1’. 0 No FHH event. 1 FHH event is pending. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 129: Measurement Duration Register (Cmu_Mdr)
This field displays the measurement duration in numbers of clock cycles of the selected clock source. This value is loaded in the frequency meter downcounter. When CMU_CSR[SFM] = 1, the downcounter starts counting. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 130: Overview
MC_CGM memory space. The MC_CGM also selects and generates an output clock. Figure 7-1 depicts the MC_CGM block diagram. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 131: Features
Figure 7-1. MC_CGM Block Diagram Features The MC_CGM includes the following features: • generates system and peripheral clocks • selects and enables/disables the system clock supply from system clock sources according to MC_ME control MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 132: Modes Of Operation
System Clock Divider Configuration 2 byte read/write on page 128 NOTE Any access to unused registers as well as write accesses to read-only registers will: • not change register content • cause a transfer error MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 133 _0080 … SIRC registers 0xC3FE _009C 0xC3FE _00A0 … FMPLL registers 0xC3FE _00BC 0xC3FE _00C0 … reserved 0xC3FE _00DC 0xC3FE _00E0 … reserved 0xC3FE _00FC 0xC3FE _0100 … CMU registers 0xC3FE _011C MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 134 0xC3FE _019C 0xC3FE _01A0 … reserved 0xC3FE _01BC 0xC3FE _01C0 … reserved 0xC3FE _01DC 0xC3FE _01E0 … reserved 0xC3FE _01FC 0xC3FE _0200 … reserved 0xC3FE _021C 0xC3FE _0220 … reserved 0xC3FE _023C MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 135 0xC3FE _02BC 0xC3FE _02C0 … reserved 0xC3FE _02DC 0xC3FE _02E0 … reserved 0xC3FE _02FC 0xC3FE _0300 … reserved 0xC3FE _031C 0xC3FE _0320 … reserved 0xC3FE _033C 0xC3FE _0340 … reserved 0xC3FE _035C MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 136: Register Descriptions
All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian. For example, the CGM_OC_EN register may be accessed as a word at address 0xC3FE_0370, as a half-word at address 0xC3FE_0372, or as a byte at address 0xC3FE_0373. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 137 Figure 7-3. Output Clock Division Select Register (CGM_OCDS_SC) This register is used to select the current output clock source and by which factor it is divided before being delivered at the output clock. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 138 0: peripheral set 1 clock • divided by system clock divider 1: peripheral set 2 clock • divided by system clock divider 2: peripheral set 3 clock Figure 7-6 for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 139 If the DE0 is set to ‘0’ (Divider 0 is disabled), any write access to the DIV0 field is ignored and the peripheral set 1 clock remains disabled. Divider 1 Enable 0 Disable system clock divider 1 1 Enable system clock divider 1 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 140: Functional Description
The reset value of all counters is ‘1’. If a divider has its DE bit in the respective configuration register set to ‘0’ (the divider is disabled), any value in its DIVn field is ignored. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 141: Output Clock Multiplexing
Output Clock Multiplexing The MC_CGM contains a multiplexing function for a number of clock sources which can then be utilized as output clock sources. The selection is done via the CGM_OCDS_SC register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 142: Output Clock Division Selection
The non-divided signal is not guaranteed to be 50% duty cycle by the MC_CGM. • the MC_CGM also has an output clock enable register (see Section 7.5.1.1, “Output Clock Enable Register (CGM_OC_EN)) which contains the output clock enable/disable control bit. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 143 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 144: Introduction
The MC_ME controls the SoC mode and mode transition sequences in all functional states. It also contains configuration, control and status registers accessible for the application. Figure 8-1 depicts the MC_ME block diagram. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 145 MC_ME VREG MC_PCU Flashes Registers Platform Interface MC_RGM FIRC MC_CGM FXOSC FMPLL core Device Mode State Machine peripherals WKPU Figure 8-1. MC_MEBlock Diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 146: Features
USER modes. BAM when present is software request STANDBY via from SAFE, TEST software, SAFE via executed in DRUN mode. and RUN0…3, software or wakeup request hardware failure. from STANDBY MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 147: External Signal Description
The MC_ME contains registers for: • mode selection and status reporting • mode configuration • mode transition interrupts status and mask control • scalable number of peripheral sub-mode selection and status reporting MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 148 0xC3FD_C09C ME_RUN_PC7 Run Peripheral Configuration 7 word read/write on page 162 0xC3FD_C0A0 ME_LP_PC0 Low-Power Peripheral Configuration word read/write on page 163 0xC3FD_C0A4 ME_LP_PC1 Low-Power Peripheral Configuration word read/write on page 163 … MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 149 CMU Control byte read/write on page 164 NOTE Any access to unused registers as well as write accesses to read-only registers will: • not change register content • cause a transfer error MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 150 ME_GS _C000 R S_CURRENT_MODE S_DFLA S_CFLA S_SYSCLK 0xC3FD ME_MCTL TARGET_MODE _C004 0xC3FD ME_ME _C008 0xC3FD ME_IS _C00C w1c w1c w1c w1c 0xC3FD ME_IM _C010 0xC3FD ME_IMTS _C014 w1c w1c w1c w1c w1c MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 151 Table 8-3. MC_ME Memory Map (continued) Address Name 0xC3FD ME_DMTS _C018 0xC3FD reserved _C01C 0xC3FD ME_RESET_ _C020 DFLAON CFLAON SYSCLK 0xC3FD ME_TEST_M _C024 DFLAON CFLAON SYSCLK 0xC3FD ME_SAFE_M _C028 DFLAON CFLAON SYSCLK MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 152 CFLAON SYSCLK 0xC3FD ME_RUN0…3 _C030 DFLAON CFLAON … 0xC3FD _C03C SYSCLK 0xC3FD ME_HALT_M _C040 DFLAON CFLAON SYSCLK 0xC3FD reserved _C044 0xC3FD ME_STOP_M _C048 DFLAON CFLAON SYSCLK 0xC3FD _C04C … reserved 0xC3FD _C050 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 153 Table 8-3. MC_ME Memory Map (continued) Address Name 0xC3FD ME_STANDB _C054 Y_MC DFLAON CFLAON SYSCLK 0xC3FD _C058 … reserved 0xC3FD _C05C 0xC3FD ME_PS0 _C060 0xC3FD ME_PS1 _C064 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 154 Table 8-3. MC_ME Memory Map (continued) Address Name 0xC3FD ME_PS2 _C068 0xC3FD ME_PS3 _C06C 0xC3FD reserved _C070 0xC3FD _C074 … reserved 0xC3FD _C07C 0xC3FD ME_RUN_PC _C080 0…7 … 0xC3FD _C09C 0xC3FD ME_LP_PC0 _C0A0 …7 … 0xC3FD _C0BC MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 155: Register Description
0xC3FD_C080, as a half-word at address 0xC3FD_C082, or as a byte at address 0xC3FD_C083. 8.3.1.1 Global Status Register (ME_GS) Address 0xC3FD_C000 Access: Supervisor read S_CURRENT_MODE S_DFLA S_CFLA Reset S_SYSCLK Reset Figure 8-2. Global Status Register (ME_GS) This register contains global mode status. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 156 11 Code flash is in normal mode and available for use S_FMPLL frequency modulated phase locked loop status 0 frequency modulated phase locked loop is not stable 1 frequency modulated phase locked loop is providing a stable clock MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 157 This register is used to trigger software-controlled mode changes. Depending on the modes as enabled by ME_ME register bits, configurations corresponding to unavailable modes are reserved and access to ME_<mode>_MC registers must respect this for successful mode requests. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 158 Read access will always return inverted key. KEY: 0101101011110000 (0x5AF0) INVERTED KEY: 1010010100001111 (0xA50F) 8.3.1.3 Mode Enable Register (ME_ME) Address 0xC3FD_C008 Access: Supervisor read/write Reset Reset Figure 8-4. Mode Enable Register (ME_ME) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 159 1 SAFE mode is enabled TEST TEST mode enable 0 TEST mode is disabled 1 TEST mode is enabled RESET RESET mode enable 0 RESET mode is disabled 1 RESET mode is enabled MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 160 (S_MTRANS transits from 1 to 0). It is cleared by writing a ‘1’ to this bit. This mode transition interrupt bit will not be set while entering low-power modes HALT, STOP, or STANDBY. 0 No mode transition complete interrupt occurred 1 Mode transition complete interrupt is pending MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 161 0 SAFE mode interrupt is masked 1 SAFE mode interrupt is enabled M_MTC Mode transition complete interrupt mask 0 Mode transition complete interrupt is masked 1 Mode transition complete interrupt is enabled MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 162 RESET/SAFE modes. It is cleared by writing a ‘1’ to this bit. 0 No new mode requested other than RESET/SAFE while SAFE event is pending 1 New mode requested other than RESET/SAFE while SAFE event is pending MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 163 PMC_PROG MC_PCU Mode Change in Progress indicator — This bit is set if the MC_PCU is in the process of powering up or down power domains. It is cleared when all power-up/down processes have completed. 0 Power-up/down transition is not in progress 1 Power-up/down transition is in progress MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 164 0 No peripheral clock disabling is pending 1 Clock disabling is pending for at least one peripheral MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 165 Address 0xC3FD_C020 Access: Supervisor read/write DFLAON CFLAON Reset SYSCLK Reset Figure 8-9. Invalid Mode Transition Status Register (ME_IMTS) This register configures system behavior during RESET mode. Please refer to Table 8-11 for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 166 Address 0xC3FD_C028 Access: Supervisor read/write DFLAON CFLAON Reset SYSCLK Reset Figure 8-11. SAFE Mode Configuration Register (ME_SAFE_MC) This register configures system behavior during SAFE mode. Please refer to Table 8-11 for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 167 This register configures system behavior during DRUN mode. Please refer to Table 8-11 for details. NOTE Byte and half-word write accesses are not allowed to this register. NOTE The values of FXOSCON, CFLAON and DFLAON are retained through STANDBY mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 168 Figure 8-14. HALT Mode Configuration Register (ME_HALT_MC) This register configures system behavior during HALT mode. Please refer to Table 8-11 for details. NOTE Byte and half-word write accesses are not allowed to this register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 169 Address 0xC3FD_C054 Access: Supervisor read/write DFLAON CFLAON Reset SYSCLK Reset Figure 8-16. STANDBY Mode Configuration Register (ME_STANDBY_MC) This register configures system behavior during STANDBY mode. Please refer to Table 8-11 for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 170 1 frequency modulated phase locked loop is switched on FXOSCON fast external crystal oscillator (4-16 MHz) control 0 fast external crystal oscillator (4-16 MHz) is switched off 1 fast external crystal oscillator (4-16 MHz) is switched on MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 171 Peripheral Status Register 0 (ME_PS0) Address 0xC3FD_C060 Access: Supervisor read Reset Reset Figure 8-17. Peripheral Status Register 0 (ME_PS0) This register provides the status of the peripherals. Please refer to Table 8-12 for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 172 Peripheral Status Register 2 (ME_PS2) Address 0xC3FD_C068 Access: Supervisor read Reset Reset Figure 8-19. Peripheral Status Register 2 (ME_PS2) This register provides the status of the peripherals. Please refer to Table 8-12 for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 173 Run Peripheral Configuration Registers (ME_RUN_PC0 … Address 0xC3FD_C080 - 0xC3FD_C09C Access: Supervisor read/write Reset Reset Figure 8-21. Run Peripheral Configuration Registers (ME_RUN_PC0…7) These registers configure eight different types of peripheral behavior during run modes. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 174 Low-Power Peripheral Configuration Registers (ME_LP_PC0 … Address 0xC3FD_C0A0 - 0xC3FD_C0BC Access: Supervisor read/write Reset Reset Figure 8-22. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) These registers configure eight different types of peripheral behavior during non-run modes. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 175 1 Peripheral is frozen if not already frozen in device modes. Note: This feature is useful to freeze the peripheral state while entering debug. For example, this may be used to prevent a reference timer from running while making a debug accesses. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 176 110 Selects ME_RUN_PC6 configuration 111 Selects ME_RUN_PC7 configuration Table 8-16. Peripheral control registers by peripheral Peripheral ME_PCTLn ADC_0 CAN sampler DMA_MUX DSPI_0 DSPI_1 DSPI_2 DSPI_3 eMIOS_0 eMIOS_1 FlexCAN_0 FlexCAN_1 FlexCAN_2 FlexCAN_3 FlexCAN_4 FlexCAN_5 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 177: Functional Description
ME_GS register matches the configuration programmed in the respective ME_<mode>_MC register. NOTE It is recommended that software poll the S_MTRANS bit in the ME_GS register after requesting a transition to HALT, STOP, or STANDBY modes. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 178: Modes Details
All power domains are made active in this mode. 8.4.2.2 DRUN Mode The device enters this mode on the following events. • automatically from RESET mode after completion of the reset sequence MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 179 If the SAFE mode is requested by software while some other mode transition process is ongoing, the new target mode becomes the SAFE mode regardless of other pending requests. In this case, the new mode request is not interpreted as an invalid request. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 180 SRAM before it changes to this mode. 8.4.2.5 RUN0…3 Modes The device enters one of these modes on the following events: MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 181 All power domains except power domains #0 and #1 are configurable in this mode in order to reduce leakage consumption. Active power domains are determined by the power configuration register PCU_PCONF2 of the MC_PCU. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 182 MC_PCU, WKPU, 8K RAM, RTC_API, CANSampler, SIRC, FIRC, SXOSC, and device and user option bits. The FIRC can be optionally switched off. This is the lowest power consumption mode possible on the device. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 183: Mode Transition Process
The SAFE mode request has the next highest priority after reset which can be generated by software via the ME_MCTL register from all software running modes including DRUN, RUN0…3, and TEST or by the MC_RGM after the detection of system hardware failures, which may occur in any mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 184 Request, the MC_ME requests each peripheral to enter its stop mode when: • the peripheral is configured to be disabled via the target mode, the peripheral configuration registers ME_RUN_PC0…7 and ME_LP_PC0…7, and the peripheral control registers ME_PCTL0…143 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 185 <clock source>ON bits of the ME_<current mode>_MC and ME_<target mode>_MC registers. The following system clock sources are controlled at this step: • the fast internal RC oscillator (16 MHz) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 186 On completion of the Clock Sources Switch-On Main Voltage Regulator Switch-On, if the FMPLL is to be switched on from the off state based on the FMPLLON bit of the ME_<current mode>_MC and MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 187 System Clock Switching Based on the SYSCLK bit field of the ME_<current mode>_MC and ME_<target mode>_MC registers, if the target and current system clock configurations differ, the following method is implemented for clock switching. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 188 STOP STANDBY        16 MHz int. RC (default) (default) (default) (default) (default) (default) (default) osc.      div. 16 MHz int. RC osc. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 189 FMPLL is to be switched off, the MC_ME requests the FMPLL to power down and updates its availability status bit S_FMPLL of the ME_GS register to ‘0’. This step is executed only after the System Clock Switching process is completed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 190 FIRCON bit of the ME_STANDBY_MC register. 8.4.3.22 Current Mode Update The current mode status bit field S_CURRENT_MODE of the ME_GS register is updated with the target mode bit field TARGET_MODE of the ME_MCTL register when: MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 191 Software can monitor the mode transition status by reading the S_MTRANS bit of the ME_GS register. The mode transition latency can differ from one mode to another depending on the resources’ availability before the new mode request and the target mode’s requirements. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 192 Memory Clock Disable FLASH Power Domain Switch-Off Outputs -Off Switch-Off Switch-Off STANDBY Target Clock sources Main VREG STANDBY Request Switch-Off Switch-Off S_MTRANS = ‘0’ Current Mode Update Figure 8-25. MC_ME Transition Diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 193: Protection Of Mode Configuration Registers
Section 8.4.4, “Protection of Mode Configuration Registers, the interrupt pending bit I_ICONF of the ME_IS register is set and an interrupt request is generated if the mask bit M_ICONF of ME_IM register is ‘1’. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 194 (i.e. S_MTRANS is ‘1’). During the low-power mode exit process, if the system is not able to enter the respective RUN0…3 mode properly (i.e. all status bits of the ME_GS register match with configuration bits in the ME_<mode>_MC register), then software MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 195: Peripheral Clock Gating
Any modifications to the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers do not affect the clock gating behavior until a new mode transition request is generated. Whenever the processor enters a debug session during any mode, the following occurs for each peripheral: MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 196: Application Example
8.4.7 Application Example Figure 8-26 shows an example application flow for requesting a mode change and then waiting until the mode transition has completed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 197 ME_MCTL write with current or mode change DONE SAFE mode and key ME_MCTL write with current or SAFE mode and inverted key Figure 8-26. MC_ME Application Example Flow Diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 198: Introduction
The reset sequencer is a state machine which controls the different phases (PHASE0, PHASE1, PHASE2, PHASE3, and IDLE) of the reset sequence and control the reset signals generated in the system. Figure 9-1 depicts the MC_RGM block diagram. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 199: Features
(reset status flags) • conversion of reset events to SAFE mode or interrupt request events (for further mode details, please see the MC_ME chapter) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 200: Modes Of Operation
IDLE phase. During this entire process, the MC_ME state machine is held in RESET mode. Only at the end of the reset sequence, when the IDLE phase is reached, does the MC_ME enter the DRUN mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 201: External Signal Description
‘0’ = disable, ‘1’ = enable. NOTE Any access to unused registers as well as write accesses to read-only registers will: • not change register content • cause a transfer error MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 202 W w1c w1c w1c w1c w1c 0xC3FE RGM_ _4004 FERD / RGM_ DERD 0xC3FE _4008 … reserved 0xC3FE _400C 0xC3FE RGM_ _4010 FEAR / RGM_ DEAR MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 203: Register Descriptions
The bytes are ordered according to big endian. For example, the RGM_STDBY register may be accessed as a word at address 0xC3FE_4018, as a half-word at address 0xC3FE_401A, or as a byte at address 0xC3FE_401B. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 204 1 A FMPLL fail event has occurred F_CHKSTOP Flag for checkstop reset 0 No checkstop reset event has occurred since either the last clear or the last destructive reset assertion 1 A checkstop reset event has occurred MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 205 Flag for 2.7 V low-voltage detected 0 No 2.7 V low-voltage detected event has occurred since either the last clear or the last power-on reset assertion 1 A 2.7 V low-voltage detected event has occurred MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 206 SAFE mode or interrupt request are similarly asserted on the reset’s deassertion. 9.3.1.3 Functional Event Reset Disable Register (RGM_FERD) Address 0xC3FE_4004 Access: Supervisor read/write Figure 9-4. Functional Event Reset Disable Register (RGM_FERD) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 207 Disable JTAG initiated reset 0 A JTAG initiated reset event triggers a reset sequence 1 A JTAG initiated reset event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_JTAG MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 208 0 A 1.2 V low-voltage detected (power domain #0) event triggers a reset sequence 1 A 1.2 V low-voltage detected (power domain #0) event generates either a SAFE mode or an interrupt request depending on the value of RGM_DEAR.AR_LVD12_PD0 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 209 Alternate Request for FMPLL fail 0 Generate a SAFE mode request on a FMPLL fail event if the reset is disabled 1 Generate an interrupt request on a FMPLL fail event if the reset is disabled MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 210 0 Generate a SAFE mode request on a software watchdog timer event if the reset is disabled 1 Generate an interrupt request on a software watchdog timer event if the reset is disabled MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 211 0 The reset sequence triggered by a code or data flash fatal error event will start from PHASE1 1 The reset sequence triggered by a code or data flash fatal error event will start from PHASE3, skipping PHASE1 and PHASE2 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 212 0 The reset sequence triggered by a JTAG initiated reset event will start from PHASE1 1 The reset sequence triggered by a JTAG initiated reset event will start from PHASE3, skipping PHASE1 and PHASE2 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 213 This register enables the generation of an external reset on functional reset. It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read in user mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 214: Functional Description
This is summarized in Table 9-12. Table 9-12. MC_RGM Reset Implications External Reset Boot Mode Source What Gets Reset Assertion Capture power-on reset MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 215 The state machine used to produce the reset sequence is shown in Figure 9-11. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 216 PHASE0 Phase This phase is entered immediately from any phase on a power-on or enabled ‘destructive’ reset event. The reset state machine exits PHASE0 and enters PHASE1 on verification of the following: MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 217 This is the final phase and is entered on exit from PHASE3. When this phase is reached, the MC_RGM releases control of the system to the platform and waits for new reset events that can trigger a reset sequence. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 218: Destructive Resets
The MC_RGM may also assert the external reset if the reset sequence was triggered by one of the following: • a power-on reset • a ‘destructive’ reset event MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 219: Functional Resets
The MC_RGM provides alternative events to be generated on reset source assertion. When a reset source is asserted, the MC_RGM normally enters the reset sequence. Alternatively, it is possible for each reset MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 220: Boot Mode Capturing
RC oscillator (16 MHz) clock periods before the external reset deassertion crosses the V threshold. NOTE RESET can be low as a consequence of the internal reset generation. This will force re-sampling of the boot mode pins. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 221 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 222: Introduction
#0 are in the power-down state. In addition, the MC_PCU acts as a bridge for mapping the VREG peripheral to the MC_PCU address space. Figure 10-1 depicts the MC_PCU block diagram. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 223: Features
• maps the VREG registers to the MC_PCU address space 10.1.3 Modes of Operation The MC_PCU is available in all device modes. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 224: External Signal Description
Any access to unused registers as well as write accesses to read-only registers will: • not change register content • cause a transfer error Table 10-2. MC_PCU Memory Map Address Name 0xC3FE PCU_PCONF0 _8000 0xC3FE PCU_PCONF1 _8004 0xC3FE PCU_PCONF2 _8008 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 225: Register Descriptions
For example, the PD0 field of the PCU_PSTAT register may be accessed as a word at address 0xC3FE_8040, as a half-word at address 0xC3FE_8042, or as a byte at address 0xC3FE_8043. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 226 1 Power domain on RUN2 Power domain control during RUN2 mode 0 Power domain off 1 Power domain on RUN3 Power domain control during RUN3 mode 0 Power domain off 1 Power domain on MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 227 STANDBY mode, power domain #1 is disconnected from the power supply, and therefore PCU_PCONF1.STBY0 is always ‘0’. Power domain #0 is always on, and therefore PCU_PCONF0.STBY0 is ‘1’. For further details about STANDBY mode, please see Section 10.4.4.2, “STANDBY Mode Transition. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 228 This register reflects the power status of all available power domains. Table 10-4. Power Domain Status Register (PCU_PSTAT) Field Descriptions Field Description Power status for power domain #n 0 Power domain is inoperable 1 Power domain is operable MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 229: Functional Description
RUN0 to HALT and back, which will result in power domain #2 being powered down during the HALT mode. In this case, PCU_PCONF2.HALT is programmed to be ‘0’. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 230 Once STANDBY is entered it can only be left via a system wakeup. On exiting the STANDBY mode, all power domains are powered up according to the settings in the PCU_PCONFn registers, and the DRUN mode is entered. In DRUN mode, at least power domains #0 and #1 are powered. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 231 No software configuration is required to enable this power saving state. While a memory is residing in this state an increased power saving is achieved. Data in the memories is retained. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 232: Initialization Information
Additional power is required during restoring the information (e.g. in the platform). Care should be taken that the time during which the SoC is operating in STANDBY mode is significantly longer than the required time for restoring the information. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 233 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 234: Voltage Regulators
The LPREG generates power for the device in the STOP mode, providing the output supply of 1.2 V. It always sees the minimum external capacitance. The control part of the regulator can be used to disable the low power regulator. It is managed by MC_ME. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 235: Ultra Low Power Regulator (Ulpreg)
The VREG digital interface also holds control register to mask 5 V LVD status coming from the voltage regulator at the power-up. 1. See section “Voltage monitor electrical characteristics” of the data sheet for detailed information about this voltage value. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 236: Register Description
3. BV (high voltage external power supply for voltage regulator module) — This must be provided externally through VDD_BV_/VSS_BV power pins. Voltage values should be aligned with . Refer to data sheet for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 237: Power Domain Organization
1. Regulator ground is separated from oscillator ground and shorted to the LV ground through star routing 2. During production test, it is also possible to provide the VDD_LV externally through pins by configuring regulator in bypass mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 238 VGATE Reset e200z0h Wakeup Pads JTAG Vdd5_cfla CFlash platform 330nF 330nF DFlash 16 KB SRAM Vdd5_dlf Peripheral Peripheral PH15 VDD12 FMPLL 330nF AVSSref AVSSsupply AVDDsupply VDD_LV_COR VDD_LV_BKP AVDDref VDD_LV_FLA0 VDD_LV_FLA1 VDD_LV_BKP domain MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 239 Figure 11-2. Power domain organization MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 240: Overview
 WKPU14 PE11 PCR75 LIN3-RX EIF14   WKPU15 PF11 PCR91 — EIF15 1. Up to 18 external sources in 144-pin LQFP and 208BGA; up to 14 external sources in 100-pin LQFP MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 241 Peripheral wakeup Bridge filter Pads IOMux 0-19 IRQ / Wakeup filter - Configuration filter bypass Mode / system wakeup Power Control Interrupt IRQs Controller 0-19 RTC, etc. Figure 12-1. WKPU block diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 242: Features
Memory map and register description This section provides a detailed description of all registers accessible in the WKPU module. 12.4.1 Memory map Table 12-2 gives an overview on the WKPU registers implemented. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 243: Nmi Status Flag Register (Nsr)
12.4.2 NMI Status Flag Register (NSR) This register holds the non-maskable interrupt status flags. Offset: 0x00 Access: User read/write NIF0 W w1c Reset Reset Figure 12-2. NMI Status Flag Register (NSR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 244: Nmi Configuration Register (Ncr)
Writing a 1 to this bit locks the configuration for the NMI until it is unlocked by a system reset. Writing a 0 has no effect. NDSS0 NMI Destination Source Select 00 Non-maskable interrupt 01 Critical interrupt 10 Machine check request 11 Reserved—no NMI, critical interrupt, or machine check request generated MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 245: Wakeup/Interrupt Status Flag Register (Wisr)
This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (IRER[x]), EIF[x] causes an interrupt request. 1 An event as defined by WIREER and WIFEER has occurred 0 No event has occurred on the pad MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 246: Interrupt Request Enable Register (Irer)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-6. Wakeup Request Enable Register (WRER) WRE[18:15] are not available in all 100-pin packages. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 247: Wakeup/Interrupt Rising-Edge Event Enable Register (Wireer)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-8. Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER) IFEE[18:15] are not available in all 100-pin packages. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 248: Wakeup/Interrupt Filter Enable Register (Wifer)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-10. Wakeup/Interrupt Pullup Enable Register (WIPUER) IPUE[18:15] are not available in all 100-pin packages. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 249: Functional Description
Each NMI passes through a bypassable analog glitch filter. NOTE Glitch filter control and pad configuration should be done while the NMI is disabled in order to avoid erroneous triggering by glitches caused by the configuration process itself. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 250 Once the pad’s NMI functionality has been enabled, the pad cannot be reconfigured in the IOMUX to override or disable the NMI. The NMI destination interrupt is controlled by the user through the configuration of the NDSS0 field. See Table 12-4 for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 251: External Wakeups/Interrupts
Interrupt enable IRER[19:0] WISR[19:0] Flag[19:16] Flag[15:8] Flag[7:0] Rising WIREER[19:0] Edge Detection Glitch Filter enable Falling WIFER[19:0] Analog Glitch Filter WIFEER[19:0] Interrupt Edge Enable Pads RTC API Figure 12-12. External interrupt pad diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 252: On-Chip Wakeups
In order to allow software to determine the wakeup source at one location, on-chip wakeups are reported along with external wakeups in the WISR register (see Figure 12-4 for details). Enabling and clearing of these wakeups are done via the on-chip wakeup source’s own registers. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 253 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 254: Overview
— 10-bit compare value to support wakeup intervals of 1.0 ms to 1 s — Compare value changeable while counter is running • Configurable interrupt for RTC match, API match, and RTC rollover • Configurable wakeup event for RTC match, API match, and RTC rollover MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 255 22:31 API wakeup Reserved sync FIRC SIRC APIF 32-bit counter SXOSC APIIE interrupt 10:21 reset RTCVAL RTC wakeup sync sync RTCF RTCIE RTC interrupt ROVRF RTCIE ROVREN Figure 13-1. RTC/API block diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 256: Device-Specific Information
Figure 13-2. Clock gating for RTC clocks 13.3 Device-specific information For MPC5604B, the device specific information is the following: • SXOSC, FIRC and SIRC clocks are provided as counter clocks for the RTC. Default clock on reset is SIRC divided by 4.
Page 257: Debug Mode
Table 13-2. RTCSUPV field descriptions Field Description SUPV RTC Supervisor Bit 0 All registers are accessible in both user as well as supervisor mode. 1 All other registers are accessible in supervisor mode only. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 258: Rtc Control Register (Rtcc)
The counter freezes on entering the debug mode on the last valid count value if the FRZEN bit is set. After coming out of the debug mode, the counter starts from the frozen value. 0 Counter does not freeze in debug mode. 1 Counter freezes in debug mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 259 Note: API functionality starts only when APIVAL is non zero. The first API interrupt takes two more cycles because of synchronization of APIVAL to the RTC clock. After that interrupts are periodic in nature. The minimum supported value of APIVAL is 4. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 260: Rtc Status Register (Rtcs)
The ROVRF bit indicates that the RTC has rolled over from 0xffff_ffff to 0x0000_0000. ROVRF is cleared by writing a 1 to ROVRF. 1 RTC has rolled over 0 RTC has not rolled over MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 261: Rtc Counter Register (Rtccnt)
All the flags and counter values are synchronized with the system clock. It is assumed that the system clock frequency is always more than or equal to the rtc_clk used to run the counter. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 262: Api Functional Description
If there is a match while in low power mode, then the API will first generate a wakeup request to force a wakeup into normal operation, then the APIF flag will be set. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 263 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 264: Introduction
User selectable CAN Rx sample port [CAN0RX-CAN5RX] • 16 MHz fast internal RC oscillator clock • 5-bit clock prescaler • Configurable trigger mode (immediate, next frame) • Flexible samples processing by software • Very low power consumption MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 265: Register Description
1: RC_CLK is currently xmem_ck 0: ipg_clk_s is currently xmem_ck MODE 0: Skip the first frame and sample and store the second frame (SF_MODE) 1: Sample and store the first frame (FF_MODE) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 266 The reset values are unknown. They will be filled only after the first CAN sampling. SR[15:0] Reset The reset values are unknown. They will be filled only after the first CAN sampling. Figure 14-3. Sample register n MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 267: Functional Description
In case of any activity on the selected Rx line, the sampler enables the 16 MHz fast internal RC oscillator. When bit CAN_SMPLR_EN is reset to 0, the sampler should receive at last three FIRC clock pulses to reset itself, after which the FIRC can be switched off. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 268: Baud Rate Generation
= 8µs Eqn. 14-1 To achieve 8 samples per bit Sample period= 8/8 µs = 1 µs BRP = 1 µs/62.5 ns = 16. Thus in this case BRP = 01111 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 269 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 270 ——— Core platform modules ——— MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 271 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 272: Overview
Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 273 Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 274: Block Diagram
The following is a list of some of the key features of the e200z0h core: • 32-bit Power Architecture VLE-only programmer’s model • Single issue, 32-bit CPU • Implements the VLE APU for reduced code footprint MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 275: Instruction Unit Features
The e200 integer unit supports single cycle execution of most integer instructions: • 32-bit AU for arithmetic and comparison operations • 32-bit LU for logical operations • 32-bit priority encoder for count leading zero’s function MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 276: Load/Store Unit Features
Run-time access to the processor memory map via the JTAG port. This allows for enhanced download/upload capabilities. • Watchpoint Messaging via the auxiliary interface 1. Advanced Microcontroller Bus Architecture 2. Advanced High Performance Bus MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 277: Core Registers And Programmer's Model
Significant Bit) to 31 (Least Significant Bit), rather than the Book E numbering scheme of 32:63, thus register bit numbers for some registers in Book E are 32 higher. Where appropriate, the Book E defined bit numbers are shown in parentheses. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 278 1 - These e200-specific registers may not be DVC2 SPR 319 supported by other Power Architecture processors. 2 - Optional registers defined by the Power Architecture technology 3 - Read-only registers Figure 15-2. e200z0 SUPERVISOR Mode Program Model SPRs MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 279 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 280: Introduction
— Ability to modify the ISR or task priority; modifying the priority can be used to implement the priority ceiling protocol for accessing shared resources. • Low latency – 3 clocks from receipt of interrupt request from peripheral to interrupt request to processor MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 281: Block Diagram
FlexCAN_1 FlexCAN_2 FlexCAN_3 FlexCAN_4 FlexCAN_5 LINFlex_0 LINFlex_1 LINFlex_2 LINFlex_3 DSPI_0 DSPI_1 DSPI_2 I2C_0 Enhanced Modular I/O Subsystem 0 (eMIOS_0) eMIOS_1 16.3 Block diagram Figure 16-1 provides a block diagram of the INTC. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 282: Modes Of Operation
PRI value in INTC_CPR onto the associated LIFO and updates PRI in the associated INTC_CPR with the new priority. Furthermore, the interrupt vector to the processor is driven as all 0s. The interrupt acknowledge signal from the associated processor is ignored. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 283: Memory Map And Register Description
16.5 Memory map and register description 16.5.1 Module memory map Table 16-2 shows the INTC memory map. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 284: Register Description
In either software or hardware vector mode, the size of a write to either INTC_SSCIR0_3–INTC_SSCIR4_7 or INTC_EOIR does not affect the operation of the write. 16.5.2.1 INTC Module Configuration Register (INTC_MCR) The module configuration register is used to configure options of the INTC. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 285 Figure 16-3. INTC Current Priority Register (INTC_CPR) Table 16-4. INTC_CPR field descriptions Field Description Priority PRI is the priority of the currently executing ISR according to the field values defined in Table 16-5. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 286 Priority 10 1001 Priority 9 1000 Priority 8 0111 Priority 7 0110 Priority 6 0101 Priority 5 0100 Priority 4 0011 Priority 3 0010 Priority 2 0001 Priority 1 0000 Priority 0—lowest priority MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 287 The interrupt acknowledge register provides a value which can be used to load the address of an ISR from a vector table. The vector table can be composed of addresses of the ISRs specific to their respective interrupt vectors. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 288 Reading the INTC_EOIR has no effect on the LIFO. 16.5.2.5 INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3–INTC_SSCIR4_7) Offset: 0x0020 Access: User read/write SET0 SET1 Reset SET2 SET3 Reset Figure 16-7. INTC Software Set/Clear Interrupt Register 0–3 (INTC_SSCIR[0:3]) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 289 CLRx is the flag bit. Writing a 1 to CLRx clears it. Writing a 0 to CLRx has no effect. If a 1 is written simultaneously to a pair of SETx and CLRx bits, CLRx will be asserted, regardless of whether CLRx was asserted before the write. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 290 Section 16.6, “Functional description. Table 16-9. INTC Priority Select Register address offsets INTC_PSRx_x Offset address INTC_PSRx_x Offset address INTC_PSR0_3 0x0040 INTC_PSR108_111 0x00AC INTC_PSR4_7 0x0044 INTC_PSR112_115 0x00B0 INTC_PSR8_11 0x0048 INTC_PSR116_119 0x00B4 INTC_PSR12_15 0x004C INTC_PSR120_123 0x00B8 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 291: Functional Description
INTC_PSR96_99 0x00A0 INTC_PSR204_207 0x010C INTC_PSR100_103 0x00A4 INTC_PSR208_210 0x0110 INTC_PSR104_107 0x00A8 — — 16.6 Functional description The functional description involves the areas of interrupt request sources, priority management, and handshaking with the processor. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 292 Section B (On-Platform Peripherals) 0x0800 Software configurable flag 0 Software 0x0804 Software configurable flag 1 Software 0x0808 Software configurable flag 2 Software 0x080C Software configurable flag 3 Software 0x0810 Software configurable flag 4 Software MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 293 0x0864 Reserved 0x0868 Reserved 0x086C Reserved 0x0870 Timeout 0x0874 Reserved 0x0878 Match on channel 0 0x087C Match on channel 1 0x0880 Match on channel 2 0x0884 Match on channel 3 0x0888 Reserved MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 294 Functional and destructive reset alternate MC_RGM event interrupt (ipi_int) 0x08E4 FXOSC counter expired (ipi_int_osc) FXOSC 0x08E8 Reserved 0x08EC PITimer Channel 0 0x08F0 PITimer Channel 1 0x08F4 PITimer Channel 2 0x08F8 ADC_EOC ADC_0 0x08FC ADC_ER ADC_0 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 295 Reserved 0x094C Reserved 0x0950 Reserved 0x0954 FlexCAN_ESR[ERR_INT] FlexCAN_1 0x0958 FlexCAN_ESR_BOFF | FlexCAN_1 FlexCAN_Transmit_Warning | FlexCAN_Receive_Warning 0x095C Reserved 0x0960 FlexCAN_BUF_00_03 FlexCAN_1 0x0964 FlexCAN_BUF_04_07 FlexCAN_1 0x0968 FlexCAN_BUF_08_11 FlexCAN_1 0x096C FlexCAN_BUF_12_15 FlexCAN_1 0x0970 FlexCAN_BUF_16_31 FlexCAN_1 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 296 FlexCAN_2 0x09C4 FlexCAN_BUF_32_63 FlexCAN_2 0x09C8 DSPI_SR[TFUF] DSPI_2 DSPI_SR[RFOF] 0x09CC DSPI_SR[EOQF] DSPI_2 0x09D0 DSPI_SR[TFFF] DSPI_2 0x09D4 DSPI_SR[TCF] DSPI_2 0x09D8 DSPI_SR[RFDF] DSPI_2 0x09DC LINFlex_RXI LINFlex_2 0x09E0 LINFlex_TXI LINFlex_2 0x09E4 LINFlex_ERR LINFlex_2 0x09E8 LINFlex_RXI LINFlex_3 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 297 EMIOS_GFR[F4,F5] eMIOS_0 0x0A40 EMIOS_GFR[F6,F7] eMIOS_0 0x0A44 EMIOS_GFR[F8,F9] eMIOS_0 0x0A48 EMIOS_GFR[F10,F11] eMIOS_0 0x0A4C EMIOS_GFR[F12,F13] eMIOS_0 0x0A50 EMIOS_GFR[F14,F15] eMIOS_0 0x0A54 EMIOS_GFR[F16,F17] eMIOS_0 0x0A58 EMIOS_GFR[F18,F19] eMIOS_0 0x0A5C EMIOS_GFR[F20,F21] eMIOS_0 0x0A60 EMIOS_GFR[F22,F23] eMIOS_0 0x0A64 EMIOS_GFR[F24,F25] eMIOS_0 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 298 FlexCAN_3 0x0AB8 FlexCAN_ESR_BOFF | FlexCAN_3 FlexCAN_Transmit_Warning | FlexCAN_Receive_Warning 0x0ABC Reserved 0x0AC0 FlexCAN_BUF_0_3 FlexCAN_3 0x0AC4 FlexCAN_BUF_4_7 FlexCAN_3 0x0AC8 FlexCAN_BUF_8_11 FlexCAN_3 0x0ACC FlexCAN_BUF_12_15 FlexCAN_3 0x0AD0 FlexCAN_BUF_16_31 FlexCAN_3 0x0AD4 FlexCAN_BUF_32_63 FlexCAN_3 0x0AD8 Reserved 0x0ADC Reserved MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 299 FlexCAN_ESR_BOFF | FlexCAN_5 FlexCAN_Transmit_Warning | FlexCAN_Receive_Warning 0x0B30 Reserved 0x0B34 FlexCAN_BUF_0_3 FlexCAN_5 0x0B38 FlexCAN_BUF_4_7 FlexCAN_5 0x0B3C FlexCAN_BUF_8_11 FlexCAN_5 0x0B40 FlexCAN_BUF_12_15 FlexCAN_5 0x0B44 FlexCAN_BUF_16_31 FlexCAN_5 0x0B48 FlexCAN_BUF_32_63 FlexCAN_5 0x0B4C Reserved 0x0B50 Reserved 0x0B54 Reserved MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 300: Interrupt Request Sources
Priority Select Registers (INTC_PSR0_3–INTC_PSR208_210). The result is compared to PRI in the associated INTC_CPR. The results of those comparisons manage the priority of the ISR executed by the associated processor. The associated LIFO also assists in managing that priority. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 301 PRI value in the INTC_CPR does not need to be loaded from the INTC_CPR and stored onto the context stack. Likewise at the end of the interrupt exception handler, the priority does not need to be loaded from the context stack and stored into the INTC_CPR. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 302: Handshaking With Processor
ISR, the interrupt request for the preempted ISR or any other asserted peripheral or software settable interrupt request at or below that priority will not cause a preemption. Instead, after the restoration MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 303 The handshaking near the end of the interrupt exception handler, that is the writing to the INTC_EOIR, is the same as in software vector mode. Refer to Section 16.6.3.1.2, “End of interrupt exception handler. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 304: Initialization/Application Information
PRI in INTC_CPR to zero enable processor recognition of interrupts 16.7.2 Interrupt exception handler These example interrupt exception handlers use Power Architecture™ assembly code. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 305 This example assumes that each interrupt_exception_handlerx only has space for four instructions, and therefore a branch to interrupt_exception_handler_continuedx is needed. interrupt_exception_handlerx: b interrupt_exception_handler_continuedx# 4 instructions available, branch to continue MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 306: Isr, Rtos, And Task Hierarchy
Since the ISRs are outside the control of the RTOS, this ISR will not run unless called by another ISR or the interrupt exception handler, perhaps after executing another ISR. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 307: Order Of Execution
ISR208 completes. Interrupt exception handler writes to INTC_EOIR. Interrupt taken. ISR308 starts to execute. ISR308 completes. Interrupt exception handler writes to INTC_EOIR. ISR108 completes. Interrupt exception handler writes to INTC_EOIR. RTOS continues execution. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 308: Priority Ceiling Protocol
(DMS). In RMS, the ISRs which have higher request rates have higher priorities. In DMS, if the deadline is before the next time the ISR is requested, then the ISR is MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 309: Software Configurable Interrupt Requests
ISR completes. The lower priority ISR is scheduled according to its priority. Execution of the higher priority ISR is not resumed after the completion of the lower priority ISR. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 310: Lowering Priority Within An Isr
An ISR can clear other flag bits besides its own. One reason that an ISR clears multiple flag bits is because it serviced those flag bits, and therefore the ISRs for these flag bits do not need to be executed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 311: Examining Lifo Contents
When the examination is complete, the LIFO can be restored using this code sequence: push_lifo: load stacked PRI value and store to INTC_CPR load INTC_IACKR if stacked PRI values are not depleted, branch to push_lifo MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 312: Introduction
The crossbar of MPC5604B is the same as the one of all other PPC55xx and PPC56xx products except that it cannot be configured by software and that it has a hard-wired configuration.
Page 313: Overview
The main goal of the XBAR is to increase overall system performance by allowing multiple masters to communicate concurrently with multiple slaves. To maximize data throughput, it is essential to keep arbitration delays to a minimum. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 314: General Operation
If the slave port is currently servicing another master of a higher priority, then the master gains control of the slave port after MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 315: Slave Ports
If the new requesting master’s priority level is higher than that of the master that currently has control of the slave port, the higher priority master is granted control at the termination of any currently pending access, assuming the pending transfer is not part of a burst transfer. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 316 When the master accesses the slave port again, no other arbitration penalties are incurred except that a one clock arbitration penalty is incurred for each access request to the slave port made by another master port. All other masters pay a one clock penalty. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 317 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 318: Introduction
– Connections to the address phase address and attributes – Typical location is immediately “downstream” of the platform’s crossbar switch A simplified block diagram of the MPU module is shown in Figure 18-1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 319: Features
“Putting it all together and AHB error terminations,” for details and Section 18.8, “Application information,” for an example. • Support for 3 XBAR slave port connections: flash controller, system SRAM controller and peripherals bus MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 320: Modes Of Operation
Finally, the programming model allocates space for an MPU definition with 8 region descriptors and up to 3 XBAR slave ports, like flash controller, system SRAM controller and peripheral bus. 18.5.1 Memory map The MPU programming model map is shown in Table 18-1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 321: Register Description
Register description 18.5.2.1 MPU Control/Error Status Register (MPU_CESR) The MPU_CESR provides one byte of error status plus three bytes of configuration information. A global MPU enable/disable bit is also included in this register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 322 When the MPU detects an access error on slave port n, the 32-bit reference address is captured in this read-only register and the corresponding bit in the MPU_CESR[SPERR] field set. Additional information MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 323 MPU_EARn register contain the most recent access error; there are no hardware interlocks with the MPU_CESR[SPERR] field as the error registers are always loaded upon the occurrence of each protection violation. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 324 All other encodings are reserved. For non-core bus masters, the access attribute information is typically wired to supervisor, data (0b011). Error Read/Write This field signals the access type (read, write) of the faulting reference. 0 Read 1 Write MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 325 The second word of the MPU region descriptor defines the 31-modulo-32 byte end address of the memory region. Writes to this word clear the region descriptor’s valid bit (see Section 18.5.2.4.4, “MPU Region Descriptor n, Word 3 (MPU_RGDn.Word3) for more information). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 326 The evaluation logic defines the processor access type based on multiple AHB signals, as hwrite and hprot[1:0]. For non-processor data movement engines (bus masters 4–7), the evaluation logic simply uses hwrite to determine if the access is a read or write. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 327 If set, this flag allows bus master 4 to perform read operations. If cleared, any attempted read by bus master 4 terminates with an access error and the read is not performed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 328 0b01 r, –, x = read and execute allowed, but no write 0b10 r, w, – = read and write allowed, but no execute 0b11 Same access controls as that defined by M1UM for user mode MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 329 If only the access controls are being updated, this operation should be performed by writing to MPU_RGDAACn (Alternate Access Control n) as stores to these locations do not affect the descriptor’s valid bit. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 330 If only the access controls are being updated, this operation should be performed by writing to MPU_RGDAACn (Alternate Access Control n) as stores to these locations do not affect the descriptor’s valid bit. The memory address therefore provides an alternate location for updating MPU_RGDn.Word2. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 331 If set, this flag allows bus master 4 to perform write operations. If cleared, any attempted write by bus master 4 terminates with an access error and the write is not performed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 332 (if not allowed by any other descriptor) and the access not performed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 333: Functional Description
(RGDn) and performs two major functions: region hit determination (hit_b) and detection of an access protection violation (error). System bus RGDn address phase start r,w,x >= <= error hit_b > > hit & error hit_b | error Figure 18-10. MPU access evaluation macro MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 334 (hit_b | error) signal is used to signal the current access is not allowed and (~hit_b & error) is used as the input to MPU_EDRn (error detail register) in the event of an error. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 335: Putting It All Together And Ahb Error Terminations
When a new descriptor is loaded into a RGDn, it would typically be performed using four 32-bit word writes. As discussed in Section 18.5.2.4.4, “MPU Region Descriptor n, Word 3 (MPU_RGDn.Word3), the hardware assists in the maintenance of the valid MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 336 In any event, the processor can retrieve the captured error address and detail information simply be reading the MPU_E{A,D}Rn registers. Information on which error registers contain captured fault data is signaled by MPU_CESR[SPERR]. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 337 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 338: Introduction
To enable monitoring of an output pad value, the pad can be configured as both output and input so the actual pad value can be read back and compared with the expected value. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 339 Up to 123 I/O pins in 144-pin and 208-pin packages; up to 79 I/O pins in 100-pin packages Up to 16 I/O pins in 144-pin and 208-pin packages; up to 12 I/O pins in 100-pin packages Figure 19-1. System Integration Unit Lite block diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 340: Features
GPIO[0:122] in 144-pin LQFP and 208 MAPBGA; GPIO[0:78] in 100-pin LQFP EIRQ[12:15] available only in 144-pin LQFP 1.Some device pins, e.g., analog pins, do not have both input and output functionality. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 341: Detailed Signal Descriptions
The EIRQ[0:15] pins are connected to the SIUL inputs. Rising- or falling-edge events are enabled by setting the corresponding bits in the SIUL_IREER or the SIUL_IFEER register. 1. EIRQ[0:15] in 144-pin LQFP and 208 MAPBGA packages; EIRQ[0:11] in the 100-pin LQFP MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 342: Memory Map And Register Description
345 0x0C10–0x0C3F Reserved 0x0C40–0x0C4C Parallel GPIO Pad Data In Registers (PGPDI0 – PGPDI3) on page 346 0x0C50–0x0C7F Reserved 0x0C80–0x0C9C Masked Parallel GPIO Pad Data Out Register on page 347 (MPGPDO0–MPGPDO7) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 343: Register Protection
— PCR[34:47] (Port C[2:15]) • Pad Selection for Multiplexed Inputs Registers (PSMI0_3–PSMI28_31) • Interrupt Filter Maximum Counter Registers (IFMC0–IFMC15). Note that only IFMC[0:15] can be protected. • Interrupt Filter Clock Prescaler Register (IFCPR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 344: Register Descriptions
0b01101: 144-pin LQFP MAJOR_MASK Major Mask Revision Counter starting at 0x0. Incremented each time there is a resynthesis. MINOR_MASK Minor Mask Revision Counter starting at 0x0. Incremented each time a mask change is done. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 345 For the full part number this field needs to be combined with MIDR1[PARTNUM[15:0]]. Data Flash present 0 No Data Flash is present 1 Data Flash is present 19.5.3.3 Interrupt Status Flag Register (ISR) This register holds the interrupt flags. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 346 This flag can be cleared only by writing a ‘1’. Writing a ‘0’ has no effect. If enabled (IRER[x]), EIF[x] causes an interrupt request. 0 No interrupt event has occurred on the pad 1 An interrupt event as defined by IREER[x] and IFEER[x] has occurred MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 347 This register is used to enable rising-edge triggered events on the corresponding interrupt pads. Offset:0x0028 Access: User read/write Reset IREE[15:0] Reset Figure 19-6. Interrupt Rising-Edge Event Enable Register (IREER) IREE[15:0] in 144-pin LQFP and 208 MAPBGA packages; IREE[11:0] in 100-pin LQFP package. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 348 If IREER[IREE] and IFEER[IFEE] bits are set for the same source the interrupts are triggered by both rising edge events and falling edge events. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 349 — Select the feature location from PSMI register — Set the IBE bit in the appropriate PCR • For normal GPIO (not alternate function): — Configure PCR — Read from GPDI or write to GPDO MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 350 OBE IBE SRC WP with GPIO and digital alternate function) J (Pad with PA[1:0] OBE IBE SRC WP GPIO and analog functionality I (Pad PA[1:0] OBE IBE SRC WP dedicated to ADC) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 351 This bit controls whether weak pull up or weak pull down devices are used for the pads connected to this signal when weak pull up/down devices are enabled. 0 Weak pull-down selected 1 Weak pull-up selected MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 352 10: PCR[95] PADSEL1 0x501 CAN2RX / FlexCAN_2 00: PCR[73] 01: PCR[89] PADSEL2 0x502 CAN3RX / FlexCAN_3 00: PCR[36] 01: PCR[73] 10: PCR[89] PADSEL3 0x503 CAN4RX / FlexCAN_4 00: PCR[35] 01: PCR[43] 10: PCR[95] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 353 E0UC[6] / eMIOS_0 00: PCR[6] 01: PCR[30] PADSEL17 0x511 E0UC[7] / eMIOS_0 00: PCR[7] 01: PCR[31] PADSEL18 0x512 E0UC[10] / eMIOS_0 00: PCR[10] 01: PCR[80] PADSEL19 0x513 E0UC[11] / eMIOS_0 00: PCR[11] 01: PCR[81] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 354 Not available in 100-pin LQFP Not available on MPC5603B devices Available only on MPC5604B 208 MAPBGA devices Not available on MPC5602B and MPC5603B 100-pin devices 19.5.3.10 GPIO Pad Data Output Registers (GPDO0_3–GPDO120_123) These registers are used to set or clear GPIO pads. Each pad data out bit can be controlled separately with a byte access.
Page 355 Please see data sheet. 19.5.3.11 GPIO Pad Data Input Registers (GPDI0_3–GPDI120_123) These registers are used to read the GPIO pad data with a byte access. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 356 19.5.3.12 Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO3) MPC5604B devices ports are constructed such that they contain 16 GPIO pins, for example PortA[0..15]. Parallel port registers for input (PGPDI) and output (PGPDO) are provided to allow a complete port to be written or read in one operation, dependent on the individual pad configuration.
Page 357 Table 19-17. PGPDI0 – PGPDI3 register map Field Offset Register 0x0C40 PGPDI0 Port A Port B 0x0C44 PGPDI1 Port C Port D 0x0C48 PGPDI2 Port E Port F 0x0C4C PGPDI3 Port G Port H MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 358 It is important to note the bit ordering of the ports in the parallel port registers. The most significant bit of the parallel port register corresponds to the least significant pin in the port. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 359 These registers are used to configure the filter counter associated with each digital glitch filter. NOTE For the pad transition to trigger an interrupt it must be steady for at least the filter period. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 360 This register is used to configure a clock prescaler which is used to select the clock for all digital filter counters in the SIUL. Offsets:0x1080 Access: User read/write Reset IFCP Reset Figure 19-14. Interrupt Filter Clock Prescaler Register (IFCPR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 361: Functional Description
19-15, all port accesses are identical with each read or write being performed only at a different location to access a different port width. 1.There are exceptions. Some pads, e.g., precision analog pads, are input only. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 362: External Interrupts
All of the external interrupt pads within a single group have equal priority. Figure 19-16 for an overview of the external interrupt implementation. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 363: Pin Muxing
The bits in the ISR[EIF] field are cleared by writing a ‘1’ to them; this prevents inadvertent overwriting of other flags in the register. 19.7 Pin muxing For pin muxing, please see the signal description chapter of this reference manual. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 364 ——— Communication modules ——— MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 365 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 366: Introduction
Start and stop signal generation/detection • Repeated start signal generation • Acknowledge bit generation/detection • Bus busy detection Features currently not supported: • No support for general call address • Not compliant to ten-bit addressing MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 367: Block Diagram
C module is given below in Table 20-1. The total address for each register is the sum of the base address for the I C module and the address offset for each register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 368 Slave Address. Specific slave address to be used by the I C Bus module. Note: The default mode of I C Bus is slave mode for an address match on the bus. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 369 2–0 select the shift register tap point (see Table 20-6) Table 20-4. I-Bus multiplier factor – IBC7 RESERVED Table 20-5. I-Bus prescaler divider values scl2start scl2stop scl2tap tap2tap – IBC5 (clocks) (clocks) (clocks) (clocks) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 370 20-5. The SCL Tap is used to generate the SCL period and the SDA Tap is used to determine the delay from the falling edge of SCL to the change of state of SDA i.e. the SDA hold time. SCL Divider SDA Hold Figure 20-4. SDA hold time MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 371 The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is: SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap] Eqn. 20-3 SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap] Eqn. 20-4 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 372 SCL hold SCL hold (hex) (clocks) (clocks) (start) (stop) 1024 1152 1280 1536 1920 1280 1536 1792 2048 1022 1025 2304 1150 1153 2560 1278 1281 3072 1534 1537 3840 1918 1921 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 373 1276 1282 3072 1532 1538 3840 1916 1922 2560 1276 1282 3072 1532 1538 3584 1788 1794 4096 2044 2050 4608 2300 2306 5120 2556 2562 6144 3068 3074 7680 3836 3842 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 374 3832 3844 5120 2552 2564 6144 3064 3076 7168 1028 3576 3588 8192 1028 4088 4100 9216 1540 4600 4612 10240 1540 5112 5124 12288 2052 6136 6148 15360 2052 7672 7684 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 375 1 No acknowledge signal response is sent (i.e., acknowledge bit = 1) 0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 376 Bus busy. This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal is detected, IBB is cleared and the bus enters idle state. 1 Bus is busy 0 Bus is Idle MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 377 For instance, if the I C is configured for master transmit but a master receive is desired, then reading the IBDR will not initiate the receive. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 378: Functional Description
Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer and STOP signal. They are described briefly in the following sections and illustrated in Figure 20-10. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 379 (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. START condition STOP condition Figure 20-11. Start and stop conditions MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 380 This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL is at logical “1” (see Figure 20-10). The master can generate a STOP even if the slave has generated an acknowledge, at which point the slave must release the bus. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 381 The first device to complete its high period pulls the SCL line low again. Start Counting High Period WAIT SCL1 SCL2 Internal Counter Reset Figure 20-12. I C bus clock synchronization MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 382: Interrupts
C Control Register. It must be cleared by writing ‘1’ to the IBIF bit in the interrupt service routine. The Bus Going Idle interrupt needs to be additionally enabled by the BIIE bit in the IBIC register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 383: Initialization/Application Information
The TCF bit will be cleared to indicate data transfer in progress whenever data register is written to in transmit mode, or during reading out from data register in receive mode. The TCF bit should not be used MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 384 — Address Detect has occurred (IAAS = 1) - determination of Slave mode. 5. Clear IBIF. 6. Wait until IBSR[TCF] bit gets cleared (that is, "Transfer under Progress" condition is reached for data transfer). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 385 START signal followed by another slave address without first generating a STOP signal. A program example is as shown. bit 2, IBCR = 1// generate another start ( restart) IBDR == calling_address// transmit the calling address MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 386 STOP condition, generate an interrupt to CPU and set the IBAL to indicate that the attempt to engage the bus is failed. When considering these cases, the slave service routine should test the IBAL first and the software should clear the IBAL bit if it is set. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 387 Rx Mode Mode Read Data Dummy Read Generate Dummy Read Dummy Read From IBDR From IBDR Stop Signal From IBDR From IBDR And Store Figure 20-13. Flow-Chart of Typical I C Interrupt Routine MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 388: Introduction
4-byte buffer for reception, 4-byte buffer for transmission • 8-bit counter for timeout management 21.2.3 Features common to LIN and UART • Fractional baud rate generator 1. Only LINFlex0 supports slave mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 389: General Description
Configure LIN parameters (for example, baud rate or mode) • Request transmissions • Handle receptions • Manage interrupts • Configure LIN error and timeout detection • Process diagnostic information The message buffer stores transmitted or received LIN frames. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 390: Fractional Baud Rate Generation
Figure 21-2. LINFlex block diagram 21.4 Fractional baud rate generation The baud rates for the receiver and transmitter are both set to the same value as programmed in the Mantissa (LINIBRR) and Fraction (LINFBRR) registers. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 391 / Desired / Desired LINIBRR LINFBRR baud rate LINIBRR LINFBRR baud rate 2400 2399.97 1666 –0.001 2399.88 –0.005 9600 9599.52 –0.005 9598.08 –0.02 10417 10416.7 –0.003 10416.7 –0.003 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 392: Operating Modes
LINFlex is in Sleep mode to reduce power consumption. The software instructs LINFlex to enter Initialization mode or Sleep mode by setting the INIT bit or SLEEP bit in the LINCR1. RESET SLEEP INITIALIZATION NORMAL Figure 21-3. LINFlex operating modes MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 393: Initialization Mode
Loop Back mode LINFlex can be put in Loop Back mode by setting the LBKM bit in the LINCR. In Loop Back mode, the LINFlex treats its own transmitted messages as received messages. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 394: Self Test Mode
Memory map and registers description 21.7.1 Memory map See the “Memory map” chapter of this reference manual for the base addresses for the LINFlex modules. Table 21-2 shows the LINFlex memory map. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 395 408 0x0078 Identifier filter control register 11 (IFCR11) on page 408 0x007C Identifier filter control register 12 (IFCR12) on page 408 0x0080 Identifier filter control register 13 (IFCR13) on page 408 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 396 LASE LIN Slave Automatic Resynchronization Enable 0 Automatic resynchronization disable. 1 Automatic resynchronization enable. Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 397 INIT Initialization Request The software sets this bit to switch hardware into Initialization mode. If the SLEEP bit is reset, LINFlex enters Normal mode when clearing the INIT bit (see Table 21-6). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 398 0111 17-bit 1000 18-bit 1001 19-bit 1010 20-bit 1011 21-bit 1100 22-bit 1101 23-bit 1110 36-bit 1111 50-bit Table 21-6. Operating mode selection SLEEP INIT Operating mode Sleep (reset value) Initialization Normal MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 399 0 No interrupt on LIN state change. 1 Interrupt generated on LIN state change. This interrupt can be used for debugging purposes. It has no status flag but is reset when writing ‘1111’ into LINS[0:3] in the LINSR. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 400 1 Interrupt generated when a valid LIN header has been received, that is, HRF bit in LINSR is set. 21.7.1.3 LIN status register (LINSR) Offset: 0x0008 Access: User read/write Reset LINS RBSY RPS WUF DBFF DBEF DRF DTF HRF Reset Figure 21-8. LIN status register (LINSR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 401 0 Receiver is idle 1 Reception ongoing Note: In Slave mode, after header reception, if BIDR[DIR] = 0 and reception starts then this bit is set. In this case, user cannot program LINCR2[DTRQ] = 1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 402 Note: If filters are enabled, this bit is set only when identifier software filtering is required, that is to say: • All filters are inactive and BF bit in LINCR1 is set • No match in any filter and BF bit in LINCR1 is set • TX filter match MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 403 This bit is set by hardware and indicates that a Identifier Parity error occurred. Note: Header interrupt is triggered when SFEF or BDEF or IDPEF bit is set and HEIE bit in LINIER is set. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 404 UART bit is set. RDFL[0:1] = Receive buffer size – 1. 00 Receive buffer size = 1. 01 Receive buffer size = 2. 10 Receive buffer size = 3. 11 Receive buffer size = 4. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 405 UART mode status register (UARTSR) Offset: 0x0014 Access: User read/write Reset R SZF OCF PE3 PE0 RMB FEF BOF RPS WUF DRF DTF W w1c Reset Figure 21-11. UART mode status register (UARTSR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 406 LINRX pin in Sleep mode. This bit must be cleared by software. It is reset by hardware in Initialization mode. An interrupt i generated if WUIE bit in LINIER is set. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 407 Idle on Timeout 0 LIN state machine not reset to Idle on timeout event. 1 LIN state machine reset to Idle on timeout event. This bit can be set/cleared in Initialization mode only. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 408 These bits contain the value to be compared to the value of bits CNT[0:7] in LINTCSR. Output compare 1 value These bits contain the value to be compared to the value of bits CNT[0:7] in LINTCSR. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 409 This field can be written only in Slave mode. 21.7.1.10 LIN fractional baud rate register (LINFBRR) Offset: 0x0024 Access: User read/write Reset DIV_F Reset Figure 21-15. LIN fractional baud rate register (LINFBRR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 410 This field defines the LINFlex divider (LFDIV) mantissa value (see Table 21-17). This field can be written in Initialization mode only. Table 21-17. Integer baud rate selection DIV_M[0:12] Mantissa 0x0000 LIN clock disabled 0x0001 0x1FFE 8190 ox1FFF 8191 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 411 Field Description IOBE Idle on Bit Error 0 Bit error does not reset LIN state machine. 1 Bit error reset LIN state machine. This bit can be set/cleared in Initialization mode only. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 412 Cleared by hardware when the request has been completed or aborted. This bit has no effect in UART mode. 21.7.1.14 Buffer identifier register (BIDR) Offset: 0x0034 Access: User read/write Reset DIR CCS Reset Figure 21-19. Buffer identifier register (BIDR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 413 Figure 21-20. Buffer data register LSB (BDRL) Table 21-21. BDRL field descriptions Field Description DATA3 Data Byte 3 Data byte 3 of the data field. DATA2 Data Byte 2 Data byte 2 of the data field. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 414 Data Byte 6 Data byte 6 of the data field. DATA5 Data Byte 5 Data byte 5 of the data field. DATA4 Data Byte 4 Data byte 4 of the data field. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 415 Filters 8 and 9 are activated. FACT[5] Filters 10 and 11 are deactivated. Filters 10 and 11 are activated. FACT[6] Filters 12 and 13 are deactivated. Filters 12 and 13 are activated. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 416 SRAM (see Section 21.8.2.2, Slave mode for more details). When no filter matches, IFMI[0:4] = 0. When Filter n is matching, IFMI[0:4] = n + 1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 417 Filters 10 and 11 are in mask mode (filter 11 is the mask for the filter 10). IFM[6] Filters 12 and 13 are in identifier list mode. Filters 12 and 13 are in mask mode (filter 13 is the mask for the filter 12). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 418 0 Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN specification 2.0 and higher. 1 Classic Checksum covering Data fields only. This is compatible with LIN specification 1.3 and earlier. Identifier Identifier part of the identifier field without the identifier parity. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 419 0 Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN specification 2.0 and higher. 1 Classic Checksum covering Data field only. This is compatible with LIN specification 1.3 and earlier. Identifier Identifier part of the identifier field without the identifier parity MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 420: Functional Description
Figure 21-28. UART mode 9-bit data frame 21.8.1.1 Buffer in UART mode The 8-byte buffer is divided into two parts: one for receiver and one for transmitter as shown in Table 21-30. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 421 In this case the latest message is always available to the application. • If the buffer lock function is enabled (LINCR1[RBLM] = 1) the most recent message is discarded and the previous message is available in the buffer. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 422: Lin Mode
If the response has been sent successfully, the LINSR[DTF] bit is set. In case of error, the DTF flag is not set and the corresponding error flag is set in the LINESR (see Section 21.8.2.1.6, Error handling). 1. Only LINFlex0 supports slave mode MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 423 An interrupt is generated if LINIER[FEIE] = 1. During reception, a Checksum Error leads LINFlex to discard the received frame. LINFlex returns to idle state. An interrupt is generated if LINIER[CEIE] = 1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 424 Typically, the application has to copy the data from the BDAR to SRAM locations. To copy the data to the right location, the application has to identify the data by means of the identifier. To avoid this and to ease MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 425 If a valid Break Field and Break Delimiter come before the end of the current header or at any time during a data field, the current header or data is discarded and the state machine synchronizes on this new break. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 426 In mask mode, the identifier registers are associated with mask registers specifying which bits of the identifier are handled as “must match” or as “don’t care”. For the bit mapping and registers organization, please see Figure 21-29. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 427 Table 21-31. Filter to interrupt vector correlation Number of Number of active filters Number of active filters Interrupt vector active filters configured as TX configured as RX RX interrupt on all identifiers MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 428 SM (not user accessible) (see Figure 21-31). Then the LFDIV value (and its associated registers LINIBRR and LINFBRR) are automatically updated at the end of the fifth falling edge. During MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 429 If D2 < 15.62%, LHE is not set. • If 15.62% < D2 < 18.75%, LHE can be either set or reset depending on the dephasing between the signal on LINFlex_RX pin the f clock. periph_set_1_clk MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 430: Bit Timeout Counter
On the checksum reception or in case of error in the header or response, the TOCE bit is reset. If there is no response, frame timeout value does not take into account the DFL value, and an 8-byte response (DFL = 7) is always assumed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 431 Programming LINTCSR[LTOM] = 0 enables the output compare mode. This mode allows the user to fully customize the use of the counter. OC1 and OC2 output compare values can be updated in the LINTOCR by software. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 432: Interrupts
In Slave mode, if at least one filter is configured as TX and enabled, header received interrupt vector is RXI or TXI depending on the value of identifier received. For debug and validation purposes MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 433 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 434: Introduction
EMI environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module is a full implementation of the CAN protocol specification, version 2.0 B, which supports both standard and extended message frames. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 435: Flexcan Module Features
Global network time, synchronized by a specific message • Maskable interrupts • Independent of the transmission medium (an external transceiver is assumed) • Short latency time due to an arbitration scheme for high-priority messages • Low power mode MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 436: Modes Of Operation
External signal description 22.2.1 Overview The FlexCAN module has two I/O signals connected to the external MCU pins. These signals are summarized in Table 22-1 and described in more detail in the next subsections. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 437: Signal Descriptions
FlexCAN is configured with 64 MBs. When it is configured with 16 MBs, the memory sizes are 288 and 64 bytes, so the address ranges 0x0180–0x047F and 0x08C0–0x097F are considered reserved space. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 438 450 The FlexCAN module stores CAN messages for transmission and reception using a Message Buffer structure. Each individual MB is formed by 16 bytes mapped on memory as described in Table 22-3. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 439: Message Buffer Structure
0 = Dominant is not a valid value for transmission in Extended Format frames ID Extended Bit This bit identifies whether the frame format is standard or extended. 1 = Frame format is extended 0 = Frame format is standard MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 440 MB does not participate in the matching process. 0100 EMPTY: MB is active and 0010 MB participates in the matching process. When empty. a frame is received successfully, the code is automatically updated to FULL. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 441 Transmit data frame unconditionally once. After transmission, the MB automatically returns to the INACTIVE state. 1100 0100 Transmit remote frame unconditionally once. After transmission, the MB automatically becomes an Rx MB with the same ID. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 442: Rx Fifo Structure
ID table can assume, depending on the IDAM field of the MCR. Note that all elements of the table must have the same format. See Section 22.4.8, “Rx FIFO for more information. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 443 (Standard = 18-28, Extended = 18-31) RXIDC_0 RXIDC_1 RXIDC_2 RXIDC_3 (Std/Ext = 0-7) (Std/Ext = 8-15) (Std/Ext = 16-23) (Std/Ext = 24-31) = Unimplemented or Reserved Figure 22-4. ID Table 0 – 7 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 444: Register Description
This register defines global system configurations, such as the module operation mode (e.g., low power) and maximum message buffer configuration. This register can be accessed at any time, however some fields must be changed only during Freeze Mode. Find more information in the fields descriptions ahead. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 445 (0x80–0xFF) is used by the FIFO engine. See Section 22.3.3, “Rx FIFO structure Section 22.4.8, “Rx FIFO for more information. This bit must be written in Freeze mode only. 1 = FIFO enabled 0 = FIFO not enabled MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 446 1 = Affected registers are in Supervisor memory space. Any access without supervisor permission behaves as though the access was done to an unimplemented register location 0 = Affected registers are in Unrestricted memory space MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 447 This feature guarantees a safe procedure for aborting a pending transmission, so that no frame is sent in the CAN bus without notification. This bit must be written in Freeze mode only. 1 = Abort enabled 0 = Abort disabled MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 448 This register can be accessed at any time, however some fields must be changed only during either Disable Mode or Freeze Mode. Find more information in the fields descriptions ahead. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 449 1= Bus Off interrupt enabled 0 = Bus Off interrupt disabled ERR_MSK Error Mask This bit provides a mask for the Error Interrupt. 1 = Error interrupt enabled 0 = Error interrupt disabled MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 450 1 = Three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples, a majority rule is used 0 = Just one sample is used to determine the bit value MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 451 The timer is clocked by the FlexCAN bit-clock (which defines the baud rate on the CAN bus). During a message transmission/reception, it increments by one for each bit that is received or transmitted. When MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 452 RXGMASK on filtering process for Rx FIFO. The contents of this register must be programmed while the module is in Freeze Mode, and must not be modified when the module is transmitting or receiving frames. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 453 It must be programmed while the module is in Freeze Mode, and must not be modified when the module is transmitting or receiving frames. • Address Offset: 0x14 • Reset Value: 0xFFFF_FFFF MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 454 128th occurrences of 11 consecutive recessive bits on the bus. Hence, TX_ERR_COUNTER is reset to zero and counts in a manner where the internal counter counts 11 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 455 Most bits in this register are read only, except TWRN_INT, RWRN_INT, BOFF_INT, WAK_INT and ERR_INT, that are interrupt flags that can be cleared by writing ‘1’ to them (writing ‘0’ has no effect). See Section 22.4.11, “Interrupts for more details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 456 Note: This bit is not set by a transmitter in case of arbitration field or ACK slot, or in case of a node sending a passive error flag that detects dominant bits. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 457 LOM bit in the Control Register is asserted, the FLT_CONF field will indicate “Error Passive”. Since the Control Register is not affected by soft reset, the FLT_CONF field will not be affected by soft reset if the LOM bit is asserted. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 458 (i.e. when the corresponding IFLAG2 bit is set). Offset: 0x0024 Access: Read/write R BUF Reset R BUF Reset Figure 22-11. Interrupt Masks 2 Register (IMASK2) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 459 22.3.4.11 Interrupt Flags 2 Register (IFLAG2) This register defines the flags for 32 Message Buffer interrupts. It contains one interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding IFLAG2 bit. If the corresponding MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 460 When the FEN bit in the MCR is set (FIFO enabled), the function of the 8 least significant interrupt flags (BUF7I – BUF0I) is changed to support the FIFO operation. BUF7I, BUF6I and BUF5I indicate operating conditions of the FIFO, while BUF4I to BUF0I are not used. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 461 Message Buffer, providing ID masking capability on a per Message Buffer basis. When the FIFO is enabled (FEN bit in MCR is set), the first 8 Mask MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 462: Functional Description
ID programmed on its ID field. A masking scheme makes it possible to match the ID programmed on the MB with a range of IDs on received CAN frames. For transmission, an arbitration algorithm decides MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 463: Local Priority Transmission
At the end of the successful transmission, the value of the Free Running Timer is written into the Time Stamp field, the Code field in the Control and Status word is MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 464: Arbitration Process
1. Actually, if LBUF is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the ID at the same positions they are transmitted in the CAN frame. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 465: Receive Process
MB, the MB is actually deactivated from any currently ongoing matching process. As a result, a newly received frame matching the ID of that MB may be lost. In summary: never do polling by reading directly the C/S word of the MBs. Instead, read the IFLAG registers. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 466: Matching Process
ID. Let us say that these MBs are the second and the fifth in the array. When the first message arrives, the matching algorithm will find the first match in MB number 2. The code MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 467: Data Coherence
MB is not deactivated, but the abort request is captured and kept pending until one of the following conditions are satisfied: • The module loses the bus arbitration MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 468 MBs have a matching ID to a received frame, and the user deactivated the first matching MB after FlexCAN has scanned the second. The received frame will be lost even if the second matching MB was “free to receive”. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 469 MB until the BUSY bit is negated. 1. In previous FlexCAN versions, reading the C/S word locked the MB even if it was EMPTY. This behavior will be honored when the BCC bit is negated. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 470: Rx Fifo
RXIMR are not available for the particular MCU), then the FIFO filter table is affected by the legacy mask registers as follows: element 6 is affected by RX14MASK, element 7 is affected by RX15MASK and the other elements (0 to 5) are affected by RXGMASK. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 471: Can Protocol Related Features
“move-in” in the TIME STAMP field, providing network behavior with respect to time. Note that the Free Running Timer can be reset upon a specific frame reception, enabling network time synchronization. Refer to TSYN description in Section 22.3.4.2, “Control Register (CTRL). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 472 Register so that their sum (plus 2) is in the range of 4 to 16 time quanta 1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 473 Resynchronization jump Time segment 1 Time segment 2 width 5 .. 10 1 .. 2 4 .. 11 1 .. 3 5 .. 12 1 .. 4 6 .. 13 1 .. 4 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 474 There must be a minimum ratio between the peripheral clock frequency and the CAN bit rate, as specified in Table 22-21 Table 22-21. Minimum ratio between peripheral clock frequency and CAN bit rate Number of message buffers Minimum ratio MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 475: Modes Of Operation Details
FRZ_ACK bit. If the module is disabled during transmission or reception, FlexCAN does the following: • Waits to be in either Idle or Bus Off state, or else waits for the third bit of Intermission and then checks it to be recessive MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 476: Interrupts
MCR. 22.4.12 Bus interface The CPU access to FlexCAN registers are subject to the following rules: • Read and write access to supervisor registers in User Mode results in access error. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 477: Initialization/Application Information
The Tx pin is in recessive state and FlexCAN does not initiate any transmission or reception of CAN frames. Note that the Message Buffers and the Rx Individual Mask Registers are not affected by reset, so they are not automatically initialized. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 478: Flexcan Addressing And Sram Size Configurations
MAXMB field in the MCR. For 16 MB configuration, MAXMB can be any number between 0–15. For 32 MB configuration, MAXMB can be any number between 0–31. For 64 MB configuration, MAXMB can be any number between 0 – MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 479 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 480: Introduction
MCU and an external peripheral device. The MPC5604B has three identical DSPI modules (DSPI_0, DSPI_1 and DSPI_2). The “x” appended to signal names signifies the module to which the signal applies. Thus CS0_x specifies that the CS0 signal applies to DSPI module 0, 1, etc.
Page 481: Features
— Continuously held chip select capability • Up to 6 peripheral chip selects, expandable to 64 with external demultiplexer • Deglitching support for up to 32 peripheral chip selects with external demultiplexer • 6 interrupt conditions: MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 482: Modes Of Operation
DSPI is stopped while in module disable mode. The DSPI enters the module disable mode when the MDIS bit in DSPIx_MCR is set. For more information, see Section 23.6.1.3, Module Disable mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 483: Debug Mode
When the pin is used for DSPI master mode as a chip select output, set the OBE bit. When the pin is used in DSPI slave mode as a slave select input, set the IBE bit. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 484 SOUT_x is a serial data output signal. 23.4.2.7 Serial Clock (SCK_x) SCK_x is a serial communication clock signal. In master mode, the DSPI generates the SCK. In slave mode, SCK_x is an input from an external bus master. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 485: Memory Map And Register Description
493 0x80 DSPI Receive FIFO Register 1 (DSPIx_RXFR1) on page 493 0x84 DSPI Receive FIFO Register 2 (DSPIx_RXFR2) on page 493 0x88 DSPI Receive FIFO Register 3 (DSPIx_RXFR3) on page 493 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 486: Dspi Module Configuration Register (Dspix_Mcr)
Note: If the FIFO is enabled with continuous SCK mode, the TX-FIFO should be cleared before setting the CONT_SCKE bit, and only the CTAR0 register should be used to transfer attributes; otherwise, a change in SCK frequency occurs. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 487 Determines the inactive state of the CS0_x signal. CS0_x must be configured as inactive high for slave mode operation. 0 The inactive state of CS0_x is low 1 The inactive state of CS0_x is high MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 488 Provides a mechanism for software to start and stop DSPI transfers. See Section 23.6.2, Start and stop of DSPI transfers, for details on the operation of this bit. 0 Start transfers 1 Stop transfers MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 489: Dspi Transfer Count Register (Dspix_Tcr)
• MSB or LSB first DSPIx_CTARs support compatibility with the QSPI module in the MPC5604B family of MCUs. At the initiation of an SPI transfer, control logic selects the DSPIx_CTAR that contains the transfer’s attributes. Do not write to the DSPIx_CTARs while the DSPI is running.
Page 490 DSPI can cause errors in the transfer due to the peripheral device interpreting the switch of clock polarity as a valid clock edge. 0 The inactive state value of SCK is low 1 The inactive state value of SCK is high MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 491 PCS. This field is only used in Master Mode. The table below lists the prescaler values. See the ASC[0:3] field description for details on how to compute the After SCK delay. PASC After SCK delay prescaler value MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 492 After SCK Delay is a multiple of the system clock period, and it is computed according to the following equation:   ---------- - Eqn. 23-2 PASC Section 23.6.4.3, After SCK delay (tASC),” for more details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 493 43/57 50/50 66/33 60/40 57/43 Table 23-7. DSPI transfer frame size FMSZ Frame size FMSZ Frame size 0000 Reserved 1000 0001 Reserved 1001 0010 Reserved 1010 0011 1011 0100 1100 0101 1101 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 494 Table 23-10. DSPI delay after transfer scaler Delay after transfer scaler Delay after transfer scaler value value 0000 1000 0001 1001 1024 0010 1010 2048 0011 1011 4096 0100 1100 8192 0101 1101 16384 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 495 50/50 50/50 33/66 40/60 43/57 50/50 66/33 60/40 57/43 Table 23-13. DSPI transfer frame size FMSZ Frame size FMSZ Frame size 0000 Reserved 1000 0001 Reserved 1001 0010 Reserved 1010 0011 1011 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 496 32768 0111 1111 65536 Table 23-16. DSPI delay after transfer scaler Delay after transfer scaler Delay after transfer scaler value value 0000 1000 0001 1001 1024 0010 1010 2048 0011 1011 4096 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 497: Dspi Status Register (Dspix_Sr)
Module Disable mode due to the use of power saving mechanisms. Offset: 0x2C Access: R/W TFUF TFFF W w1c Reset TXCTR TXNXTPTR RXCTR POPNXTPTR Reset Figure 23-6. DSPI Status Register (DSPIx_SR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 498 Indicates that an overflow condition in the RX FIFO has occurred. The bit is set when the RX FIFO and shift register are full and a transfer is initiated. 0 RX FIFO overflow has not occurred 1 RX FIFO overflow has occurred MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 499: Dspi Interrupt Request Enable Register (Dspix_Rser)
23.5.6 DSPI Interrupt Request Enable Register (DSPIx_RSER) The DSPIx_RSER enables flag bits in the DSPIx_SR to generate interrupt requests. Do not write to the DSPIx_RSER while the DSPI is running. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 500 Selects an interrupt request. When the TFFF flag bit in the DSPIx_SR is set, and the TFFF_RE bit in the DSPIx_RSER is set, this bit selects an interrupt request. 0 Interrupt request is selected 1 Reserved MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 501: Dspi Push Tx Fifo Register (Dspix_Pushr)
Write accesses of 8 or 16 bits to the DSPIx_PUSHR transfers 32 bits to the TX FIFO. NOTE TXDATA is used in master and slave modes. Offset:0x34 Access: Read/write CTAS Reset TXDATA Reset Figure 23-8. DSPI PUSH TX FIFO Register (DSPIx_PUSHR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 502 SPI_TCNT field in the DSPIx_TCR. The SPI_TCNT field is cleared before transmission of the current SPI frame begins. 0 Do not clear SPI_TCNT field in the DSPIx_TCR 1 Clear SPI_TCNT field in the DSPIx_TCR Note: Use in SPI master mode only. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 503: Dspi Pop Rx Fifo Register (Dspix_Popr)
Figure 23-9. DSPI POP RX FIFO Register (DSPIx_POPR) Table 23-21. DSPIx_POPR field descriptions Field Description RXDATA Received data The RXDATA field contains the SPI data from the RX FIFO entry pointed to by the pop next data pointer (POPNXTPTR). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 504: Dspi Transmit Fifo Registers 0–3 (Dspix_Txfrn)
RX FIFO. The DSPIx_RXFR registers are read-only. Reading the DSPIx_RXFRn registers does not alter the state of the RX FIFO. The device uses four registers to implement the RX FIFO, that is DSPIx_RXFR0–DSPIx_RXFR3 are used. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 505: Functional Description
At the end of a transfer, the TCF bit in the DSPIx_SR is set to indicate a completed transfer. Figure 23-12 illustrates how master and slave data is exchanged. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 506: Modes Of Operation
FIFO entry. The CTAS field in the SPI command selects which of the eight DSPIx_CTARs are used to set the transfer attributes. Transfer attribute control is on a frame by frame basis. Section 23.6.3, Serial peripheral interface (SPI) configuration for more details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 507: Start And Stop Of Dspi Transfers
The TXRXS bit in the DSPIx_SR is cleared in this state. In the RUNNING state, serial transfers take place. The TXRXS bit in the DSPIx_SR is set in the RUNNING state. Figure 23-13 shows a state diagram of the start and stop mechanism. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 508: Serial Peripheral Interface (Spi) Configuration
RX FIFO to memory external to the DSPI. The FIFO buffer operations are described in Section 23.6.3.4, Transmit First In First Out (TX FIFO) buffering mechanism, and Section 23.6.3.5, Receive First In First Out (RX FIFO) buffering mechanism. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 509 Disable the TX and RX FIFOs only if the FIFO must be disabled as a requirement of the application's operating mode. A FIFO must be disabled before it is accessed. Failure to disable a FIFO prior to a first FIFO access is not supported, and can result in incorrect results. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 510 SPI data frames. SPI data is added to the RX FIFO at the completion of a transfer when the received data in the shift register is transferred into the RX FIFO. SPI data is removed (popped) from the RX FIFO by MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 511: Dspi Baud Rate And Clock Delay Generation
The SCK_x frequency and the delay values for serial transfer are generated by dividing the system clock frequency by a prescaler and a scaler with the option of doubling the baud rate. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 512 CS to SCK_x delay. Table 23-26. CS to SCK delay computation example PCSSCK Prescaler value CSSCK Scaler value CS to SCK delay 0b01 0b0100 64 MHz 1.5 µs MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 513 When the DSPI is in master mode and PCSSE bit is set in the DSPIx_MCR, CS5_x provides a signal for an external demultiplexer to decode the CS4_x signals into as many as 32 glitch-free CSx signals. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 514: Transfer Formats
When the DSPI is the bus master, the CPOL and CPHA bits in the DSPI clock and transfer attributes registers (DSPIx_CTARn) select the polarity and phase of the serial clock, SCK_x. The polarity bit selects MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 515 Section 23.6.5.4, Modified SPI transfer format (MTFE = 1, CPHA = In the SPI configuration, the DSPI provides the option of keeping the CS signals asserted between frames. Section 23.6.5.5, Continuous selection format for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 516 For the CPHA = 0 condition of the slave, TCF is set and the RXCTR counter is updated at the last serial clock edge of the frame (edge 16) of Figure 23-16. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 517 For CPHA = 1 the master EOQF and TCF and slave TCF are set at the last serial clock edge (edge 16) of Figure 23-17. For CPHA = 1 the master and slave RXCTR counters are updated on the same clock edge. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 518 Table 23-31. Delayed master sample point Number of system clock cycles between odd-numbered edge of SCK and SMPL_PT sampling of SIN Invalid value MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 519 SCK. No clock edge is visible on the master SCK pin during the sampling of the last bit. The SCK to CS delay must be greater or equal to half of the SCK period. NOTE For the modified transfer format to operate correctly, you must thoroughly analyze the SPI link timing budget. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 520 When the CONT bit = 0, the DSPI drives the asserted chip select signals to their idle states in between frames. The idle states of the chip select signals are selected by the PCSIS field in the DSPIx_MCR. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 521 Switching CTARs between frames while using continuous selection can cause errors in the transfer. The CS signal must be negated before CTAR is switched. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 522: Continuous Serial Communications Clock
Continuous SCK is only supported for CPHA = 1. Setting CPHA = 0 is ignored if the CONT_SCKE bit is set. Continuous SCK is supported for modified transfer format. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 523 If the CONT bit in the TX FIFO entry is set, CS remains asserted between the transfers when the CS signal for the next transfer is the same as for the current transfer. Figure 23-24 shows timing diagram for continuous SCK format with continuous selection enabled. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 524 (CPOL = 0) (CPOL = 1) Master SOUT Master SIN Transfer 1 Transfer 2 Figure 23-24. Continuous SCK timing diagram (CONT=1) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 525: Interrupt Requests
TCF_RE bit is set in the DSPIx_RSER. See the TCF bit description in Section 23.5.5, DSPI Status Register (DSPIx_SR). See Figure 23-16 Figure 23-17 that illustrate when TCF is set. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 526: Power Saving Features
In the module disable mode, all status bits and register flags in the DSPI return the correct values when read, but writing to them has no affect. Writing to the MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 527: Initialization And Application Information
PBR and the baud rate scaler BR in the DSPIx_CTARs. The values are calculated at a 64 MHz system frequency. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 528 3.12 kHz 2.23 kHz 4096 3.90 kHz 2.60 kHz 1.56 kHz 1.11 kHz 8192 1.95 kHz 1.31 kHz 781 Hz 558 Hz 16384 979 Hz 653 Hz 390 Hz 279 Hz 32768 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 529: Delay Settings
The pointer to the first-in entry in each FIFO is memory mapped. For the TX FIFO the first-in pointer is the transmit next pointer (TXNXTPTR). For the RX FIFO the first-in pointer is the pop next pointer (POPNXTPTR). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 530 The memory address of the last-in entry in the RX FIFO is computed by the following equation: Last-in entry address = RXFIFO base + 4 [(RXCTR + POPNXTPTR - 1) modulo RXFIFO depth] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 531 RXFIFO base = base address of receive FIFO RXCTR = receive FIFO counter POPNXTPTR = pop next pointer RX FIFO depth = receive FIFO depth, implementation specific MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 532: Timers
——— Timers ——— MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 533 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 534: Introduction
This section gives a technical overview of each of the timers as well as detailing the pins that can be used to access the timer peripherals if applicable. Figure 24-1 details the interaction between the timers and the eDMA, INTC, CTU, and ADC. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 535 There are 14 interrupt requests from the eMIOS to the INTC. eMIOS channels are routed to the interrupt controller in pairs for example CH[0,1] CH[2,3] Figure 24-1. Interaction between timers and relevant peripherals MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 536: Overview Of The Stm
The PWM trigger can then cause the CTU to perform a single ADC conversion which in turn measures the operating conditions of the LED to ensure it is working within specification. A watchdog feature on MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 537 PH[2] UC[20] PE[13] UC[5] PH[3] PH[11] UC[21] PE[14] UC[6] PH[4] UC[22] PE[15] UC[7] PH[5] UC[23] PG[0] UC[8] PH[6] UC[24] PG[1] UC[9] PH[7] UC[25] PF[12] UC[10] PH[8] UC[26] PF[13] UC[11] PG[2] UC[27] PF[14] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 538: Overview Of The Pit
The counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). 24.3.1.2 Features The STM has the following features: MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 539: External Signal Description
0x0024 STM Channel 1 Interrupt Register (STM_CIR1) on page 531 0x0028 STM Channel 1 Compare Register (STM_CMP1) on page 531 0x002C Reserved 0x0030 STM Channel 2 Control Register (STM_CCR2) on page 530 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 540 Counter Prescaler. Selects the clock divide value for the prescaler (1 - 256). 0x00 = Divide system clock by 1 0x01 = Divide system clock by 2 0xFF = Divide system clock by 256 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 541 STM Channel Control Register (STM_CCRn) The STM Channel Control Register (STM_CCRn) has the enable bit for channel n of the timer. Offset: 0x10+0x10*n Access: Read/Write Reset Reset Figure 24-4. STM Channel Control Register (STM_CCRn) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 542 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-6. STM Channel Compare Register (STM_CMPn) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 543: Functional Description
Features of the eMIOS module • 2 eMIOS blocks with 28 channels each — 50 channels with OPWMT, which can be connected to the CTU — 6 channels with single action IC/OC MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 544 If an unimplemented mode (reserved) is selected, the results are unpredictable such as writing a reserved value to MODE[0:6] in Section 24.4.3.2.8, eMIOS UC Control Register (EMIOSC[n]). 24.4.1.4 Channel implementation Figure 24-7 shows the channel configuration of the eMIOS blocks. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 545 Buffered Output Pulse Width Modulation with Trigger OPWFMB Buffered Output Pulse Width and Frequency Modulation OPWMCB Center Aligned Output PWM Buffered with Dead-Time SAIC Single Action Input Capture SAOC Single Action Output Compare Figure 24-7. Channel configuration MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 546: External Signal Description
539 0x010–0x01F Reserved — 0x020–0x11F Channel [0] — Channel [7] 0x120–0x21F Channel [8] — Channel [15] 0x220–0x31F Channel [16] — Channel [23] 0x320–0x39F Channel [24] — Channel [27] 0x3A0–0xFFF Reserved — MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 547 Puts the eMIOS in low power mode. The MDIS bit is used to stop the clock of the block, except the access to registers EMIOSMCR, EMIOSOUDIS and EMIOSUCDIS. 1 = Enter low power mode 0 = Clock is running MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 548 The EMIOSGFLAG is a read-only register that groups the flag bits (F[27:0]) from all channels. This organization improves interrupt handling on simpler devices. Each bit relates to one channel. For Unified Channels these bits are mirrors of the FLAG bits in the EMIOSS[n] register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 549 A2 to A1 and B2 to B1. Each bit controls one channel. 1 = Transfers disabled 0 = Transfer enabled. Depending on the operation mode, transfer may occur immediately or in the next period. Unless stated otherwise, transfer occurs immediately. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 550 EMIOSA[n]. Both A1 and A2 are cleared by reset. Figure 24-16 summarizes the EMIOSA[n] writing and reading accesses for all operation modes. For more information see Section 24.4.4.1.1, UC modes of operation. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 551 — DAOC — — — — OPWMT — — OPWFMB — — OPWMCB — — OPWMB — — In these modes, the register EMIOSB[n] is not used, but B2 can be accessed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 552 UC Control Register (EMIOSC[n]) The Control register gathers bits reflecting the status of the UC input/output signals and the overflow condition of the internal counter, as well as several read/write control bits. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 553 24-19. For output modes, these bits have no meaning. Filter Clock select bit The FCK bit selects the clock source for the programmable input filter. 1 = Main clock 0 = Prescaled clock MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 554 Mode selection The MODE field selects the mode of operation of the Unified Channel, as shown in Table 24-21. Note: If a reserved value is written to mode the results are unpredictable. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 555 General purpose Input/Output mode (output) 0000010 Single Action Input Capture 0000011 Single Action Output Compare 0000100 Input Pulse Width Measurement 0000101 Input Period Measurement 0000110 Double Action Output Compare (with FLAG set on B match) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 556 Section 24.4.4.1.1, UC modes of operation for details. 24.4.3.2.9 eMIOS UC Status Register (EMIOSS[n]) Address: UC[n] base address + 0x10 R OVR W w1c Reset UCIN W w1c Reset Figure 24-16. eMIOS UC Status Register (EMIOSS[n]) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 557 Please, see Section 24.4.4.1.1.1, General purpose Input/Output (GPIO) mode, Section 24.4.4.1.1.12, Output Pulse Width Modulation with Trigger (OPWMT) mode for a more detailed description of the use of EMIOSALTA[n] register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 558: Functional Description
UC for a new operation mode, writing to registers EMIOSA[n] or EMIOSB[n] stores the same value in registers A1/A2 or B1/B2, respectively. Writing to register EMIOSALTA[n] stores a value only in register A2. MODE[6] bit selects between input (MODE[6] = 0) and output (MODE[6] = 1) modes. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 559 0x001250 0x001525 0x0016A0 FLAG pin/register A2 (captured) value 0xxxxxxx 0x001000 0x001250 0x0016A0 Notes: 1. After input filter 2. EMIOSA[n] <= A2 Figure 24-18. Single action input capture with rising edge triggering example MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 560 Subsequent matches are enabled with no need of further writes to EMIOSA[n] register. The FLAG is set at the same time a match occurs (see Figure 24-22). NOTE The channel internal counter in SAOC mode is free-running. It starts counting as soon as the SAOC mode is entered. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 561 B2. When this leading edge is detected, the count value of the selected time base is latched into register B2; the FLAG bit is not set. When the trailing edge is detected, the count value of the MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 562 EMIOSA[n] read. The B1 register updates remains locked until EMIOSB[n] read occurs. If EMIOSA[n] read is performed B1 is updated with A1 register content even if B1 update is locked by a previous EMIOSA[n] read operation. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 563 B2 to B1, to take effect at the next edge capture. The input pulse period is calculated by subtracting the value in B1 from A2. Figure 24-25 shows how the Unified Channel can be used for input period measurement. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 564 When the DAOC mode is entered, coming out from GPIO mode both comparators are disabled and the output flip-flop is set to the complement of the EDPOL bit in the EMIOSC[n] register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 565 Notes: 1. EMIOSA[n] = A1 (when reading) 2. EMIOSB[n] = B1 (when reading) A2 = A1according to OU[n] bit B2 = B1according to OU[n] bit Figure 24-27. Double action output compare with FLAG set on the second match MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 566 The internal counter counts up from the current value until it matches the value in register A1. Register B1 is cleared and is not accessible to the MCU. Bit MODE[4] selects up mode or up/down mode, when cleared or set, respectively. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 567 Register B2 has no effect in MC mode. Nevertheless, register B2 can be accessed for reads and writes by addressing EMIOSB. Figure 24-30 Figure 24-31 show how the Unified Channel can be used as modulus counter in up mode and up/down mode, respectively. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 568 Bit MODE[6] selects internal clock source if cleared or external if set. When external clock is selected the input channel pin is used as the channel clock source. The active edge of this clock is defined by EDPOL and EDSEL bits in the EMIOSC[n] channel register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 569 If A2 is written in cycle n, this new value will be used in cycle n+1 for A1 match. Flags are generated only at A1 match start if MODE[5] is 0. If MODE[5] is set to 1 flags are also generated at the cycle boundary. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 570 Thus A1 receives this new value at the next cycle boundary. Note that the update disable bits OU[n] of EMIOSOUDIS register can be used to disable the update of A1 register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 571 4 counter periods after the cycle had started, plus one system clock cycle. Note that in the example shown in Figure 24-36 the internal counter prescaler has a ratio of two. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 572 This allows to use the A1 posedge match to mask the B1 negedge match when they occur at the same time. The result is that no transition occurs on the output flip-flop and a 0% duty cycle is generated. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 573 B2 data written on cycle n were loaded to A1 or B1, respectively, thus generating matches in cycle n+1. Note that the FLAG has a synchronous operation, meaning that it is asserted one system clock cycle after the FLAG set event. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 574 A 0% duty cycle signal is generated if A1 = 0x0 as shown in Figure 24-39 cycle 9. In this case B1 = 0x8 match from cycle 8 occurs at the same time as the A1 = 0x0 match from cycle 9. Please, refer to MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 575 11. [OPWMCB channel] Select time base input through BSL[1:0] bits; 12. [OPWMCB channel] Enter OPWMCB mode; 13. [OPWMCB channel] Set prescaler ratio; 14. [OPWMCB channel] Enable Channel Prescaler; 15. [global] Enable Global Prescaler. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 576 Center Aligned PWM signal. Note that both A1 and B1 register values are changing within the same cycle which allows to vary at the same time the duty cycle and dead time values. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 577 A1 and the selected time base, the internal counter is set to 0x1 and B1 matches are enabled. When the match between register B1 and the selected time base occurs the output flip-flop is set to the complement of the EDPOL bit. This sequence repeats continuously. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 578 FORCMA bit set does not set the internal time-base to 0x1 as a regular A1 match. The FLAG bit is not set either in case of a FORCMA or FORCMB or even if both forces are issued at the same time. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 579 100% duty cycle output signal generated by setting A1 = 4 and B1 = 3. In this case the trailing edge is positioned at the boundary of cycle n+1, which is actually considered to belong to cycle n+2 and therefore does not cause the output flip-flip to transition. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 580 A1 or B1 respectively. FLAG bit is not set by the FORCMA and FORCMB operations. At OPWMB mode entry the output flip-flop is set to the value of the EDPOL bit in the EMIOSC[n] register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 581 B1 = 0x8 negedge signal. In this case A1 match has precedence over B1 match, causing the output pin to remain at EDPOL bit value, thus generating a 0% duty cycle signal. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 582 EDPOL bit at B1 match. Note also that if B1 is set to 0x9, for instance, B1 match does not occur, thus a 0% duty cycle signal is generated. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 583 Note that the output pin and flag transitions are based on the posedges of the A1, B1 and A2 match signals. Please, refer to Figure 24-44 Section 24.4.4.1.1.11, Output Pulse Width Modulation Buffered (OPWMB) Mode for details on match posedge. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 584 EDPOL bit. The transfer from register B2 to B1 is still triggered by the match at comparator A. Figure 24-47 shows the Unified Channel running in OPWMT mode with Trigger Event Generation and duty cycle update on next period update. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 585 2. EMIOSB[n] = B2 for write, B1 for read Figure 24-48. OPWMT with 0% Duty Cycle Figure 24-49 shows the Unified Channel running in OPWMT mode with Trigger Event Generation and 100% duty cycle. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 586 At the next pin transition, the counter starts counting again. Any pulse that is shorter than a full range of the masked counter is regarded as a glitch and it is not passed on to the edge detector. A timing diagram of the input filter is shown in Figure 24-51. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 587 When exiting debug mode or freeze enable bit is cleared (FRZ in the EMIOSMCR or FREN in the EMIOSC[n] register) the channel actions resume, but may be inconsistent until channel enters GPIO mode again. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 588: Initialization/Application Information
EMIOSA[n] or EMIOSB[n]. When interrupts are enabled, the software must clear the FLAG bits before exiting the interrupt service routine. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 589 Figure 24-54. • If MC mode and Clear on Match End are selected the internal counter behaves as described in Figure 24-55. NOTE MCB and OPWFMB modes have a different behavior. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 590 FLAG clear Note 1: The match occurs only when the input event/prescaler clock enable is active. Then, the internal counter is immediately cleared. Figure 24-55. Time base generation with clear on match end MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 591: Periodic Interrupt Timer (Pit)
The flags can be configured at any time. 24.5 Periodic Interrupt Timer (PIT) 24.5.1 Introduction The PIT is an array of timers that can be used to raise interrupts. Figure 24-56 shows the PIT block diagram. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 592: Features
This section provides a detailed description of all registers accessible in the PIT module. 24.5.4.1 Memory map Table 24-23 gives an overview of the PIT registers. See the chip memory map for the PIT base address. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 593 Reserved registers will read as 0, writes will have no effect. 24.5.4.2 PIT Module Control Register (PITMCR) This register controls whether the timer clocks should be enabled and whether the timers should run in debug mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 594 Timer Load Value Register (LDVAL) This register selects the timeout period for the timer interrupts. Offset: channel_base + 0x00 Access: Read/Write TSV[31:16] Reset TSV[15:0] Reset Figure 24-58. Timer Load Value Register (LDVAL) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 595 Note: The timer values will be frozen in Debug mode if the FRZ bit is set in the PIT Module Control Register (see Figure 24-2). 24.5.4.5 Timer Control Register (TCTRL) This register contains the control bits for each timer. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 596 0 Timer will be disabled 1 Timer will be active 24.5.4.6 Timer Flag Register (TFLG) This register holds the PIT interrupt flags. Offset: channel_base + 0x0C Access: Read/Write Reset Reset Figure 24-61. Timer Flag Register (TFLG) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 597: Functional Description
This value will then be loaded after the next trigger event (see Figure 24-64). Timer Enabled Disable Re-Enable Start Value = p1 Timer Timer Trigger Event Figure 24-62. Stopping and starting a timer MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 598: Initialization And Application Information
5.12 ms/20 ns = 256000 cycles and Timer 3 every 30 ms/20 ns = 1500000 cycles. The value for the LDVAL register trigger would be calculated as (period / clock period) – 1. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 599 PIT_TCTRL1 = TIE; // enable Timer 1 interrupts PIT_TCTRL1 |= TEN; // start timer 1 // Timer 3 PIT_LDVAL3 = 0x0016E35F; // setup timer 3 for 1500000 cycles PIT_TCTRL3 = TEN; // start timer 3 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 600 ——— ADC system ——— MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 601 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 602: Overview
Conversions on external channels managed in the same way as internal channels, making it transparent to the application • One Shot/Scan Modes • Chain Injection Mode • Power-down mode • 2 different Abort functions allow to abort either single-channel conversion or chain conversion • Auto-clock-off MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 603: Device-Specific Implementation
The MA[0:2] are controlled by the ADC itself and are set automatically by the hardware. A conversion timing register for configuring different sampling and conversion times is associated to each channel type. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 604: Functional Description
MCR[EDGE] bit. EDGE = 0 means that the start of conversion is enabled if the signal is low. If EDGE = 1, the start of conversion is enabled when the signal is high. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 605 In One Shot Mode (MODE = 0) a sequential conversion specified in the NCMR registers is performed only once. At the end of each conversion, the digital result of the conversion is stored in the corresponding data register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 606 After the last channel in the injected chain is converted, normal conversion resumes from the channel at which the normal conversion was aborted as shown in Figure 25-3. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 607 In that case the behavior of the ADC depends on the MODE bit. If scan mode is disabled, the NSTART bit is automatically reset together with the MCR[ABORTCHAIN] bit. Otherwise, if the MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 608: Analog Clock Generator And Conversion Timings
INPSAMP are used to define the total conversion duration (T ) and in particular the partition between conv sampling phase duration (T ) and total evaluation phase duration (T sample eval 25.3.3.1 ADC_0 Figure 25-4 represents the sampling and conversion sequence. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 609 Clock eval conv conv INPSAMPLE Ndelay INPCMP INPLATCH sample sample (MHz) (s) (s) (s) 0.167 0.583 3.500 1.667 2.333 14.000 0.143 0.500 3.500 1.429 2.000 14.000 0.125 0.563 4.500 1.250 1.875 15.000 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 610: Adc Ctu (Cross Triggering Unit)
CTU triggered conversion proceeds. By aborting the injected conversion, the MSR[JSTART] is reset. That abort is signalled through the status bit MSR[JABORT]. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 611: Presampling
Figure 25-6. Presampling sequence with PRECONV = 1 25.3.5.2 Presampling channel enable signals It is possible to select between two internally generated voltages V0 and V1 depending on the value of the PSCR[PREVAL] as shown in Table 25-4. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 612: Programmable Analog Watchdog
THRL <= converted data <= THRH The channel on which the analog watchdog is to be applied is selected by the TRC[THRCH]. The analog watchdog is enabled by setting the corresponding TRC[THREN]. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 613: Interrupts
Status Register) and WTIMR (Watchdog Threshold Interrupt Mask Register) in order to check and enable the interrupt request to the INTC module. The Watchdog interrupt source sets two pending bits WDGxH and WDGxL in the WTISR for each of the channels being monitored. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 614: External Decode Signals Delay
“auto-clock-off” feature can be enabled by setting the MCR[ACKO] bit. When enabled, the analog clock is automatically switched off when no operation is ongoing, that is, no conversion is programmed by the user. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 615: Register Descriptions
619 0x0084 Presampling Register 0 (PSR0) on page 620 0x0088 Presampling Register 1 (PSR1) on page 620 0x008C Presampling Register 2 (PSR2) on page 620 0x0090 .. 0x0093 Reserved — MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 616 Channel 12 Data Register (CDR12) on page 628 0x0134 Channel 13 Data Register (CDR13) on page 628 0x0138 Channel 14 Data Register (CDR14) on page 628 0x013C Channel 15 Data Register (CDR15) on page 628 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 617 Channel 73 Data Register (CDR73) on page 628 0x0228 Channel 74 Data Register (CDR74) on page 628 0x022C Channel 75 Data Register (CDR75) on page 628 0x0230 Channel 76 Data Register (CDR76) on page 628 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 618: Control Logic Registers
Channel 95 Data Register (CDR95) on page 628 0x0280 .. 0x02FF Reserved — 25.4.2 Control logic registers 25.4.2.1 Main Configuration Register (MCR) The Main Configuration Register (MCR) provides configuration settings for the ADC. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 619 JSTART Injection start Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect, as the injected chain conversion cannot be interrupted. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 620 PWDN, resetting this bit starts ADC transition to IDLE mode. 0 ADC is in normal mode 1 ADC has been requested to power down 25.4.2.2 Main Status Register (MSR) The Main Status Register (MSR) provides status bits for the ADC. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 621 MSR[JSTART] is automatically set when the injected conversion starts. At the same time MCR[JSTART] is reset, allowing the software to program a new start of conversion. The JCMR registers do not change their values. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 622: Interrupt Registers
CEOCFR0 = End of conversion pending interrupt for channel 0 to 15 (precision channels) CEOCFR1 = End of conversion pending interrupt for channel 32 to 47 (standard channels) CEOCFR2 = End of conversion pending interrupt for channel 64 to 95 (external multiplexed channels) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 623 Access: User read/write Reset W w1c Reset Figure 25-11. Channel Pending Register 0 (CEOCFR0) Address: Base + 0x0018 Access: User read/write Reset W w1c Reset Figure 25-12. Channel Pending Register 1 (CEOCFR1) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 624 Interrupt Mask Register (IMR) The Interrupt Mask Register (IMR) contains the interrupt enable bits for the ADC. Address: Base + 0x0020 Access: User read/write Reset Reset Figure 25-14. Interrupt Mask Register (IMR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 625 CIMR1 = Enable bits for channel 32 to 47 (standard channels) CIMR2 = Enable bits for channel 64 to 95 (external multiplexed channels) Address: Base + 0x0024 Access: User read/write Reset R CIM Reset Figure 25-15. Channel Interrupt Mask Register 0 (CIMR0) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 626 R CIM Reset Figure 25-17. Channel Interrupt Mask Register 2 (CIMR2) Table 25-12. CIMR field descriptions Field Description CIMn Interrupt enable When set (CIMn = 1), interrupt for channel n is enabled. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 627 This corresponds to the status flag generated on the converted value being lower than the programmed lower threshold (for [x = 0..3]). 25.4.3.6 Watchdog Threshold Interrupt Mask Register (WTIMR) Address: Base + 0x0034 Access: User read/write Reset Reset Figure 25-19. Watchdog Threshold Interrupt Mask Register (WTIMR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 628 MSKWDGxL This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold (for [x = 0..3]). When set the interrupt is enabled. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 629: Threshold Registers
Figure 25-20. Threshold Control Register (TRCx, x = [0..3]) Table 25-15. TRCx field descriptions Field Description THREN Threshold enable When set, this bit enables the threshold detection feature for the selected channel. THRCH Choose the channel for threshold comparison. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 630: Presampling Registers
Low threshold value for channel n. 25.4.5 Presampling registers 25.4.5.1 Presampling Control Register (PSCR) Address: Base + 0x0080 Access: User read/write Reset PREVAL2 PREVAL1 PREVAL0 CONV Reset Figure 25-22. Presampling Control Register (PSCR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 631 Address: Base + 0x0084 Access: User read/write Reset R PRES PRES PRES PRES PRES PRES PRES PRES PRES PRES PRES PRES PRES PRES PRES PRES Reset Figure 25-23. Presampling Register 0 (PSR0) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 632 PRES PRES PRES PRES Reset Figure 25-25. Presampling Register 2 (PSR2) Table 25-18. PSR field descriptions Field Description PRESn Presampling enable When set (PRESn = 1), presampling is enabled for channel n. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 633: Mask Registers
INPSAMP Configuration bits for sampling phase duration 25.4.7 Mask registers 25.4.7.1 Introduction These registers are used to program which of the 96 input channels must be converted during Normal and Injected conversion. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 634 Address: Base + 0x00A8 Access: User read/write Reset CH47 CH46 CH45 CH44 CH43 CH42 CH41 CH40 CH39 CH38 CH37 CH36 CH35 CH34 CH33 CH32 Reset Figure 25-28. Normal Conversion Mask Register 1 (NCMR1) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 635 When set Sampling is enabled for channel n. NOTE The implicit channel conversion priority in the case in which all channels are selected is the following: ADC0_P[0:x], ADC0_S[0:y], ADC0_X[0:z]. The channels always start with 0, the lowest index. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 636 Address: Base + 0x00B8 Access: User read/write Reset CH47 CH46 CH45 CH44 CH43 CH42 CH41 CH40 CH39 CH38 CH37 CH36 CH35 CH34 CH33 CH32 Reset Figure 25-31. Injected Conversion Mask Register 1 (JCMR1) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 637 CH79 CH78 CH77 CH76 CH75 CH74 CH73 CH72 CH71 CH70 CH69 CH68 CH67 CH66 CH65 CH64 Reset Figure 25-32. Injected Conversion Mask Register 2 (JCMR2) Table 25-21. JCMR field descriptions Field Description Sampling enable When set, sampling is enabled for channel n. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 638: Delay Registers
DSD = 2; 1 ADC clock cycle delay DSD = 4; 2 ADC clock cycles delay 25.4.8.2 Power-down Exit Delay Register (PDEDR) Address: Base + 0x00C8 Access: User read/write Reset PDED Reset Figure 25-34. Power-down Exit Delay Register (PDEDR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 639: Data Registers
Each data register also gives information regarding the corresponding result as described below. Address: See Table 25-6 Access: User read/write OVER RESULT Reset CDATA[0:9] (MCR[WLSIDE] = 0) Reset CDATA[0:9] (MCR[WLSIDE] = 1) Reset Figure 25-35. Channel Data Register (CDR[0..95]) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 640 10 Data is a result of CTU conversion mode 11 Reserved CDATA Channel 0-95 converted data. Depending on the value of the MCR[WLSIDE] bit, the position of this bitfield can be changed as shown in Figure 25-35 Figure 25-35. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 641 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 642: Introduction
Figure 26-1. Cross Triggering Unit block diagram 26.4 Memory map and register descriptions The CTU registers are listed in Table 26-1. Every register can have 32-bit access. The base address of the CTU is 0xFFE6_4000. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 643 CLR_FLAG is used to clear the respective timer event flag by software (this applies only to the PIT as the eMIOS flags are automatically cleared by the CTU). The CLR_FLAG bit has to be used cautiously as setting this bit may result in a loss of events. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 644: Functional Description
0 Channel_12 eMIOS 0 Channel_13 eMIOS 0 Channel_14 eMIOS 0 Channel_15 eMIOS 0 Channel_16 eMIOS 0 Channel_17 eMIOS 0 Channel_18 eMIOS 0 Channel_19 eMIOS 0 Channel_20 eMIOS 0 Channel_21 eMIOS 0 Channel_22 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 645 1 Channel_12 eMIOS 1 Channel_13 eMIOS 1 Channel_14 eMIOS 1 Channel_15 eMIOS 1 Channel_16 eMIOS 1 Channel_17 eMIOS 1 Channel_18 eMIOS 1 Channel_19 eMIOS 1 Channel_20 eMIOS 1 Channel_21 eMIOS 1 Channel_22 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 646: Channel Value
Channel number in 10-bit ADC signal name 10-bit ADC channel # CTU_EVTCFGRx ADC_P[0] ADC_P[1] ADC_P[2] ADC_P[3] ADC_P[4] ADC_P[5] ADC_P[6] ADC_P[7] ADC_P[8] ADC_P[9] ADC_P[10] CH10 ADC_P[11] CH11 ADC_P[12] CH12 ADC_P[13] CH13 ADC_P[14] CH14 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 647 CTU channel mapping should be taken into consideration when programming an event configuration register. For example, if the channel value of any event configuration register is programmed to 16, it will actually correspond to ADC channel 32 and conversion will occur for this channel. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 648 ——— Memory ——— MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 649 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 650: Introduction
An electrical means for selectively adding (programming) and removing (erasing) charge from these elements • A means of selectively sensing (reading) the charge stored in these elements The flash memory module is arranged as two functional units: MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 651: Main Features
Commands to the FPEC are given through a User Registers Interface. The read data bus is 128 bits wide, while the flash memory registers are on a separate bus 32 bits wide addressed in the user memory map. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 652: Functional Description
The flash memory module uses an embedded hardware algorithm implemented in the Memory Interface to program and erase the flash memory core. The embedded hardware algorithm includes control logic that works with software block enables and software lock mechanisms to guard against accidental program/erase. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 653: Flash Memory Module Sectorization
Addresses Size (KB) space locking the address space 0x00000000–0x00007FFF LLK0 0x00008000–0x0000BFFF LLK1 0x0000C000–0x0000FFFF LLK2 0x00010000–0x00017FFF LLK3 0x00018000–0x0001FFFF LLK4 0x00020000–0x0003FFFF LLK5 0x00040000–0x0005FFFF MLK0 0x00060000–0x0007FFFF MLK1 Shadow 0x00200000–0x00203FFF Shadow TSLK Test 0x00400000–0x00403FFF Test TSLK MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 654: Testflash Block
A section of the TestFlash is reserved to store the nonvolatile information related to Redundancy, Configuration and Protection. The ECC is also applied to TestFlash. The structure of the TestFlash sector is detailed in Table 27-4 Table 27-5. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 655 The first 8 KB of TestFlash block may be used for user defined functions (possibly to store serial numbers, other configuration words or factory process codes). Locations of the TestFlash other than the first 8 KB of OTP area cannot be programmed by the user application. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 656: Shadow Sector
The main, shadow and test address space can be read only in the read state. The majority of CFlash and DFlash memory-mapped registers can be read even when the CFlash or DFlash is in power-down or low-power mode. The exceptions are as follows: MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 657: Reset
After reset is negated, read register access may be done, although it should be noted that registers that require updating from shadow information, or other inputs, may not read updated values until the DONE MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 658: Power-Down Mode
If the flash memory module enters low power mode during a program operation, the operation will be in any case completed and the low power mode will be entered only after the programming end. It is forbidden to enter power-down mode when the low power mode is active. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 659: Register Description
DFlash Module Configuration Register (DFLASH_MCR) on page 680 0x0004 DFlash Low/Mid Address Space Block Locking Register on page 685 (DFLASH_LML) 0x0008 Reserved — 0x000C DFlash Secondary Low/Mid Address Space Block Locking on page 689 Register (DFLASH_SLL) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 660: Cflash Register Description
PEG bit of the corresponding MCR (CFLASH_MCR or DFLASH_MCR). 27.5.1 CFlash register description 27.5.1.1 CFlash Module Configuration Register (CFLASH_MCR) The CFlash Module Configuration Register is used to enable and monitor all modify operations of the flash memory module. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 661 If EER is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of EER) were correct. 0: Reads are occurring normally. 1: An ECC Double Error occurred during a previous read. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 662 , time equals to Erase Suspend Latency) after a 0 to 1 ESUS transition of ESUS, which suspends an erase operation. 0: Flash memory is executing a high voltage operation. 1: Flash memory is not executing a high voltage operation. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 663 ERS can be cleared by the user only when ESUS and EHV are low and DONE is high. ERS is cleared on reset. 0: Flash memory is not executing an erase sequence. 1: Flash memory is executing an erase sequence. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 664 1: Flash memory is enabled to perform an high voltage operation. Table 27-10. Array space size SIZE Array space size 128 KB 256 KB 512 KB 1024 KB 1536 KB Reserved (2048 KB) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 665 Table 27-13. CFLASH_MCR bits set/clear priority levels Priority level CFLASH_MCR bits ESUS If the user attempts to write two or more CFLASH_MCR bits simultaneously then only the bit with the lowest priority level is written. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 666 Reset Defined by CFLASH_NVLML at CFlash Test Sector Address 0x403DE8. This location is user OTP (One Time Programmable). The CFLASH_NVLML register influences only the R/W bits of the CFLASH_LML register. Figure 27-4. CFlash Low/Mid Address Space Block Locking Register (CFLASH_LML) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 667 TSLK is not writable unless LME is high. 0: Test/Shadow Address Space Block is unlocked and can be modified (also if CFLASH_SLL[STSLK] = 0). 1: Test/Shadow Address Space Block is locked and cannot be modified. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 668 TestFlash that contains the default reset value for CFLASH_LML. During the reset phase of the flash memory module, the CFLASH_NVLML register content is read and loaded into the CFLASH_LML. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 669 TSLK is not writable unless LME is high. 0: Test/Shadow Address Space Block is unlocked and can be modified (also if CFLASH_SLL[STSLK] = 0). 1: Test/Shadow Address Space Block is locked and cannot be modified. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 670 These bits, along with bits in the CFLASH_LML register, determine if the block is locked from Program or Erase. An “OR” of CFLASH_LML and CFLASH_SLL determine the final lock status. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 671 STSLK is not writable unless SLE is high. 0: Test/Shadow Address Space Block is unlocked and can be modified (also if CFLASH_LML[TSLK] = 0). 1: Test/Shadow Address Space Block is locked and cannot be modified. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 672 SLK is not writable unless SLE is high. 0: Low Address Space Block is unlocked and can be modified (also if CFLASH_LML[LLK] = 1: Low Address Space Block is locked and cannot be modified. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 673 The CFLASH_NVSLL register is a 64-bit register, of which the 32 most significant bits 63:32 are ‘don’t care’ and are used to manage ECC codes. Offset: 0x403DF8 Access: Read/write R SLE Reset Reset Figure 27-7. CFlash Nonvolatile Secondary Low/mid address space block Locking register (CFLASH_NVSLL) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 674 STSLK is not writable unless SLE is high. 0: Test/Shadow Address Space Block is unlocked and can be modified (also if CFLASH_LML[TSLK] = 0). 1: Test/Shadow Address Space Block is locked and cannot be modified. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 675 SLK is not writable unless SLE is high. 0: Low Address Space Block is unlocked and can be modified (also if CFLASH_LML[LLK] = 1: Low Address Space Block is locked and cannot be modified. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 676 0, and register writes will have no effect. Bits LSL[15:6] are read-only and locked at ‘0’. 0: Low Address Space Block is unselected for erase. 1: Low Address Space Block is selected for erase. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 677 Address of first ECC Double Error CFLASH_MCR[RWE] = 1 Address of first RWW Error CFLASH_MCR[PEG] = 0 Address of first FPEC Error CFLASH_MCR[EDC] = 1 Address of first ECC Single Error Correction MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 678 This bit can be written and its value can be read back, but there is no function associated. This bit is not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 679 Once completed, AID will be set to indicate that the Array Integrity Check is complete. At this time the MISR (CFLASH_UMISR0-4) can be checked. 0: Array Integrity Check is on-going. 1: Array Integrity Check is done. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 680 The CFLASH_UT2 register allows to enable the checks on the ECC logic related to the 32 MSB of the Double Word. The User Test 2 Register is not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 681 The User Multiple Input Signature Register 0 represents the bits 31:0 of the whole 144 bits word (2 Double Words including ECC). The CFLASH_UMISR0 Register is not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 682 The CFLASH_UMISR1 represents the bits 63:32 of the whole 144 bits word (2 Double Words including ECC). The CFLASH_UMISR1 is not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 683 The CFLASH_UMISR2 represents the bits 95:64 of the whole 144 bits word (2 Double Words including ECC). The CFLASH_UMISR2 is not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 684 The CFLASH_UMISR3 represents the bits 127:96 of the whole 144 bits word (2 Double Words including ECC). The CFLASH_UMISR3 is not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 685 Word; bits 4:5 and 20:21 of MISR are respectively the double and single ECC error detection for odd and even Double Word. The CFLASH_UMISR4 is not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 686 27.5.1.14 CFlash Nonvolatile Private Censorship Password 0 Register (NVPWD0) The nonvolatile private censorship password 0 register contains the 32 LSB of the Password used to validate the Censorship information contained in NVSCC0–1 registers. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 687 The nonvolatile private censorship password 1 register contains the 32 MSB of the Password used to validate the Censorship information contained in NVSCC0–1 registers. Offset: 0x203DDC Access: Read/write PWD[63:48] Reset PWD[47:32] Reset Figure 27-19. CFlash Nonvolatile Private Censorship Password 1 Register (NVPWD1) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 688 The parts are delivered uncensored to the user. Offset: 0x203DE0 Access: Read/write SC[15:0] Reset CW[15:0] Reset Figure 27-20. CFlash Nonvolatile System Censorship Control 0 register (NVSCC0) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 689 These bits represent the 16 MSB of the Censorship Control Word (CCW). If CW15-0 = 0x55AA and NVSCC1 = NVSCC0 the Censored Mode is disabled.   If CW15-0 0x55AA or NVSCC1 NVSCC0 the Censored Mode is enabled. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 690 0: High voltage supply is 5.0 V 1: High voltage supply is 3.3 V Default manufacturing value before flash memory initialization is ‘1’ (3.3 V) which should ensure correct minimum slope for boundary scan. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 691: Dflash Register Description
The value of the LAS field corresponds to the configuration of the Low Address Space; see Table 27-36. Mid Address Space The value of the MAS field corresponds to the configuration of the Mid Address Space; see Table 27-37. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 692 , time equals to Erase Suspend Latency) after a 0 to 1 ESUS transition of ESUS, which suspends an erase operation. 0: Flash memory is executing a high voltage operation. 1: Flash memory is not executing a high voltage operation. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 693 ERS can be cleared by the user only when ESUS and EHV are low and DONE is high. ERS is cleared on reset. 0: Flash memory is not executing an erase sequence. 1: Flash memory is executing an erase sequence. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 694 1: Flash memory is enabled to perform an high voltage operation. Table 27-35. Array space size SIZE Array space size 128 KB 256 KB 512 KB Reserved (1024 KB) Reserved (1536 KB) Reserved (2048 KB) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 695 Table 27-38. DFLASH_MCR bits set/clear priority levels Priority level DFLASH_MCR bits ESUS If the user attempts to write two or more DFLASH_MCR bits simultaneously then only the bit with the lowest priority level is written. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 696 Reset Defined by DFLASH_NVLML at DFlash Test Sector Address 0xC03DE8. This location is user OTP (One Time Programmable). The DFLASH_NVLML register influences only the R/W bits of the DFLASH_LML register. Figure 27-24. DFlash Low/Mid Address Space Block Locking Register (DFLASH_LML) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 697 LLK is not writable unless LME is high. 0: Low Address Space Block is unlocked and can be modified (also if DFLASH_SLL[SLK] = 1: Low Address Space Block is locked and cannot be modified. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 698 The DFLASH_NVLML register is a 64-bit register, of which the 32 most significant bits 63:32 are ‘don’t care’ and are used to manage ECC codes. Offset: 0xC03DE8 Access: Read/write R LME TSLK Reset Reset Figure 27-25. DFlash Nonvolatile Low/Mid address space block Locking register (DFLASH_NVLML) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 699 LLK is not writable unless LME is high. 0: Low Address Space Block is unlocked and can be modified (also if DFLASH_SLL[SLK] = 1: Low Address Space Block is locked and cannot be modified. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 700 Defined by DFLASH_NVSLL at DFlash Test Sector Address 0xC03DF8. This location is user OTP (One Time Programmable). The DFLASH_NVSLL register influences only the R/W bits of the DFLASH_SLL register. Figure 27-26. DFlash Secondary Low/mid address space block Locking register (DFLASH_SLL) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 701 SLK is not writable unless SLE is high. 0: Low Address Space Block is unlocked and can be modified (also if DFLASH_LML[LLK] = 1: Low Address Space Block is locked and cannot be modified. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 702 The DFLASH_NVSLL register is a 64-bit register, of which the 32 most significant bits 63:32 are ‘don’t care’ and are used to manage ECC codes. Offset: 0xC03DF8 Access: Read/write R SLE Reset Reset Figure 27-27. DFlash Nonvolatile Secondary Low/mid address space block Locking register (DFLASH_NVSLL) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 703 SLK is not writable unless SLE is high. 0: Low Address Space Block is unlocked and can be modified (also if DFLASH_LML[LLK] = 1: Low Address Space Block is locked and cannot be modified. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 704 DFlash Address Register (DFLASH_ADR) The DFLASH_ADR provides the first failing address in the event module failures (ECC, RWW or FPEC) occur or the first address at which an ECC single error correction occurs. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 705 Address of first ECC Single Error Correction 27.5.2.6 DFlash User Test 0 register (DFLASH_UT0) The User Test Registers provide the user with the ability to test features on the flash memory module. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 706 This bit can be written and its value can be read back, but there is no function associated. This bit is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 707 Once completed, AID will be set to indicate that the Array Integrity Check is complete. At this time the MISR (DFLASH_UMISR0-4) can be checked. 0: Array Integrity Check is on-going. 1: Array Integrity Check is done. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 708 The DFLASH_UT2 register allows to enable the checks on the ECC logic related to the 32 MSB of the Double Word. The User Test 2 Register is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 709 The DFLASH_UMISR0 represents the bits 31:0 of the whole 144 bits word (2 Double Words including ECC). The DFLASH_UMISR0 is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 710 The DFLASH_UMISR1 represents the bits 63:32 of the whole 144 bits word (2 Double Words including ECC). The DFLASH_UMISR1 is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 711 The DFLASH_UMISR2 represents the bits 95:64 of the whole 144 bits word (2 Double Words including ECC). The DFLASH_UMISR2 is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 712 The DFLASH_UMISR3 represents the bits 127:96 of the whole 144 bits word (2 Double Words including ECC). The DFLASH_UMISR3 is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 713 ECC error detection for odd and even Double Word. The DFLASH_UMISR4 Register is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 714: Programming Considerations
MCR[RWE] will be automatically set. This means that the flash memory module is not fetchable when a modify operation is active and these commands must be executed from another memory (internal SRAM or another flash memory module). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 715: Double Word Program
Double word program A flash memory Program sequence operates on any Double Word within the flash memory core. Up to two words within the Double Word may be altered in a single Program operation. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 716 MCR[PEAS] field to be set/cleared. An interlock write must be performed before setting MCR[EHV]. The user may terminate a program sequence by clearing MCR[PGM] prior to setting MCR[EHV]. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 717: Sector Erase
3. Write to any address in flash memory. This is referred to as an erase interlock write. 4. Write a logic 1 to the MCR[EHV] bit to start the internal erase sequence or skip to step 9 to terminate. 5. Wait until the MCR[DONE] bit goes high. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 718 The user must wait until MCR[DONE] = 1 before the module is suspended and further actions are attempted. MCR[DONE] will go high no more than t after MCR[ESUS] is set to ‘1’. ESUS MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 719 MISR through five different read accesses at the same location. The whole check is done through five complete scans of the memory address space: 1. The first pass will scan only bits 31:0 of each page. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 720 = UMISR2; /* Read UMISR2 content*/ data3 = UMISR3; /* Read UMISR3 content*/ data4 = UMISR4; /* Read UMISR4 content*/ = 0x00000000; /* Reset UTE and AIE in UT0: Operation End */ MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 721 UMISR0 = 0x00000000; /* Reset UMISR0 content */ UMISR1 = 0x00000000; /* Reset UMISR1 content */ UMISR2 = 0x00000000; /* Reset UMISR2 content */ UMISR3 = 0x00000000; /* Reset UMISR3 content */ MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 722 /* Loop to wait for AID=1 */ { tmp = UT0; /* Read UT0 */ } while ( !(tmp & 0x00000001) ); data0 = UMISR0; /* Read UMISR0 content (expected 0x55555555) */ MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 723 Table 27-55. Bit manipulation: Double words with the same ECC value Double word ECC all ‘1’s no error 0xFFFF_FFFF_FFFF_FFFF 0xFF 0xFFFF_FFFF_FFFF_0000 0xFF 0xFFFF_FFFF_0000_FFFF 0xFF 0xFFFF_0000_FFFF_FFFF 0xFF 0x0000_FFFF_FFFF_FFFF 0xFF 0xFFFF_FFFF_0000_0000 0xFF 0xFFFF_0000_FFFF_0000 0xFF 0x0000_FFFF_FFFF_0000 0xFF 0xFFFF_0000_0000_FFFF 0xFF 0x0000_FFFF_0000_FFFF 0xFF MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 724 An alternate means to enable software locking for blocks of Low Address Space only is through the SLL. All these registers have a nonvolatile image stored in TestFlash (NVLML, NVSLL), so that the locking information is kept on reset. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 725: Platform Flash Memory Controller
A block diagram of the e200z0h Power Architecture reduced product platform (RPP) reference design is shown below in Figure 27-38 with the platform flash memory controller module and its attached off-platform flash memory arrays highlighted. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 726 AHB-to-IPS/APB bus controller (PBRIDGE) for access to on- and off-platform slave modules • Interrupt Controller (INTC) • 4-channel System Timers (STM) • Software Watchdog Timer (SWT) • Error Correction Status Module (ECSM) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 727 The following list summarizes the key features of the platform flash memory controller: • Dual array interfaces support up to a total of 16 MB of flash memory, partitioned as two separate 8 MB banks MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 728: Memory Map And Register Description
The system memory map defines one code flash memory array and one data flash memory array. See Table 27-56. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 729 Register Location 0x1C Platform Flash Configuration Register 0 (PFCR0) on page 719 0x20 Platform Flash Configuration Register 1 (PFCR1) on page 722 0x24 Platform Flash Access Protection Register (PFAPR) on page 724 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 730 See the MPC5604B data sheet for detailed settings for different values of frequency. 27.7.2.2 Register description This section details the individual registers of the platform flash memory controller. Flash memory configuration registers must be written only with 32-bit write operations to avoid any issues associated with register “incoherency”...
Page 731 PFlash and the actual read access time of the PFlash. The required settings are documented in the device datasheet. 00000: No additional wait-states are added 00001: One additional wait-state is added 00010: Two additional wait-states are added 11111: 31 additional wait-states are added MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 732 Prefetching can be enabled/disabled on a per Master basis at PFAPR[MxPFD]. 0: No prefetching is triggered by an instruction fetch read access 1: If page buffers are enabled (B0_P0_BFE = 1), prefetching is triggered by any instruction fetch read access MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 733 Do not execute code from flash memory when you are programming PFCR1. If you wish to program PFCR1, execute your application code from RAM. Offset 0x020 Access: Read/write BK1_APC BK1_WWSC BK1_RWSC Reset Reset Figure 27-40. PFlash Configuration Register 1 (PFCR1) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 734 00000: No additional wait-states are added 00001: One additional wait-state is added 00010: Two additional wait-states are added 11111: 31 additional wait-states are added This field is ignored in single bank flash memory configurations. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 735 0x203E00 of the shadow region in the flash memory array must be programmed using the normal sequence of operations. The reset value shown in Table 27-41 reflects an erased or unprogrammed value from the shadow region. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 736 PFAPR. The NVPFAPR register is a 64-bit register, of which the 32 most significant bits 63:32 are ‘don’t care’ and are used to manage ECC codes. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 737: Functional Description
Flash Configuration Register 1 (PFCR1). Access protections may be applied on a per-master basis for both reads and writes to support security and privilege mechanisms; see Section 27.7.2.2.3, Platform Flash Access Protection Register (PFAPR). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 738: Access Protections
Read Access Control or Write Access Control settings do not allow the access, thus causing a protection violation. In this case, the platform flash memory controller does not initiate a flash memory array access. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 739: Access Pipelining
A read access to the platform flash memory controller may trigger a prefetch to the next sequential page of array data on the first idle cycle following the request. The access MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 740 Prefetch triggering may be enabled for instruction reads via the Bx_Py_IPFE control field, while prefetching for data reads is enabled via the Bx_Py_DPFE control field. Additionally, the Bx_Py_PFLIM field must be set to enable prefetching. Prefetches are never triggered by write cycles. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 741: Bank1 Temporary Holding Register
Subsequent flash memory accesses that “hit” the buffer, that is, the current access address matches the address stored in the temporary holding register, can be serviced in MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 742: Read-While-Write Functionality
Once the retried address phase is complete, the read is processed normally and once the data is valid, it is forwarded to the AHB bus to terminate the system bus transfer. • BKn_RWWC = 0b110 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 743: Wait-State Emulation
These wait-states are applied to the initial access of a burst fetch or to single-beat read accesses on the AHB system bus. Note that the wait-state specification consists of two components: haddr[28:26] and haddr[25:24] and effectively extends the flash memory read by (8 * haddr[25:24] + haddr[28:26]) cycles. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 744 Table 27-64. Extended additional wait-state encoding Memory address Additional wait-states haddr[25:24] (added to those specified by haddr[28:26]) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 745 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 746: Introduction
SRAM ECC mechanism The SRAM ECC detects the following conditions and produces the following results: • Detects and corrects all 1-bit errors • Detects and flags all 2-bit errors as non-correctable errors MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 747: Access Timing
Current operation Previous operation Number of wait states required Read Read Idle Pipelined read 8, 16 or 32-bit write (read from the same address) (read from a different address) Pipelined read Read MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 748: Reset Effects On Sram Accesses
32-bit word-aligned boundaries. If the write is not the entire 32 bits (8 or 16 bits), a read / modify / write operation is generated that checks the ECC value upon the read. See Section 28.4, “SRAM ECC mechanism. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 749 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 750 ——— Integrity ——— MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 751 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 752: Introduction
Restrict write accesses for the module under protection to supervisor mode only • Lock registers for first 6 KB of memory-mapped address space • Address mirror automatically sets corresponding lock bit • Once configured lock bits can be protected from changes MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 753: Modes Of Operation
X in the same cycle as the register at address X is written. Not all registers in area 1 need to have protection defined by associated soft lock bits. For unprotected registers MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 754: Memory Map
Soft Lock Bit Register 1535 (SLBR1535): soft lock bits 6140-6143 0x3E00–0x3FFB Reserved — 0x3FFC Global Configuration Register (GCR) on page 745 NOTE Reserved registers in area #2 will be handled according to the protected IP (module under protection). MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 755: Register Description
SLB3 can block accesses to MR[n *4 + 3] 1 Associated MRn byte is locked against write accesses 0 Associated MRn byte is unprotected and writeable Figure 29-3 gives some examples how SLBRn.SLB and MRn go together. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 756 29.5.2.4 Global Configuration Register (GCR) This register is used to make global configurations related to register protection. Address 0x3FFC Access: Read Always Supervisor write Reset Reset Figure 29-4. Global Configuration Register (GCR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 757: Functional Description
• Modify the SLBRn.SLBm directly by writing to area #4 • Set the SLBRn.SLBm bit(s) by writing to the mirror module space (area #3) Both methods are explained in the following sections. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 758 In the example on the left side of Figure 29-6 the data written to SLBRn.SLB[0] is mirrored to SLBRn.SLB[1] and the data written to SLBRn.SLB[2] is mirrored to SLBRn.SLB[3] as for both registers the write enables are set. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 759 Enable locking via mirror module space (area #3) It is possible to enable locking for a register after writing to it. To do so the mirrored module address space must be used. Figure 29-9 shows one example: MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 760 Section 29.6.2.2, Enable locking via mirror module space (area #3) is only possible as long as the bit GCR.HLB is cleared. Once this bit is set the locking bits can no longer be modified until there is a system reset. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 761: Access Errors
In summary, after reset, locking for all MRn registers is disabled. The registers can be accessed in Supervisor Mode only. 29.8 Protected registers For MPC5604B the Register Protection module protects the registers shown in Table 29-5. Table 29-5. Protected registers...
Page 762 SIUL PCR36 C3F90000 bits[0:15] SIUL PCR37 C3F90000 bits[0:15] SIUL PCR38 C3F90000 bits[0:15] SIUL PCR39 C3F90000 bits[0:15] SIUL PCR40 C3F90000 bits[0:15] SIUL PCR41 C3F90000 bits[0:15] SIUL PCR42 C3F90000 bits[0:15] SIUL PCR43 C3F90000 bits[0:15] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 763 Mode Entry Module, 41 registers to protect MC ME ME_ME C3FDC000 bits[0:31] MC ME ME_IM C3FDC000 bits[0:31] MC ME ME_TEST_MC C3FDC000 bits[0:31] MC ME ME_SAFE_MC C3FDC000 bits[0:31] MC ME ME_DRUN_MC C3FDC000 bits[0:31] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 764 C3FDC000 bits[0:31] MC ME ME_PCTL[32..35] C3FDC000 bits[0:31] MC ME ME_PCTL[44..47] C3FDC000 bits[0:31] MC ME ME_PCTL[48..51] C3FDC000 bits[0:31] MC ME ME_PCTL[56..59] C3FDC000 bits[0:31] MC ME ME_PCTL[60..63] C3FDC000 bits[0:31] MC ME ME_PCTL[68..71] C3FDC000 bits[0:31] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 765 MC RGM RGM_DEAR C3FE4000 bits[0:15] MC RGM RGM_FESS C3FE4000 bits[0:15] MC RGM RGM_STDBY C3FE4000 bits[0:15] MC RGM RGM_FBRE C3FE4000 bits[0:15] Power Control Unit, 1 registers to protect MC PCU PCONF2 C3FE8000 bits[0:31] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 766: Overview
SWT will continue from the state it was before entering this mode. The software watchdog is not available during standby. On exit from standby, the SWT behaves in a usual “out of reset” situation. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 767: External Signal Description
SWT Time-Out Register (SWT_TO) on page 759 0x000C SWT Window Register (SWT_WN) on page 759 0x0010 SWT Service Register (SWT_SR) on page 760 0x0014 SWT Counter Output Register (SWT_CO) on page 760 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 768: Register Description
1 = Windowed mode, the service sequence is only valid when the down counter is less than the value in the SWT_WN register. Interrupt Then Reset. 0 = Generate a reset on a time-out 1 = Generate an interrupt on an initial time-out, reset on a second consecutive time-out MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 769 1 = SWT_CR, SWT_TO and SWT_WN are read only registers Clock Selection. Selects the SIRC oscillator clock that drives the internal timer. CSL bit can be written.The status of the bit has no effect on counter clock selection on MPC5604B device.
Page 770 Access: Read/Write 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reset Figure 30-4. SWT Window Register (SWT_WN) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 771 Access: Read Only 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reset Figure 30-6. SWT Counter Output Register (SWT_CO) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 772: Functional Description
(The peripheral bus bridge may add one or more system wait states.) However, due to synchronization logic in the SWT design, recognition of the service sequence or configuration changes may require up to three system plus seven counter clock cycles. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 773 Watchdog is disabled at the start of BAM execution. In the case of an unexpected issue during BAM execution, the CPU may be stalled and an external reset needs to be generated to recover. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 774: Introduction
Register Location 0x00 Processor Core Type Register (PCT) on page 765 0x02 SoC-Defined Platform Revision Register (REV) on page 765 0x04 Reserved 0x08 IPS On-Platform Module Configuration Register (IOPMC) on page 765 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 775: Register Description
Unless noted otherwise, writes to the programming model must match the size of the register, e.g., an n-bit register only supports n-bit writes, MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 776 The IOPMC is a 32-bit read-only register identifying the presence/absence of the 32 low-order IPS peripheral modules connected to the primary IPI slave bus controller. The state of this register is defined MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 777 MWCR[LPMD], to be entered, and the appropriate clock signals disabled. In most implementations, there are multiple low-power modes, where the exact clocks to be disabled vary across the different modes. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 778 Certain interrupt controller implementations include logic associated with this priority level that restricts the data value contained in this field to a [0, maximum - 1] range. See the specific interrupt controller module for details. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 779 0 A flash bank 1 stall has not occurred. 1 A flash bank 1 stall has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a 0 has no effect. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 780 Platform Flash ECC Address Register (PFEAR) • Platform Flash ECC Master Number Register (PFEMR) • Platform Flash ECC Attributes Register (PFEAT) • Platform Flash ECC Data Register (PFEDR) • Platform RAM ECC Address Register (PREAR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 781 ESR[RNCE]. The faulting address, attributes and data are also captured in the PREAR, PRESR, PREMR, PREAT and PREDR registers. 0 Reporting of non-correctable SRAM errors is disabled. 1 Reporting of non-correctable SRAM errors is enabled. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 782 ESR[FNCE]. The faulting address, attributes and data are also captured in the PFEAR, PFEMR, PFEAT and PFEDR registers. 0 Reporting of non-correctable flash errors is disabled. 1 Reporting of non-correctable flash errors is enabled. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 783 3. Re-read the ESR and verify the current contents matches the original contents. If the two values are different, go back to step 1 and repeat. 4. When the values are identical, write a 1 to the asserted ESR flag to negate the interrupt request. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 784 ECC, most notably the SRAM. This capability is provided for two purposes: • It provides a software-controlled mechanism for “injecting” errors into the memories during data writes to verify the integrity of the ECC logic. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 785 This bit can only be set if the same SoC configurable input enable signal (as that used to enable single-bit correction reporting) is asserted. 0 No SRAM single 1-bit data inversion is generated. 1 One 1-bit data inversion in the SRAM is generated. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 786 ERRBIT = 65, then ECC Parity[1] of the odd bank is inverted if ERRBIT = 70, then ECC Parity[6] of the odd bank is inverted For ERRBIT values of 32 to 63 and greater than 70, no bit position is inverted. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 787 Figure 31-10. Platform Flash ECC Address Register (PFEAR) Table 31-11. PFEAR field descriptions Field Description FEAR Flash ECC Address Register This 32-bit register contains the faulting access address of the last, properly-enabled flash ECC event. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 788 – – – – – – Figure 31-12. Platform Flash ECC Attributes Register (PFEAT) Table 31-13. PFEAT field descriptions Field Description WRITE AMBA-AHB HWRITE 0 AMBA-AHB read access 1 AMBA-AHB write access MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 789 Flash ECC Data Register This 32-bit register contains the data associated with the faulting access of the last, properly-enabled flash ECC event. The register contains the data value taken directly from the data bus. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 790 This register can only be read from the IPS programming model; any attempted write is ignored. Offset: 0x65 Access: Read RESR Reset: – – – – – – – – Figure 31-15. Platform RAM ECC Syndrome Register (PRESR) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 791 DATA ODD BANK[25] 0x18 DATA ODD BANK[24] 0x1a DATA ODD BANK[23] 0x1c DATA ODD BANK[22] 0x50 DATA ODD BANK[21] 0x20 ECC ODD[5] 0x22 DATA ODD BANK[20] 0x24 DATA ODD BANK[19] 0x26 DATA ODD BANK[18] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 792 See the XBAR chapter of this reference manual for a listing of XBAR bus master numbers. This register can only be read from the IPS programming model; any attempted write is ignored. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 793 Protection[3]: Cacheable 0 = Non-cacheable, 1 = Cacheable Protection[2]: Bufferable 0 = Non-bufferable, 1 = Bufferable Protection[1]: Mode 0 = User mode, 1 = Supervisor mode Protection[0]: Type 0 = I-Fetch, 1 = Data MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 794: Register Protection
SRAM ECC event. The register contains the data value taken directly from the data bus. 31.4.3 Register protection Logic exists which restricts accesses to INTC, ECSM, MPU, STM and SWT to supervisor mode only. Accesses in User mode are not possible. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 795 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 796 ——— Debug ——— MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 797 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 798: Introduction
TEST mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. In addition, instructions can be executed that allow the Test Access Port MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 799: Features
Only one test data register path is enabled to shift data between TDI and TDO for each instruction. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 800: External Signal Description
JTAGC. Once TAP enters shift-ir or shift-dr then output direction control from JTAGC which allows the value to see on pad. It is up to the user to configure them as GPIOs accordingly, in this case MPC5604B get incompliance with IEEE 1149.1-2001.
Page 801: Memory Map And Register Description
Entry into the capture-DR state while the device identification register is selected loads the IDCODE into the shift register to be shifted out on TDO in the Shift-DR state. No action occurs in the update-DR state. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 802: Boundary Scan Register
4–9 Design center. For the MPC5604B this value is 0x2B. 10–19 Part identification number. Contains the part number of the device. For the MPC5604B, this value is 0x241. 20–30 Manufacturer identity code. Contains the reduced Joint Electron Device Engineering Council (JEDEC) ID for Freescale, 0xE IDCODE register ID.
Page 803: Tap Controller State Machine
TMS signal sampled on the rising edge of the TCK signal. Figure 32-5 shows, holding TMS at logic 1 while clocking TCK through a sufficient number of rising edges also causes the state machine to enter the test-logic-reset state. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 804 JTAGC is enabled. Instructions are shifted in via the select-IR-scan path and loaded in the update-IR state. At this point, all data register access is performed via the select-DR-scan path. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 805: Jtagc Instructions
This allows more rapid movement of test data to and from other components on a board that are required to perform test functions. While the BYPASS instruction is active the system logic operates normally. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 806 This sampling occurs on the rising-edge of TCK in the capture-DR state when the SAMPLE/PRELOAD instruction is active. The sampled data is viewed by shifting it through the boundary scan register to the TDO output MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 807: Boundary Scan
Nexus2+ configuration registers. A complete discussion of the e200z0 OnCE debug features is available in the e200z0 Reference Manual. 32.9.1 e200z0 OnCE Controller Block Diagram Figure 32-6 is a block diagram of the e200z0 OnCE block. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 808: E200Z0 Once Controller Functional Description
32-7. The OCMD is updated when the TAP controller enters the update-IR state. It contains fields for controlling access to a resource, as well as controlling single-step operation and exit from OnCE mode. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 809 Debug Control Register 1 (DBCR1) 011 0011 Debug Control Register 2 (DBCR2) 011 0100 – 101 1111 Reserved (do not access) 110 1111 Shared Nexus Control Register (SNC) (only available on the e200z0 core) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 810: Initialization/Application Information
To initialize the JTAGC module and enable access to registers, the following sequence is required: 1. Place the JTAGC in reset through TAP controller state machine transitions controlled by TMS 2. Load the appropriate instruction for the test or action to be performed. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 811 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 812: Introduction
Introduction The Nexus Development Interface (NDI) block provides real-time development support capabilities for the MPC5604B MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for MCUs without requiring external address and data pins for internal visibility.
Page 813: Features
Figure 33-2. NDI Implementation Block Diagram 33.3 Features The NDI module of the MPC5604B is compliant with Class 2 of the IEEE-ISTO 5001-2003 standard, with additional Class 3 and Class 4 features available.The following features are implemented: • Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to...
Page 814: Modes Of Operation
The NDI block indicates to the MCU that it is not using the auxiliary output port. This indication can be used to three-state the output pins or use them for another function. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 815: Operating Mode
JTAG port using a client-select value and a register index. OnCE registers are accessed by loading the appropriate value in the RS[0:6] field of the OnCE command register (OCMD) via the JTAG port. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 816: Nexus Debug Interface Registers
813 0b0000 Read/Write Access Data (RWD) Register on page 814 0b0000 Watchpoint Trigger (WT) Register on page 814 Implemented in NPC block. All other registers implemented in e200z0 Nexus2+ block. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 817: Register Description
The PCR register may be rewritten by the debug tool subsequent to the enabling of the NPC for low power debug support. In this case, the debug tool may set and clear the LP_DBG_EN, SLEEP_SYNC, and STOP_SYNC bits, but must preserve the original state of the remaining bits in the register. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 818 This bit enables the MCKO clock to run. When enabled, the frequency of MCKO is determined by the MCKO_DIV field. 0 MCKO clock is driven to zero. 1 MCKO clock is enabled. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 819 STOP_SYNC as set, the debug tool then clears STOP_SYNC to acknowledge to the device that it may enter into STOP mode. 0 Stop mode entry acknowledge 1 Stop mode entry pending 24–30 Reserved Processor Status Mode Enable PSTAT_EN MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 820 0 Watchpoint messaging disabled 1 Watchpoint messaging enabled 8–23 Reserved 24–26 Overrun Control OVC[2:0] 000 Generate overrun messages. 001–010 Reserved 011 Delay processor for BTM / DTM / OTM overruns. 1XX Reserved MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 821 XXX1XXXXWatchpoint #3 (IAC4 from Nexus1) triggers EVTO. XXXX1XXXWatchpoint #4 (DAC1 from Nexus1) triggers EVTO. XXXXX1XXWatchpoint #5 (DAC2 from Nexus1) triggers EVTO. XXXXXX1XWatchpoint #6 (DCNT1 from Nexus1) triggers EVTO. XXXXXXX1Watchpoint #7 (DCNT2 from Nexus1) triggers EVTO. 8–31 Reserved MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 822 00 Normal (run) mode 01 CPU in halted state 10 CPU in stopped state 11 Reserved CPU Checkstop Status 0 CPU not in checkstop state 1 CPU in checkstop state 7–31 Reserved MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 823 10 Reserved (default to lowest priority) 11 Highest access priority Burst Control 0 Module accesses are single bus cycle at a time. 1 Module accesses are performed as burst operation. 11–15 Reserved MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 824 The read/write access address register provides the system bus address to be accessed when initiating a read or a write access. Nexus Reg: 0x0009 Access: User read/write RWA[0-15] Reset RWA[16-31] Reset Figure 33-9. Read/Write Access Address (RWA) Register MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 825 These watchpoints can control program and/or data trace enable and disable. The WT bits can be used to produce an address-related window for triggering trace messages. Nexus Reg: 0x000B Access: User read/write Reset Reset Figure 33-11. Watchpoint Trigger (WT) Register Table 33-10 details the watchpoint trigger register fields. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 826: Functional Description
111 Use watchpoint #6 or #7 (DCNT1 or DCNT2 from Nexus1). 12–31 Reserved 33.7 Functional description The NDI block is implemented by integrating the following blocks on the MPC5604B: • Nexus e200z0 development interface (OnCE and Nexus2p subblocks) • Nexus port controller (NPC) block •...
Page 827: Enabling Nexus Clients For Tap Access
Opcode for e200z0 OnCE Nexus ENABLE instruction (10-bits) 0x7C BYPASS Opcode for the e200z0 OnCE BYPASS instruction (10-bits) 0x7F Refer to the e200z0 reference manual for a complete list of available OnCE instructions. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 828: Configuring The Ndi For Nexus Messaging
SRC field by the different clients on the MPC5604B. These values are specific to the MPC5604B. The size of the SRC field in transmitted messages is 4 bits. This value is also specific to the MPC5604B.
Page 829: Debug Mode Control
NPC drives EVTO for two system clock periods. EVTO sharing is active as long as the NDI is not in reset. 33.7.7 Debug Mode Control On MPC5604B, program breaks can be requested either by using the EVTI pin as a break request, or when a Nexus event is triggered. 33.7.7.1 EVTI Generated Break Request To use the EVTI pin as a debug request, the EIC field in the e200z0 Nexus2+ Development Control Register 1 (DC1[4:3]) must be set to configure the EVTI input as a debug request.
Page 830 (Program trace or data trace) and ownership trace overrun 01000 (Program trace or data trace or ownership trace) and watchpoint overrun 01001–0111 Reserved 11000 BTM lost due to collision w/ higher priority message 11001–11111 Reserved MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 831 3. If the periodic OTM message counter expires (after 255 queued messages without an OTM), an OTM is sent using the latched data from the previous OTM or process ID register write. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 832: Appendix A
0xFFE4_4000 on page 854 LINFlex_2 0xFFE4_8000 on page 854 LINFlex_3 0xFFE4_C000 on page 855 0xFFE6_4000 on page 856 CAN sampler 0xFFE7_0000 on page 858 0xFFF1_0000 on page 858 0xFFF3_8000 on page 859 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 833: Register Map
Base + 0x0040 User Test Register 2 CFLASH_UT2 32-bit Base + 0x0044 User Multiple Input Signature Register 0 CFLASH_UMISR0 32-bit Base + 0x0048 User Multiple Input Signature Register 1 CFLASH_UMISR1 32-bit Base + 0x004C MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 834: Register Map
IRER 32-bit Base + 0x0018 Reserved — — Base + (0x001C – 0x0027) Interrupt Rising Edge Event Enable IREER 32-bit Base + 0x0028 Interrupt Falling-Edge Event Enable IFEER 32-bit Base + 0x002C MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 835: Register Map
PCR25 16-bit Base + 0x0072 Pad Configuration Register 26 PCR26 16-bit Base + 0x0074 Pad Configuration Register 27 PCR27 16-bit Base + 0x0076 Pad Configuration Register 28 PCR28 16-bit Base + 0x0078 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 836: Register Map
PCR57 16-bit Base + 0x00B2 Pad Configuration Register 58 PCR58 16-bit Base + 0x00B4 Pad Configuration Register 59 PCR59 16-bit Base + 0x00B6 Pad Configuration Register 60 PCR60 16-bit Base + 0x00B8 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 837: Register Map
PCR89 16-bit Base + 0x00F2 Pad Configuration Register 90 PCR90 16-bit Base + 0x00F4 Pad Configuration Register 91 PCR91 16-bit Base + 0x00F6 Pad Configuration Register 92 PCR92 16-bit Base + 0x00F8 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 838: Register Map
Pad Configuration Register 120 PCR120 16-bit Base + 0x0130 Pad Configuration Register 121 PCR121 16-bit Base + 0x0132 Pad Configuration Register 122 PCR122 16-bit Base + 0x0134 Reserved — — Base + (0x0136 – 0x04FF) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 839: Register Map
Base + 0x0648 GPIO Pad Data Output Register GPDO76_79 32-bit Base + 0x064C GPIO Pad Data Output Register GPDO80_83 32-bit Base + 0x0650 GPIO Pad Data Output Register GPDO84_87 32-bit Base + 0x0654 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 840: Register Map
Base + 0x0844 GPIO Pad Data Input Register GPDI72_75 32-bit Base + 0x0848 GPIO Pad Data Input Register GPDI76_79 32-bit Base + 0x084C GPIO Pad Data Input Register GPDI80_83 32-bit Base + 0x0850 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 841: Register Map
Masked Parallel GPIO Pad Data Out Register MPGPDO6 32-bit Base + 0x0C98 Masked Parallel GPIO Pad Data Out Register MPGPDO7 32-bit Base + 0x0C9C Reserved — — Base + (0x0CA0 – 0x0FFF) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 842: Register Map
Base + 0x0018 Wakeup Request Enable Register WKPU_WRER 32-bit Base + 0x001C Reserved — — (Base + 0x0020) – (Base + 0x0027) Wakeup/Interrupt Rising-Edge Event Enable Register WKPU_WIREER 32-bit Base + 0x0028 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 843: Register Map
Base + 0x0068 – Base + 0x006B eMIOS_0 UC2 Control Register EMIOS0_UC2_SC 32-bit Base + 0x006C eMIOS_0 UC2 Status Register EMIOS0_UC2_SS 32-bit Base + 0x0070 Reserved — — Base + 0x0074 – Base + 0x007F MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 844: Register Map
Base + 0x00F4 – Base + 0x00FF eMIOS_0 UC7 A Register EMIOS0_UC7_A 32-bit Base + 0x0100 eMIOS_0 UC7 B Register EMIOS0_UC7_B 32-bit Base + 0x0104 Reserved — — Base + 0x0108 – Base + 0x010B MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 845: Register Map
Base + 0x0188 – Base + 0x018B eMIOS_0 UC11 Control Register EMIOS0_UC11_SC 32-bit Base + 0x018C eMIOS_0 UC11 Status Register EMIOS0_UC11_SS 32-bit Base + 0x0190 Reserved — — Base + 0x0194 – Base + 0x019F MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 846: Register Map
Base + 0x0214 – Base + 0x021F eMIOS_0 UC16 A Register EMIOS0_UC16_A 32-bit Base + 0x0220 eMIOS_0 UC16 B Register EMIOS0_UC16_B 32-bit Base + 0x0224 eMIOS_0 UC16 CNT EMIOS0_UC16_CNT 32-bit Base + 0x0228 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 847: Register Map
Base + 0x02A8 – Base + 0x02AB eMIOS_0 UC20 Control Register EMIOS0_UC20_SC 32-bit Base + 0x02AC eMIOS_0 UC20 Status Register EMIOS0_UC20_SS 32-bit Base + 0x02B0 Reserved — — Base + 0x02B4 – Base + 0x02BF MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 848: Register Map
UC0 A Register eMIOS1_UC0_A 32-bit Base + 0x0020 eMIOS_1 UC0 B Register eMIOS1_UC0_B 32-bit Base + 0x0024 eMIOS_1 UC0 CNT eMIOS1_UC0_CNT 32-bit Base + 0x0028 eMIOS_1 UC0 Control Register eMIOS1_UC0_SC 32-bit Base + 0x002C MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 849: Register Map
32-bit Base + 0x00AC eMIOS_1 UC4 Status Register eMIOS1_UC4_SS 32-bit Base + 0x00B0 Reserved — — Base + 0x00B4 – Base + 0x00BF eMIOS_1 UC5 A Register eMIOS1_UC5_A 32-bit Base + 0x00C0 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 850: Register Map
32-bit Base + 0x0140 eMIOS_1 UC9 B Register eMIOS1_UC9_B 32-bit Base + 0x0144 Reserved — — Base + 0x0148 – Base + 0x014B eMIOS_1 UC9 Control Register eMIOS1_UC9_SC 32-bit Base + 0x014C MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 851: Register Map
32-bit Base + 0x01CC eMIOS_1 UC13 Status Register eMIOS1_UC13_SS 32-bit Base + 0x01D0 Reserved — — Base + 0x01D4 – Base + 0x01DF eMIOS_1 UC14 A Register eMIOS1_UC14_A 32-bit Base + 0x01E0 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 852: Register Map
32-bit Base + 0x0260 eMIOS_1 UC18 B Register eMIOS1_UC18_B 32-bit Base + 0x0264 Reserved — — Base + 0x0268 – Base + 0x026B eMIOS_1 UC18 Control Register eMIOS1_UC18_SC 32-bit Base + 0x026C MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 853: Register Map
32-bit Base + 0x02EC eMIOS_1 UC22 Status Register eMIOS1_UC22_SS 32-bit Base + 0x02F0 Reserved — — Base + 0x02F4 – Base + 0x02FF eMIOS_1 UC23 A Register eMIOS1_UC23_A 32-bit Base + 0x0300 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 854: Register Map
RUN1 Mode Configuration ME_RUN1_MC 32-bit Base + 0x0034 RUN2 Mode Configuration ME_RUN2_MC 32-bit Base + 0x0038 RUN3 Mode Configuration ME_RUN3_MC 32-bit Base + 0x003C HALT Mode Configuration ME_HALT_MC 32-bit Base + 0x0040 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 855: Register Map
Low Power Peripheral Configuration Registers ME_LP_PC7 32-bit Base + 0x00BC Reserved — — (Base + 0x00C0) – (Base + 0x00C3) DSPI0 Control ME_PCTL4 8-bit Base + 0x00C4 DSPI1 Control ME_PCTL5 8-bit Base + 0x00C5 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 856: Register Map
Base + 0x0104 WKPU Control ME_PCTL69 8-bit Base + 0x0105 Reserved — — (Base + 0x0106) – (Base + 0x0107) eMIOS0 Control ME_PCTL72 8-bit Base + 0x0108 eMIOS1 Control ME_PCTL73 8-bit Base + 0x0109 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 857: Register Map
Control Status Register CMU_CSR 32-bit Base + 0x0000 Frequency Display Register CMU_FDR 32-bit Base + 0x0004 High Frequency Reference Register CMU_HFREFR_A 32-bit Base + 0x0008 Low Frequency Reference Register CMU_LFREFR_A 32-bit Base + 0x000C MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 858: Register Map
Power Control Unit (MC_PCU) 0xC3FE_8000 Power domain #0 configuration register PCONF0 32-bit Base + 0x0000 Power domain #1 configuration register PCONF1 32-bit Base + 0x0004 Power domain #2 configuration register PCONF2 32-bit Base + 0x0008 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 859: Register Map
Base + 0x012C Timer Load Value Register 3 LDVAL3 32-bit Base + 0x0130 Current Timer Value Register 3 CVAL3 32-bit Base + 0x0134 Timer Control Register 3 TCTRL3 32-bit Base + 0x0138 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 860: Register Map
Threshold Control Register 1 TRC1 32-bit Base + 0x0054 Threshold Control Register 2 TRC2 32-bit Base + 0x0058 Threshold Control Register 3 TRC3 32-bit Base + 0x005C Threshold Register 0 THRHLR0 32-bit Base + 0x0060 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 861: Register Map
CDR2 32-bit Base + 0x0108 Channel 3 Data Register CDR3 32-bit Base + 0x010C Channel 4 Data Register CDR4 32-bit Base + 0x0110 Channel 5 Data Register CDR5 32-bit Base + 0x0114 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 862: Register Map
Base + 0x01C0 – 0x01FF Channel 64 Data Register CDR64 32-bit Base + 0x0200 Channel 65 Data Register CDR65 32-bit Base + 0x0204 Channel 66 Data Register CDR66 32-bit Base + 0x0208 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 863: Register Map
CDR93 32-bit Base + 0x0274 Channel 94 Data Register CDR94 32-bit Base + 0x0278 Channel 95 Data Register CDR95 32-bit Base + 0x027C Reserved — — Base + 0x0280 – 0x02FF 0xFFE3_0000 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 864: Register Map
Base + 0x004C Identifier filter control register 1 IFCR1 32-bit Base + 0x0050 Identifier filter control register 2 IFCR2 32-bit Base + 0x0054 Identifier filter control register 3 IFCR3 32-bit Base + 0x0058 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 865: Register Map
Base + 0x0034 Buffer data register LSB BDRL 32-bit Base + 0x0038 Buffer data register MSB BDRM 32-bit Base + 0x003C Reserved — — (Base + 0x0040)– (Base + 0x7FFF) LINFlex_2 0xFFE4_8000 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 866: Register Map
32-bit Base + 0x0024 LIN integer baud rate register LINIBRR 32-bit Base + 0x0028 LIN checksum field register LINCFR 32-bit Base + 0x002C LIN control register 2 LINCR2 32-bit Base + 0x0030 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 867: Register Map
Event Configuration Register21 CTU_EVTCFGR21 32-bit Base + 0x0084 Event Configuration Register22 CTU_EVTCFGR22 32-bit Base + 0x0088 Event Configuration Register23 CTU_EVTCFGR23 32-bit Base + 0x008C Event Configuration Register24 CTU_EVTCFGR24 32-bit Base + 0x0090 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 868: Register Map
Event Configuration Register53 CTU_EVTCFGR53 32-bit Base + 0x0104 Event Configuration Register54 CTU_EVTCFGR54 32-bit Base + 0x0108 Event Configuration Register55 CTU_EVTCFGR55 32-bit Base + 0x010C Event Configuration Register56 CTU_EVTCFGR56 32-bit Base + 0x0110 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 869: Register Map
MPU Error Detail Register, Slave Port 0 MPU_EDR0 32-bit Base + 0x0014 MPU Error Address Register, Slave Port 1 MPU_EAR1 32-bit Base + 0x0018 MPU Error Detail Register, Slave Port 1 MPU_EDR1 32-bit Base + 0x001c MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 870: Register Map
SWT Time-Out Register SWT_TO 32-bit Base + 0x0008 SWT Window Register SWT_WN 32-bit Base + 0x000C SWT Service Register SWT_SR 32-bit Base + 0x0010 SWT Counter Output Register SWT_CO 32-bit Base + 0x0014 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 871: Register Map
SOC-Defined Platform Revision ECSM_REV 16-bit Base + 0x0002 Reserved — — Base + (0x0004 – 0x0007) IPS On-Platform Module Configuration ECSM_IMC 32-bit Base + 0x0008 Reserved — — Base + (0x000C – 0x0012) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 872: Register Map
Platform RAM ECC Attributes Register ECSM_PREAT 8-bit Base + 0x0067 Reserved — — Base + (0x068 – 0x006B) Platform RAM ECC Data Register ECSM_PREDR 32-bit Base + 0x006C Reserved — — Base + (0x0070 – 0x3FFF) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 873: Register Map
Priority Select Register INTC_PSR52_55 32-bit Base + 0x0074 Priority Select Register INTC_PSR56_59 32-bit Base + 0x0078 Priority Select Register INTC_PSR60_63 32-bit Base + 0x007C Priority Select Register INTC_PSR64_67 32-bit Base + 0x0080 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 874: Register Map
Priority Select Register INTC_PSR180_183 32-bit Base + 0x00F4 Priority Select Register INTC_PSR184_187 32-bit Base + 0x00F8 Priority Select Register INTC_PSR188_191 32-bit Base + 0x00FC Priority Select Register INTC_PSR192_195 32-bit Base + 0x0100 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 875: Register Map
32-bit Base + 0x0080 Receive FIFO Registers RXFR2 32-bit Base + 0x0084 Receive FIFO Registers RXFR3 32-bit Base + 0x0088 Reserved — — (Base + 0x008C) – (Base + 0x3FFF) DSPI_1 0xFFF9_4000 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 876: Register Map
PMCR 32-bit Base + 0x0000 Reserved — — (Base + 0x0004) – (Base + 0x0007) Transfer Count Register 32-bit Base + 0x0008 Clock and Transfer Attribute Registers CTAR0 32-bit Base + 0x000C MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 877: Register Map
Rx Global Mask Register RXGMASK 32-bit Base + 0x0010 Rx 14 Mask Register RX14MASK 32-bit Base + 0x0014 Rx 15 Mask Register RX15MASK 32-bit Base + 0x0018 Error Counter Register 32-bit Base + 0x001C MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 878: Register Map
Message Buffer 13 MB13 128 bits Base + 0x0150 per MB Message Buffer 14 MB14 128 bits Base + 0x0160 per MB Message Buffer 15 MB15 128 bits Base + 0x0170 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 879: Register Map
Message Buffer 33 MB33 128 bits Base + 0x0290 per MB Message Buffer 34 MB34 128 bits Base + 0x02A0 per MB Message Buffer 35 MB35 128 bits Base + 0x02B0 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 880: Register Map
Message Buffer 53 MB53 128 bits Base + 0x03D0 per MB Message Buffer 54 MB54 128 bits Base + 0x03E0 per MB Message Buffer 55 MB55 128 bits Base + 0x03F0 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 881: Register Map
Base + 0x08B8 RX Individual Mask Register 15 RXIMR15 32-bit Base + 0x08BC RX Individual Mask Register 16 RXIMR16 32-bit Base + 0x08C0 RX Individual Mask Register 17 RXIMR17 32-bit Base + 0x08C4 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 882: Register Map
Base + 0x0938 RX Individual Mask Register 47 RXIMR47 32-bit Base + 0x093C RX Individual Mask Register 48 RXIMR48 32-bit Base + 0x0940 RX Individual Mask Register 49 RXIMR49 32-bit Base + 0x0944 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 883: Register Map
Interrupt Masks 1 Register IMASK1 32-bit Base + 0x0028 Interrupt Flags 2 Register IFLAG2 32-bit Base + 0x002C Interrupt Flags 1 Register IFLAG1 32-bit Base + 0x0030 Reserved — — Base + (0x0034 – 0x007F) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 884: Register Map
Message Buffer 17 MB17 128 bits Base + 0x0190 per MB Message Buffer 18 MB18 128 bits Base + 0x01A0 per MB Message Buffer 19 MB19 128 bits Base + 0x01B0 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 885: Register Map
Message Buffer 37 MB37 128 bits Base + 0x02D0 per MB Message Buffer 38 MB38 128 bits Base + 0x02E0 per MB Message Buffer 39 MB39 128 bits Base + 0x02F0 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 886: Register Map
Message Buffer 57 MB57 128 bits Base + 0x0410 per MB Message Buffer 58 MB58 128 bits Base + 0x0420 per MB Message Buffer 59 MB59 128 bits Base + 0x0430 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 887: Register Map
Base + 0x08D0 RX Individual Mask Register 21 RXIMR21 32-bit Base + 0x08D4 RX Individual Mask Register 22 RXIMR22 32-bit Base + 0x08D8 RX Individual Mask Register 23 RXIMR23 32-bit Base + 0x08DC MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 888: Register Map
Base + 0x0950 RX Individual Mask Register 53 RXIMR53 32-bit Base + 0x0954 RX Individual Mask Register 54 RXIMR54 32-bit Base + 0x0958 RX Individual Mask Register 55 RXIMR55 32-bit Base + 0x095C MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 889: Register Map
MB Message Buffer 1 128 bits Base + 0x0090 per MB Message Buffer 2 128 bits Base + 0x00A0 per MB Message Buffer 3 128 bits Base + 0x00B0 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 890: Register Map
Message Buffer 21 MB21 128 bits Base + 0x01D0 per MB Message Buffer 22 MB22 128 bits Base + 0x01E0 per MB Message Buffer 23 MB23 128 bits Base + 0x01F0 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 891: Register Map
Message Buffer 41 MB41 128 bits Base + 0x0310 per MB Message Buffer 42 MB42 128 bits Base + 0x0320 per MB Message Buffer 43 MB43 128 bits Base + 0x0330 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 892: Register Map
Message Buffer 61 MB61 128 bits Base + 0x0450 per MB Message Buffer 62 MB62 128 bits Base + 0x0460 per MB Message Buffer 63 MB63 128 bits Base + 0x0470 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 893: Register Map
Base + 0x08E8 RX Individual Mask Register 27 RXIMR27 32-bit Base + 0x08EC RX Individual Mask Register 28 RXIMR28 32-bit Base + 0x08F0 RX Individual Mask Register 29 RXIMR29 32-bit Base + 0x08F4 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 894: Register Map
Base + 0x0968 RX Individual Mask Register 59 RXIMR59 32-bit Base + 0x096C RX Individual Mask Register 60 RXIMR60 32-bit Base + 0x0970 RX Individual Mask Register 61 RXIMR61 32-bit Base + 0x0974 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 895: Register Map
MB Message Buffer 4 128 bits Base + 0x00C0 per MB Message Buffer 5 128 bits Base + 0x00D0 per MB Message Buffer 6 128 bits Base + 0x00E0 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 896: Register Map
Message Buffer 24 MB24 128 bits Base + 0x0200 per MB Message Buffer 25 MB25 128 bits Base + 0x0210 per MB Message Buffer 26 MB26 128 bits Base + 0x0220 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 897: Register Map
Message Buffer 44 MB44 128 bits Base + 0x0340 per MB Message Buffer 45 MB45 128 bits Base + 0x0350 per MB Message Buffer 46 MB46 128 bits Base + 0x0360 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 898: Register Map
(Base + 0x087F) RX Individual Mask Register 0 RXIMR0 32-bit Base + 0x0880 RX Individual Mask Register 1 RXIMR1 32-bit Base + 0x0884 RX Individual Mask Register 2 RXIMR2 32-bit Base + 0x0888 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 899: Register Map
Base + 0x08FC RX Individual Mask Register 32 RXIMR32 32-bit Base + 0x0900 RX Individual Mask Register 33 RXIMR33 32-bit Base + 0x0904 RX Individual Mask Register 34 RXIMR34 32-bit Base + 0x0908 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 900: Register Map
RX Individual Mask Register 62 RXIMR62 32-bit Base + 0x0978 RX Individual Mask Register 63 RXIMR63 32-bit Base + 0x097C Reserved — — (Base + 0x0980) – (Base + 0x3FFF) FlexCAN_4 0xFFFD_0000 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 901: Register Map
MB Message Buffer 7 128 bits Base + 0x00F0 per MB Message Buffer 8 128 bits Base + 0x0100 per MB Message Buffer 9 128 bits Base + 0x0110 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 902: Register Map
Message Buffer 27 MB27 128 bits Base + 0x0230 per MB Message Buffer 28 MB28 128 bits Base + 0x0240 per MB Message Buffer 29 MB29 128 bits Base + 0x0250 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 903: Register Map
Message Buffer 47 MB47 128 bits Base + 0x0370 per MB Message Buffer 48 MB48 128 bits Base + 0x0380 per MB Message Buffer 49 MB49 128 bits Base + 0x0390 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 904: Register Map
Base + 0x0890 RX Individual Mask Register 5 RXIMR5 32-bit Base + 0x0894 RX Individual Mask Register 6 RXIMR6 32-bit Base + 0x0898 RX Individual Mask Register 7 RXIMR7 32-bit Base + 0x089C MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 905: Register Map
Base + 0x0910 RX Individual Mask Register 37 RXIMR37 32-bit Base + 0x0914 RX Individual Mask Register 38 RXIMR38 32-bit Base + 0x0918 RX Individual Mask Register 39 RXIMR39 32-bit Base + 0x091C MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 906: Register Map
Control Register CTRL 32-bit Base + 0x0004 Free Running Timer TIMER 32-bit Base + 0x0008 Reserved — — Base + (0x000C – 0x000F) Rx Global Mask Register RXGMASK 32-bit Base + 0x0010 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 907: Register Map
Message Buffer 11 MB11 128 bits Base + 0x0130 per MB Message Buffer 12 MB12 128 bits Base + 0x0140 per MB Message Buffer 13 MB13 128 bits Base + 0x0150 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 908: Register Map
Message Buffer 31 MB31 128 bits Base + 0x0270 per MB Message Buffer 32 MB32 128 bits Base + 0x0280 per MB Message Buffer 33 MB33 128 bits Base + 0x0290 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 909: Register Map
Message Buffer 51 MB51 128 bits Base + 0x03B0 per MB Message Buffer 52 MB52 128 bits Base + 0x03C0 per MB Message Buffer 53 MB53 128 bits Base + 0x03D0 per MB MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 910: Register Map
Base + 0x08A8 RX Individual Mask Register 11 RXIMR11 32-bit Base + 0x08AC RX Individual Mask Register 12 RXIMR12 32-bit Base + 0x08B0 RX Individual Mask Register 13 RXIMR13 32-bit Base + 0x08B4 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 911: Register Map
Base + 0x0928 RX Individual Mask Register 43 RXIMR43 32-bit Base + 0x092C RX Individual Mask Register 44 RXIMR44 32-bit Base + 0x0930 RX Individual Mask Register 45 RXIMR45 32-bit Base + 0x0934 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 912: Register Map
Base + 0x0974 RX Individual Mask Register 62 RXIMR62 32-bit Base + 0x0978 RX Individual Mask Register 63 RXIMR63 32-bit Base + 0x097C Reserved — — (Base + 0x0980) – (Base + 0x3FFF) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 913 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 914: B.1 Changes Between Revisions 7 And 8
Appendix B Revision History This appendix describes corrections to the MPC5604B Microcontroller Reference Manual. For convenience, the corrections are grouped by revision. Changes between revisions 7 and 8 Table B-1. Changes between revisions 7 and 8 Chapter Description Throughout Editorial changes and improvements (including reformatting of memory maps, register figures, and field descriptions to a consistent format).
Page 915 Chapter Description Clock Description Replaced the “MPC5604B system clock generation” figure with the version present in Rev. 5 of the MPC5604B reference manual. Fast external crystal oscillator (FXOSC) digital interface section: Changed the sentence from “The FXOSC digital interface controls the 4–40 MHz fast external crystal oscillator (FXOSC).”...
Page 916 Deleted the duplicate register map. In the “CAN sampler memory map” table, added the module base address. e200z0h Core In the “e200z0h block diagram” figure, added a box around the core elements. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 917 Added the “Transmit/receive sequence” section. In the “Generation of STOP” section, in the code sample, changed “bit 1” to “bit 5”. In the “I2C memory map” table, added the module base address. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 918 In the Features section, changed “Three test data registers” to “2 test data registers”. Access Port Controller In the “SAMPLE instruction” section, added information about pad status. In the “SAMPLE/PRELOAD instruction” section, added information about pad status. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 919: B.2 Changes Between Revisions 5 And 7
Interrupt functionalities are not available on SXOSC Boot Assist Module Added notes in the following section: Download 64-bit password and password check Download data Execute code 1.Rev. 6 was not publicly released. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 920 Removed “Control Status Register (CTU_CSR)” because the interrupt feature is not implemented. Cross Triggering Unit block diagram: trigger output control and output signals removed Main Features section: Removed “Maskable interrupt generation whenever a trigger output is generated”. Feature not implemented. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 921: B.3 Changes Between Revisions 4 And 5
“DSPIx_MCR register“: Peripheral Interface – Included Bit fields CLR_TXF and CLR_RXF. LIN Controller “LINTCSR“ register: – Updated the reset value. FlexCAN “Control Register (CTRL) field description” table: – Sorted correctly the bit fields. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 922: B.4 Changes Between Revisions 2 And 4
– Changed the “Reset config.” of PB[7] and PB[8] to Tristate – Changed “Pad Type“ from S to M in 27 pads – Changed pad type from S to M on port pin PE[7] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 923 Chapter title change Replaced “AIPS” with “peripheral bridge”, or “PBRIDGE” where appropriate, throughout chapter Peripheral bridge interface: Updated PBRIDGE1 peripheral names Updated Section 11.1.4, “Modes of operation” Crossbar Switch Updated XBAR block diagram MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 924 Section 16.7.4, “Nexus Messaging”: Removed sentence referencing Client Select Control Register Section 16.7.6.1, “EVTI Generated Break Request”: Removed sentence referencing Shared Nexus Control (SNC) Register (SNC register not implemented on this device) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 925 PFCR0 field descriptions: Modified field descriptions for BK0_APC, BK0_WWSC and BK0_RWSC PFCR1 field descriptions: Modified field descriptions for BK1_APC, BK1_WWSC and BK1_RWSC Section 18.5.13, “Timing diagrams”: Reformatted and rescaled timing diagrams to improve readability and alignment of content MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 926 Section 19.6, “Functional description”: Removed all DMA requests content and eDMA controller content Section 19.7.1, “How to change queues”: Modified list of events: Was 1–11, is 1–7 Updated Section 19.7.3, “Delay settings” MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 927 – Amended address offsets for IFCR2n and for IFCR2n+1 Added Section 21.8.1.4, “Clock gating Section 21.8.1, “UART mode Section 21.8.2, “LIN mode: Added footnote regarding slave mode Updated Section 21.8.2.1.3, “Data reception (transceiver as subscriber) MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 928 IBSR field descriptions: Removed comment “Check w/design if this is the case (only TCF)” from description of field IBIF Section 26.5.2.2, “Interrupt description”: Removed comment “To be checked” from Byte Transfer condition MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 929 Presampling Control Register (PSCR) field descriptions: Updated descriptions for PREVAL fields Section 25.4.12, “Conversion timing registers CTR[01..12]”: Restored OFFSHIFT field Channel Data Register (CDR[0..95]) field descriptions: – Updated description for field OVERW – Added value ‘11’ to field RESULT[0:1] MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 930 – Updated description of RSER – Replaced “Program Flash A Configuration” with “Code Flash A Configuration” – Replaced registers IFER, IFMI, IFMR, IFCR2n and IFCR2n+1 with “Reserved” for LINFlex modules 1, 2 and 3 MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 931: B.5 Changes Between Revisions 1 And 2
Replaced the entire chapter. Boot Assist Module - Aligned naming of LINFlex module. Section 8.3.4.3, “BAM resources”: Removed any references to STM, CMU and FMPLL. Reset Generation Replaced the entire chapter. Module MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 932 - Fixed information about the number of frames accumulated in the FIFO to generate a warning interrupt, which is 5. (Affected sections: Section 21.3.4.12, “Interrupt Flags 1 Register (IFLAG1)” Section 21.4.8, “Rx FIFO”). Section 21.4.2, “Local priority transmission”: added. MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 933 13-1: Updated to explain that “RTC Rollover wakeup“ and “RTC cnt_or_rlovr“ are Interrupt not connected on MPC5604B. Figure 13.4: Removed section “Test mode“. - Removed section “External Signal Description“. Voltage Regulators and Aligned the electrical value with data sheet. Power Supplies MPC5604B/C Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor...
Page 934 Exchange Building 23F application in which the failure of the Freescale Semiconductor product could No. 118 Jianguo Road create a situation where personal injury or death may occur. Should Buyer...

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