Appendix B, 56F826EVM Bill of Material - provides a list of the materials used on the 56F826EVM board Suggested Reading More documentation on the 56F826 and the 56F826EVM kit may be found at URL: http://www.freescale.com Preface, Rev. 2 Freescale Semiconductor...
Numbers Considered positive Voltage is often shown as unless specifically positive: +3.3V noted as a negative value Blue Text Linkable on-line ...refer to Figure 1-1 Bold Reference sources, ...see: paths, emphasis http://www.freescale.com/ 56F826EVM User Manual, Rev. 2 viii Freescale Semiconductor...
Printed Circuit Board Phase Locked Loop Random Access Memory Read-Only Memory Serial Communications Interface Port Serial Peripheral Interface Port SRAM Static Random Access Memory Synchronous Serial Interface Port Wait State Preface, Rev. 2 Freescale Semiconductor...
References The following sources were used to produce this manual: [1] DSP56800 Family Manual, , DSP56800FM, Freescale Semiconductor [2] 56F826/827 User’s Manual, DSP56F826-827UM, Freescale Semiconductor [3] 56F826 Technical Data, DSP56F826, Freescale Semiconductor 56F826EVM User Manual, Rev. 2 Freescale Semiconductor...
Chapter 1 Introduction The 56F826EVM is used to demonstrate the abilities of the 56F826 and to provide a hardware tool allowing the development of applications that use the 56F826. The 56F826EVM is an evaluation module board that includes a 56F826 part, 16-bit stereo codec, external memory and a daughter card expansion interface.
The 56F826EVM is flexible enough to allow a user to fully exploit the 56F826's features to optimize the performance of his product, as shown in Figure 1-1.
1–2, 3–4, 5–6 & 7–8 1.3 56F826EVM Connections An interconnection diagram is shown in for connecting the PC and the external Figure 1-3 +12.0V DC power supply or external +5.0V DC lab power supply to the 56F826EVM board. Introduction, Rev. 2 Freescale Semiconductor...
1-3. Optionally, attach an external +5.0V DC lab power supply via the 2-pin terminal block, TB1. 5. Apply power to the external power supply. The green Power-On LED, LED7, will illuminate when power is applied correctly. 56F826EVM User Manual, Rev. 2 Freescale Semiconductor...
The power of the 16-bit 56F826 device, combined with the on-board 16-bit external program static RAM (SRAM), 64K...
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The 56F826EVM uses a Freescale DSP56F826BU80 part, designated as U1 on the board and in the schematics. This part will operate at a maximum speed of 80MHz. A full description of the 56F826, including functionality and user information, is provided in these documents: • 56F826 Preliminary Technical Data Sheet, (DSP56F826-827 UM): Provides features list and specifications including signal descriptions, DC power requirements, AC timing requirements and available packaging.
This memory bank will operate with zero wait state accesses while the 56F826 is running at 70MHz. However, when running at 80MHz, the memory bank operates with four wait state accesses. This memory bank can be disabled by removing the jumper at JG3.
2-2. This memory connects directly to the SPI Port through a Figure header on the 56F826. It can be used to load program code and data into the 56F826’s internal or external memory spaces. A jumper block, JG7, is provided, which allows the user to disconnect the on-board SPI EEPROM from the SPI port and to connect his own SPI port peripheral.
P3. Flow control is not provided, but could be implemented using uncommitted GPIO signals. The pinout of connector P3 is listed 2-2. The RS-232 level converter/transceiver can be disabled by placing a jumper at JG2. Table RS-232 56F826 Level Converter Interface T1in T1out...
The 56F826EVM uses a 4.00MHz crystal, Y1, connected to its External Crystal Inputs, EXTAL and XTAL. To achieve its 80MHz maximum operating frequency, the 56F826 uses its internal PLL to multiply the input frequency by 20. An external oscillator source can be connected to the controller by using the oscillator bypass connectors, JG4 and JG5;...
PB0 signal. User LED2 is controlled by PB1. User LED3 is controlled by PB2. User LED4 is controlled by PB3. User LED5 is controlled by PB4. User LED6 is controlled by PB5. Setting PB0, PB1, PB2, PB3, PB4 or PB5 to a Logic One value will turn on the associated LED. 56F826 INVERTING BUFFER +3.3V...
The JTAG connector on the 56F826EVM allows the connection of an external Host Target Interface for downloading programs and working with the 56F826’s registers. This connector is used to communicate with an external Host Target Interface which passes information and data back and forth with a host processor running a debugger program.
Debug Support 2.8.2 Parallel JTAG Interface Connector The Parallel JTAG Interface Connector, P2, allows the 56F826 to communicate with a Parallel Printer Port on a Windows PC; reference 2-6. By using this connector, the user can Figure download programs and work with the 56F826’s registers.
2-7. SW2 allows the user to generate a hardware interrupt for signal line IRQA. SW3 Figure allows the user to generate a hardware interrupt for signal line IRQB. These two switches allow the user to generate interrupts for his user-specific programs. +3.3V 56F826 IRQA 0.1µF +3.3V IRQB 0.1µF...
Reset 2.10 Reset Logic is provided on the 56F826 to generate an internal Power-On RESET. Additional reset logic is provided to support the RESET signals from the JTAG connector, the Parallel JTAG Interface and the user RESET push-button; refer to Figure 2-8.
56F826EVM is indicated with a Power-On LED, referenced as LED7. Power +5.0V DC +5.0V CODEC +12.0V DC Condition Analog Regulator +3.3 VDC +3.3V 56F826 +5.0V DC Regulator 56F826EVM PARTS +2.5V DC 56F826 +2.5V CORE Regulator Figure 2-9. Schematic Diagram of the Power Supply 56F826EVM User Manual, Rev.
A 16-bit audio quality stereo codec, Crystal Semiconductor CS4218, is connected to the 56F826’s SSI port to support audio, voice and signal analysis applications. The codec is clocked with a 12.288MHz oscillator, allowing the codec to operate between a sample frequency of 8kHz and 48kHz.
The Serial Transmit Frame Sync pin, STFS, is programmed to control the codec’s Frame Sync, FSYNC, signal. FSYNC is sampled by SCLK, with a rising edge indicating that a new frame is 56F826EVM User Manual, Rev. 2 2-14 Freescale Semiconductor...
Table 2-7 information is sent over a separate serial port using: PD1 as the Control Chip Select, CCS, signal; PD2 as the Control Data Input, CDIN, signal; and PD3 as the Control Clock, CCLK, signal. 56F826 CS4218 CODEC Enable Logic...
The controller’s external memory bus signals are connected to the Memory Daughter Card Expansion connector, J1. shows the port signal to pin assignments. Table 2-8 Table 2-8. Memory Daughter Card Connector Description Pin # Signal Pin # Signal 56F826EVM User Manual, Rev. 2 2-16 Freescale Semiconductor...
The controller’s peripheral port signals are connected to the Peripheral Daughter Card Expansion connector, J2. shows the port signal to pin assignments. Table 2-9 Table 2-9. Peripheral Daughter Card Connector Description Pin # Signal Pin # Signal CLKO SRFS SCLK MOSI Technical Summary, Rev. 2 Freescale Semiconductor 2-17...
The +5.0VA and AGND test points are located in the analog corner of the board. The +2.5V and +3.3V test points are located in the power supply section of the board. 56F826EVM User Manual, Rev. 2 2-18 Freescale Semiconductor...
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56F826EVM User Manual, Rev. 2 Index-iv Freescale Semiconductor...
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LDCForFreescaleSemiconductor@hibbertgroup.com application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended...
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