Freescale Semiconductor 56F800 User Manual page 118

Register Definitions
4.6.2.5 PLL Divide-By (PLLDB)—Bits 6–0
The output frequency of the PLL is primarily controlled by the PLLDB register. If N is the value
written to the PLLDB register, the output frequency F
where
Example:
then
Let N = 19 then
Before changing the PLLDB register it is recommended the core clock be first switched from the
postscaler output to the prescaler output (ZSRC = 001b). Notice also, the lock detect circuit is
reset when writing to the PLLDB register.
The value written to this register, plus one, is used by the PLL to directly multiply the input
frequency and present it at its output. For example, if the input frequency is 8MHz and the
PLLDB[6:0] register is set to 14, then the PLL output frequency is 120MHz.
Using the default bits shown in
EXTAL_CLK, seen in
160MHz, resulting in an FOUT/2 of 80MHz. Before changing the divide-by value, it is
recommended the core clock be first switched to the prescaler clock.
Note: Upon writing to the PLLDB register, the lock detect circuit is reset.
12
F = F
OUT-PLL IN-PLL
F is the PLL input frequency
IN-PLL
F = 4MHz and PLLCD is set to divide by 1
XTAL
F = F
IN_PLL
F F
OUT-PLL =
= 4Mhz × 20
= 80MHz
Figure 4-7, the value is (19 +1), or 20. For an 8MHz
Figure 4-11, this default value sets the output of the PLL, FOUT, to
56F826/827 User Manual, Rev. 3
is then given by
OUT_PLL
- (N +1)
/1 = 4MH
Z
XTAL
× (19 +1)
IN-PLL
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