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FlexRay MFR4310
Freescale Semiconductor FlexRay MFR4310 Manuals
Manuals and User Guides for Freescale Semiconductor FlexRay MFR4310. We have
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Freescale Semiconductor FlexRay MFR4310 manual available for free PDF download: Reference Manual
Freescale Semiconductor FlexRay MFR4310 Reference Manual (268 pages)
Communication Controllers
Brand:
Freescale Semiconductor
| Category:
Controller
| Size: 1 MB
Table of Contents
Table of Contents
7
List of Figures
13
Additional Reading
25
Audience
25
Table 1-1. Acronyms and Abbreviations
26
Terminology
26
Figure 1-1. Order Part Number Coding
27
Part Number Coding
27
Table 1-2. Notational Conventions
27
Chapter 1 Device Overview
29
Features
29
Introduction
29
Block Diagram
31
Figure 2-1. MFR4310 Functional Block Diagram
31
Memory Map
32
Table 2-1. MFR4310 Device Memory Map after Reset
32
Part ID and Module Version Number Assignments
33
Signal Descriptions
33
System Pinout
33
Table 2-2. Part ID and Module Version Numbers
33
Figure 2-2. MFR4310 Pin Assignment
34
Pin Functions and Signal Properties
35
Table 2-3. Pin Functions and Signal Properties
35
Detailed Signal Descriptions
38
Figure 2-3. Oscillator Connections
43
Figure 2-4. External Square Wave Clock Generator Connection
43
Power Supply Pins
44
Table 2-4. MFR4310 Power and Ground Connection Summary
44
External Clock and Host Interface Selection
45
External 4/10/40 Mhz Output Clock
45
Table 2-5. CLKOUT Frequency Selection
45
External Host Interface Selection
46
Table 2-6. Interface Selection
46
Recommended Pullup/Pulldown Resistor Values
47
Modes of Operation
45
External Host Interface
47
Asynchronous Memory Interface
47
Table 2-7. Recommended Pullup and Pulldown Resistor Values for IF_SEL[1:0] Inputs
47
Table 2-8. AMI Access Types
47
Figure 2-5. AMI Interface with S12X Family
49
MPC Interface
50
Figure 2-6. AMI Interface with DSP 56F83 (Hawk) Family
50
Table 2-9. MPC Interface Access Types
51
HCS12 Interface
52
Figure 2-7. MPC EBI Interface with Mpc5Xx and Mpc55Xx Families
52
Table 2-10. HCS12 Access Types
53
Figure 2-8. HCS12 Interface Address Decoding and Internal Chip Select Generation
54
Figure 2-9. HCS12 Interface with HCS12 Page Mode Support
55
Resets and Interrupts
56
Resets
56
Figure 2-10. HCS12 Interface with HCS12 Unpaged Mode Support
56
Interrupt Sources
57
Chapter 3 Flexray Module (FLEXRAYV4)
59
Introduction
59
Reference
59
Glossary
59
Table 3-1. List of Terms
59
Color Coding
60
Overview
60
Features
61
Figure 3-1. Flexray Module Block Diagram
61
Modes of Operation
63
External Signal Description
64
Detailed Signal Descriptions
64
Table 3-2. External Signal Properties
64
Memory Map and Register Description
65
Memory Map
65
Table 3-3. Flexray Memory Map
65
Register Descriptions
68
Table 3-4. Register Access Conventions
68
Table 3-5. Additional Register Reset Conditions
69
Table 3-6. Register Write Access Restrictions
69
Figure 3-2. Module Version Register (MVR)
70
Figure 3-3. Module Configuration Register (MCR)
70
Table 3-7. MVR Field Descriptions
70
Table 3-8. MCR Field Descriptions
71
Table 3-9. Flexray Channel Selection
71
Figure 3-4. Strobe Signal Control Register (STBSCR)
72
Table 3-10. Flexray Channel Bit Rate Selection
72
Table 3-11. STBSCR Field Descriptions
73
Table 3-12. Strobe Signal Mapping
73
Figure 3-5. Message Buffer Data Size Register (MBDSR)
75
Figure 3-6. Message Buffer Segment Size and Utilization Register (MBSSUTR)
76
Table 3-13. MBDSR Field Descriptions
76
Table 3-14. MBSSUTR Field Descriptions
76
Figure 3-7. Protocol Operation Control Register (POCR)
77
Table 3-15. POCR Field Descriptions
77
Figure 3-8. Global Interrupt Flag and Enable Register (GIFER)
78
Table 3-16. GIFER Field Descriptions
79
Figure 3-9. Protocol Interrupt Flag Register 0 (PIFR0)
81
Table 3-17. PIFR0 Field Descriptions
81
Figure 3-10. Protocol Interrupt Flag Register 1 (PIFR1)
83
Table 3-18. PIFR1 Field Descriptions
83
Figure 3-11. Protocol Interrupt Enable Register 0 (PIER0)
84
Table 3-19. PIER0 Field Descriptions
84
Figure 3-12. Protocol Interrupt Enable Register 1 (PIER1)
85
Table 3-20. PIER1 Field Descriptions
85
Figure 3-13. CHI Error Flag Register (CHIERFR)
86
Table 3-21. CHIERFR Field Descriptions
86
Figure 3-14. Message Buffer Interrupt Vector Register (MBIVEC)
88
Table 3-22. MBIVEC Field Descriptions
88
Figure 3-15. Channel a Status Error Counter Register (CASERCR)
89
Figure 3-16. Channel B Status Error Counter Register (CBSERCR)
89
Table 3-23. CASERCR Field Descriptions
89
Table 3-24. CBSERCR Field Descriptions
89
Figure 3-17. Protocol Status Register 0 (PSR0)
90
Table 3-25. PSR0 Field Descriptions
90
Figure 3-18. Protocol Status Register 1 (PSR1)
91
Figure 3-19. Protocol Status Register 2 (PSR2)
92
Table 3-26. PSR1 Field Descriptions
92
Table 3-27. PSR2 Field Descriptions
93
Figure 3-20. Protocol Status Register 3 (PSR3)
94
Table 3-28. PSR3 Field Descriptions
95
Figure 3-21. Macrotick Counter Register (MTCTR)
96
Figure 3-22. Cycle Counter Register (CYCTR)
96
Table 3-29. MTCTR Field Descriptions
96
Table 3-30. CYCTR Field Descriptions
96
Figure 3-23. Slot Counter Channel a Register (SLTCTAR)
97
Figure 3-24. Slot Counter Channel B Register (SLTCTBR)
97
Figure 3-25. Rate Correction Value Register (RTCORVR)
97
Table 3-31. SLTCTAR Field Descriptions
97
Table 3-32. SLTCTBR Field Descriptions
97
Figure 3-26. Offset Correction Value Register (OFCORVR)
98
Figure 3-27. Combined Interrupt Flag Register (CIFRR)
98
Table 3-33. RTCORVR Field Descriptions
98
Table 3-34. OFCORVR Field Descriptions
98
Table 3-35. CIFRR Field Descriptions
99
Figure 3-28. Sync Frame Counter Register (SFCNTR)
100
Figure 3-29. Sync Frame Table Offset Register (SFTOR)
100
Table 3-36. SFCNTR Field Descriptions
100
Figure 3-30. Sync Frame Table Configuration, Control, Status Register (SFTCCSR)
101
Table 3-37. SFTOR Field Description
101
Table 3-38. SFTCCSR Field Descriptions
101
Figure 3-31. Sync Frame ID Rejection Filter Register (SFIDRFR)
102
Table 3-39. SFIDRFR Field Descriptions
102
Figure 3-32. Sync Frame ID Acceptance Filter Value Register (SFIDAFVR)
103
Figure 3-33. Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR)
103
Figure 3-34. Network Management Vector Registers (NMVR0-NMVR5)
103
Table 3-40. SFIDAFVR Field Descriptions
103
Table 3-41. SFIDAFMR Field Descriptions
103
Table 3-42. NMVR[0:5] Field Descriptions
104
Table 3-43. Mapping of Nmvrn to the Received Payload Bytes Nmvn
104
Table 3-44. NMVLR Field Descriptions
104
Figure 3-36. Timer Configuration and Control Register (TICCR)
105
Table 3-45. TICCR Field Descriptions
105
Figure 3-37. Timer 1 Cycle Set Register (TI1CYSR)
106
Figure 3-38. Timer 1 Macrotick Offset Register (TI1MTOR)
106
Table 3-46. TI1CYSR Field Descriptions
106
Table 3-47. TI1MTOR Field Descriptions
106
Figure 3-39. Timer 2 Configuration Register 0 (TI2CR0)
107
Figure 3-40. Timer 2 Configuration Register 1 (TI2CR1)
107
Table 3-48. TI2CR0 Field Descriptions
107
Figure 3-41. Slot Status Selection Register (SSSR)
108
Table 3-49. TI2CR1 Field Descriptions
108
Figure 3-42. Slot Status Counter Condition Register (SSCCR)
109
Table 3-50. SSSR Field Descriptions
109
Table 3-51. Mapping between Sssrn and Ssrn
109
Table 3-52. SSCCR Field Descriptions
110
Table 3-53. Mapping between Internal Ssccrn and Sscrn
110
Figure 3-43. Slot Status Registers (SSR0-SSR7)
111
Table 3-54. SSR0-SSR7 Field Descriptions
111
Figure 3-44. Slow Status Counter Registers (SSCR0-SSCR3)
112
Figure 3-45. MTS a Configuration Register (MTSACFR)
113
Figure 3-46. MTS B Configuration Register (MTSBCFR)
113
Table 3-55. SSCR0-SSCR3 Field Descriptions
113
Table 3-56. MTSACFR Field Descriptions
113
Figure 3-47. Receive Shadow Buffer Index Register (RSBIR)
114
Table 3-57. MTSBCFR Field Descriptions
114
Table 3-58. RSBIR Field Descriptions
114
Figure 3-48. Receive FIFO Selection Register (RFSR)
115
Figure 3-49. Receive FIFO Start Index Register (RFSIR)
115
Table 3-59. SEL Controlled Receiver FIFO Registers
115
Table 3-60. RFSR Field Descriptions
115
Table 3-61. RFSIR Field Descriptions
115
Figure 3-50. Receive FIFO Depth and Size Register (RFDSR)
116
Figure 3-51. Receive FIFO a Read Index Register (RFARIR)
116
Table 3-62. RFDSR Field Descriptions
116
Table 3-63. RFARIR Field Descriptions
116
Figure 3-52. Receive FIFO B Read Index Register (RFBRIR)
117
Figure 3-53. Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR)
117
Table 3-64. RFBRIR Field Descriptions
117
Table 3-65. RFMIDAFVR Field Descriptions
117
Figure 3-54. Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR)
118
Figure 3-55. Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR)
118
Figure 3-56. Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR)
118
Table 3-66. RFMIAFMR Field Descriptions
118
Table 3-67. RFFIDRFVR Field Descriptions
118
Figure 3-57. Receive FIFO Range Filter Configuration Register (RFRFCFR)
119
Figure 3-58. Receive FIFO Range Filter Control Register (RFRFCTR)
119
Table 3-68. RFFIDRFMR Field Descriptions
119
Table 3-69. RFRFCFR Field Descriptions
119
Figure 3-59. Last Dynamic Slot Channel a Register (LDTXSLAR)
120
Table 3-70. RFRFCTR Field Descriptions
120
Table 3-71. LDTXSLAR Field Descriptions
120
Figure 3-60. Last Dynamic Slot Channel B Register (LDTXSLBR)
121
Table 3-72. LDTXSLBR Field Descriptions
121
Table 3-73. Protocol Configuration Register Fields
121
Figure 3-61. Protocol Configuration Register 0 (PCR0)
123
Figure 3-62. Protocol Configuration Register 1 (PCR1)
123
Figure 3-63. Protocol Configuration Register 2 (PCR2)
123
Table 3-74. Wakeup Channel Selection
123
Figure 3-64. Protocol Configuration Register 3 (PCR3)
124
Figure 3-65. Protocol Configuration Register 4 (PCR4)
124
Figure 3-66. Protocol Configuration Register 5 (PCR5)
124
Figure 3-67. Protocol Configuration Register 6 (PCR6)
124
Figure 3-68. Protocol Configuration Register 7 (PCR7)
124
Figure 3-69. Protocol Configuration Register 8 (PCR8)
125
Figure 3-70. Protocol Configuration Register 9 (PCR9)
125
Figure 3-71. Protocol Configuration Register 10 (PCR10)
125
Figure 3-72. Protocol Configuration Register 11 (PCR11)
125
Figure 3-73. Protocol Configuration Register 12 (PCR12)
126
Figure 3-74. Protocol Configuration Register 13 (PCR13)
126
Figure 3-75. Protocol Configuration Register 14 (PCR14)
126
Figure 3-76. Protocol Configuration Register 15 (PCR15)
126
Figure 3-77. Protocol Configuration Register 16 (PCR16)
126
Figure 3-78. Protocol Configuration Register 17 (PCR17)
127
Figure 3-79. Protocol Configuration Register 18 (PCR18)
127
Figure 3-80. Protocol Configuration Register 19 (PCR19)
127
Figure 3-81. Protocol Configuration Register 20 (PCR20)
127
Figure 3-82. Protocol Configuration Register 21 (PCR21)
127
Figure 3-83. Protocol Configuration Register 22 (PCR22)
128
Figure 3-84. Protocol Configuration Register 23 (PCR23)
128
Figure 3-85. Protocol Configuration Register 24 (PCR24)
128
Figure 3-86. Protocol Configuration Register 25 (PCR25)
128
Figure 3-87. Protocol Configuration Register 26 (PCR26)
128
Figure 3-88. Protocol Configuration Register 27 (PCR27)
129
Figure 3-89. Protocol Configuration Register 28 (PCR28)
129
Figure 3-90. Protocol Configuration Register 29 (PCR29)
129
Figure 3-91. Protocol Configuration Register 30 (PCR30)
129
Figure 3-92. Message Buffer Configuration, Control, Status Registers (Mbccsrn)
130
Table 3-75. Mbccsrn Field Descriptions
130
Figure 3-93. Message Buffer Cycle Counter Filter Registers (Mbccfrn)
132
Table 3-76. Mbccfrn Field Descriptions
132
Table 3-77. Channel Assignment Description
132
Figure 3-94. Message Buffer Frame ID Registers (Mbfidrn)
133
Figure 3-95. Message Buffer Index Registers (Mbidxrn)
133
Table 3-78. Mbfidrn Field Descriptions
133
Table 3-79. Mbidxrn Field Descriptions
133
Functional Description
134
Message Buffer Concept
134
Physical Message Buffer
134
Figure 3-96. Physical Message Buffer Structure
134
Message Buffer Types
135
Figure 3-97. Individual Message Buffer Structure
136
Figure 3-98. Receive Shadow Buffer Structure
137
Figure 3-99. Receive FIFO Structure
138
Flexray Memory Layout
140
Figure 3-100. Example of FRM Layout
141
Physical Message Buffer Description
142
Figure 3-101. Frame Header Structure
143
Table 3-80. Frame Header Write Access Constraints
143
Table 3-81. Frame Header Field Descriptions
144
Figure 3-102. Receive Message Buffer Slot Status Structure (Chab)
146
Figure 3-103. Receive Message Buffer Slot Status Structure (Cha)
146
Figure 3-104. Receive Message Buffer Slot Status Structure (Chb)
146
Table 3-82. Receive Message Buffer Slot Status Content
146
Table 3-83. Receive Message Buffer Slot Status Field Descriptions
146
Figure 3-105. Transmit Message Buffer Slot Status Structure (Chab)
148
Figure 3-106. Transmit Message Buffer Slot Status Structure (Cha)
148
Figure 3-107. Transmit Message Buffer Slot Status Structure (Chb)
148
Table 3-84. Transmit Message Buffer Slot Status Content
148
Table 3-85. Transmit Message Buffer Slot Status Structure Field Descriptions
148
Table 3-86. Message Buffer Data Field Minimum Length
149
Figure 3-108. Message Buffer Data Field Structure
150
Individual Message Buffer Functional Description
151
Table 3-87. Frame Data Write Access Constraints
151
Table 3-88. Frame Data Field Descriptions
151
Table 3-89. Individual Message Buffer Types
152
Figure 3-109. Single Transmit Message Buffer Access Regions
153
Table 3-90. Single Transmit Message Buffer Access Regions Description
153
Figure 3-110. Single Transmit Message Buffer States
154
Table 3-91. Single Transmit Message Buffer State Description
154
Table 3-92. Single Transmit Message Buffer Application Transitions
155
Table 3-93. Single Transmit Message Buffer Module Transitions
156
Table 3-94. Single Transmit Message Buffer Transition Priorities
156
Figure 3-111. Message Transmission Timing
158
Figure 3-112. Message Transmission from Hlck State with Unlock
158
Figure 3-113. Null Frame Transmission from Idle State
159
Figure 3-114. Null Frame Transmission from Hlck State
159
Figure 3-115. Null Frame Transmission from Hlck State with Unlock
159
Figure 3-116. Null Frame Transmission from Idle State with Locking
160
Figure 3-117. Receive Message Buffer Access Regions
161
Figure 3-118. Receive Message Buffer States
162
Table 3-95. Receive Message Buffer Access Region Description
162
Table 3-96. Receive Message Buffer States and Access
162
Table 3-97. Receive Message Buffer Application Transitions
163
Table 3-98. Receive Message Buffer Module Transitions
164
Table 3-99. Receive Message Buffer Transition Priorities
164
Table 3-100. Receive Message Buffer Update
165
Figure 3-119. Message Reception Timing
166
Figure 3-120. Double Transmit Buffer Structure and Data Flow
168
Figure 3-121. Double Transmit Message Buffer Access Regions Layout
168
Table 3-101. Double Transmit Message Buffer Access Regions Description
169
Figure 3-122. Double Transmit Message Buffer State Diagram (Commit Side)
170
Table 3-102. Double Transmit Message Buffer State Description (Commit Side)
170
Figure 3-123. Double Transmit Message Buffer State Diagram (Transmit Side)
171
Table 3-103. Double Transmit Message Buffer State Description (Transmit Side)
171
Table 3-104. Double Transmit Message Buffer Host Transitions
172
Table 3-105. Double Transmit Message Buffer Module Transitions
173
Table 3-106. Double Transmit Message Buffer Transition Priorities
173
Figure 3-124. Internal Message Transfer in Streaming Commit Mode
175
Figure 3-125. Internal Message Transfer in Immediate Commit Mode
175
Individual Message Buffer Search
176
Table 3-107. Message Buffer Search Priority
177
Individual Message Buffer Reconfiguration
178
Figure 3-126. Inconsistent Channel Assignment
178
Receive FIFO
179
Figure 3-127. Message Buffer Reconfiguration Scheme
179
Figure 3-128. Received Frame FIFO Filter Path
182
Channel Device Modes
184
Figure 3-129. Dual Channel Device Mode
184
Figure 3-130. Single Channel Device Mode (Channel A)
185
Figure 3-131. Single Channel Device Mode (Channel B)
185
External Clock Synchronization
186
Sync Frame ID and Sync Frame Deviation Tables
186
Figure 3-132. External Offset Correction Write and Application Timing
186
Figure 3-133. External Rate Correction Write and Application Timing
186
Figure 3-134. Sync Table Memory Layout
187
Table 3-108. Sync Frame Table Generation Modes
188
MTS Generation
189
Figure 3-135. Sync Frame Table Trigger and Generation Timing
189
Sync Frame and Startup Frame Transmission
190
Sync Frame Filtering
191
Strobe Signal Support
192
Figure 3-136. Strobe Signal Timing (Type = Pulse, Clk_Offset = -2)
192
Figure 3-137. Strobe Signal Timing (Type = Pulse, Clk_Offset = +4)
192
Timer Support
193
Slot Status Monitoring
194
Figure 3-138. Slot Status Vector Update
194
Table 3-109. Slot Status Content
195
Figure 3-139. Slot Status Counting and Sscrn Update
196
Interrupt Support
197
Figure 3-140. Scheme of Cascaded Interrupt Request
200
Figure 3-141. INT_CC# Generation Scheme
201
Figure 3-142. Scheme of Combined Interrupt Flags
201
Clock Domain Crossing
202
Initialization Information
202
Lower Flexray Bit Rate Support
202
Table 3-110. Flexray Channel Bit Rate Control
202
Flexray Initialization Sequence
203
Number of Usable Message Buffers
203
Application Information
204
Shut down Sequence
204
Table 3-111. Minimum F Chi [Mhz] Examples (128 Message Buffers)
204
Protocol Control Command Execution
205
Table 3-112. Protocol Control Command Priorities
205
Protocol Reset Command
206
Chapter 4 Port Integration Module (PIM)
207
External Signal Description
207
Functional Mode
208
Table 4-1. Pin Functions (Functional Mode)
208
Reset Mode
209
Introduction
207
Overview
207
Features
207
Modes of Operation
207
PIM Memory Map and Registers
209
Table 4-2. Pin Functions (Reset Mode)
209
Table 4-3. Port Integration Module Memory Map
209
Port Integration Module Registers
210
Figure 4-1. Part ID Register (PIDR)
210
Figure 4-2. ASIC Version Number Register (AVNR) (for Maskset 1M63J)
210
Figure 4-3. Host Interface Pins Drive Strength Register (HIPDSR)
210
Figure 4-4. Physical Layer Pins Drive Strength Register (PLPDSR)
211
Table 4-4. HIPDSR Field Descriptions
211
Table 4-5. PLPDSR Field Descriptions
211
Figure 4-5. Host Interface Pins Pullup/Pulldown Enable Register (HIPPER)
212
Table 4-6. HIPPER Field Descriptions
212
Figure 4-6. Host Interface Pins Pullup/Pulldown Control Register (HIPPCR)
213
Table 4-7. HIPPCR Field Descriptions
213
Figure 4-7. Physical Layer Pins Pullup/Pulldown Enable Register (PLPPER)
214
Functional Description
215
Functional Mode
215
Figure 4-8. Physical Layer Pins Pullup/Pulldown Control Register (PLPPCR)
215
Table 4-8. PLPPER Field Descriptions
215
Table 4-9. PLPPCR Field Descriptions
215
Reset Mode
216
Table 4-10. Reset Mode Interface
216
Chapter 5 Dual Output Voltage Regulator (VREG3V3V2)
217
Introduction
217
Features
217
Modes of Operation
217
Block Diagram
217
Figure 5-1. VREG3V3 Block Diagram
218
External Signal Description
219
Vddr , V Ssr
219
VDDA , V SSA - Regulator Reference Supply
219
VDD2_5 , VSS2_5 - Regulator Output1 (Core Logic)
219
Table 5-1. VREG3V3V2 - Signal Properties
219
VDDOSC , V SSOSC - Regulator Output2 (OSC)
220
Functional Description
220
REG - Regulator Core
220
Full-Performance Mode
220
POR - Power on Reset
220
LVR - Low Voltage Reset
221
CTRL - Regulator Control
221
Resets
221
Power on Reset
221
Low Voltage Reset
221
Table 5-2. VREG3V3V2 - Reset Sources
221
Chapter 6 Clocks and Reset Generator (CRG)
223
Introduction
223
Overview
223
Features
223
CRG Registers
224
Detection Enable Register (DER)
224
Figure 6-1. Detection Enable Register (DER)
224
Table 6-1. MFR4310 Relevant Pins for the CRG
224
Clock and Reset Status Register (CRSR)
225
Figure 6-2. Clock and Reset Status Register (CRSR)
225
Table 6-2. der Field Descriptions
225
Table 6-3. CRSR Field Descriptions
225
MFR4310 Relevant Pins for the CRG
224
Functional Description
226
Reset Generation
226
Table 6-4. CRG Reset Sources Priorities
226
Figure 6-3. CRG Power on Reset
227
Figure 6-4. Low Voltage Reset
228
Figure 6-5. Clock Monitor Failure Reset
228
Interface Selection
229
Figure 6-6. External Reset
229
CLKOUT Mode Selection and Control
230
Figure 6-7. Interface Selection During Power-On or Low Voltage Reset or Clock Monitor Failure
230
Figure 6-8. Interface Selection During External Reset
230
Table 6-5. IF_SEL[1:0] Encoding by CRSR.ECS
230
Figure 6-9. CLKOUT Mode Selection and Control During Low-Voltage Reset or
231
Figure 6-10. CLKOUT Mode Selection and Control During External Reset
232
Figure 6-11. CLKOUT Mode Selection and Control During Power-On Reset
233
Chapter 7 Oscillator (OSCV2)
235
External Signal Description
235
VDDOSC and VSSOSC - OSC Operating Voltage, OSC Ground
235
EXTAL and XTAL - Clock/Crystal Source Pins
235
Introduction
235
Features
235
Modes of Operation
235
Functional Description
236
Clock Monitor (CM)
236
Memory Map and Register Definition
236
Resets
236
Appendix A Electrical Characteristics
237
General
237
Parameter Classification
237
Power Supply
238
Pins
238
Current Injection
238
Absolute Maximum Ratings
239
Table A-1. Absolute Maximum Ratings
239
ESD Protection and Latch-Up Immunity
240
Table A-2. ESD and Latch-Up Test Conditions
240
Table A-3. ESD and Latch-Up Protection Characteristics
240
Operating Conditions
241
Power Dissipation and Thermal Characteristics
241
Table A-4. Operating Conditions
241
Table A-5. Thermal Package Simulation Details
243
I/O Characteristics
244
Table A-6. 5V I/O Characteristics (VDD5 = 5V)
244
Table A-7. 3.3V I/O Characteristics (VDD5 = 3.3V)
245
Supply Currents
246
Table A-8. Supply Current Characteristics
246
Voltage Regulator (VREG)
247
Operating Conditions
247
Table A-9. Voltage Regulator - Operating Conditions
247
Chip Power-Up and Voltage Drops
248
Output Loads
248
Figure A-1. Voltage Regulator - Chip Power-Up and Voltage Drops (Not Scaled)
248
Table A-10. Voltage Regulator Recommended Capacitive Loads
248
Reset and Oscillator
249
Startup
249
Table A-11. Startup Characteristics
249
Oscillator
250
Asynchronous Memory Interface Timing
250
Table A-12. Oscillator Characteristics
250
Figure A-2. AMI Interface Read Timing Diagram
251
Figure A-3. AMI Interface Write Timing Diagram
251
MPC Interface Timing
252
Table A-13. AMI Interface AC Switching Characteristics over the Operating Range
252
Figure A-4. MPC Interface Read Timing Diagram
253
Figure A-5. MPC Interface Write Timing Diagram
253
Table A-14. MPC Interface AC Switching Characteristics over the Operating Range
254
Figure A-6. HCS12 Interface Read Timing Diagram
255
Figure A-7. HCS12 Interface Write Timing Diagram
255
HCS12 Interface Timing
255
Table A-15. HCS12 Interface AC Switching Characteristics over the Operating Range
256
Figure B-1. 64-Pin LQFP Mechanical Dimensions (Case N 840F-02)
257
Figure B-2. 64-Pin LQFP Mechanical Dimensions (Case N 840F-02)
258
Figure B-3. 64-Pin LQFP Mechanical Dimensions (Case N 840F-02)
259
Table C-1. Suggested External Component Values
261
Figure C-1. Recommended PCB Layout (64-Pin LQFP) for Standard Pierce Oscillator Mode
262
Figure 3-35. Network Management Vector Length Register (NMVLR)
264
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