Freescale Semiconductor CPU32 Reference Manual

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Freescale Semiconductor, Inc.

CPU32

REFERENCE MANUAL

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Page 1 Freescale Semiconductor, Inc. CPU32 REFERENCE MANUAL Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
Page 2 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com...
Page 3 CPU32. Although there are comparative references to other Motorola micro- processors throughout the manual, Section 1, Section 2, and Appendix A specifi- cally identify the CPU32 within the M68000 Family, and discuss the differences betweeen it and related devices.
Page 4 Freescale Semiconductor, Inc. MOTOROLA CPU32 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 5: Table Of Contents
Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Title Page SECTION 1 OVERVIEW Features ....................1-1 1.1.1 Virtual Memory .................. 1-2 1.1.2 Loop Mode Instruction Execution ............1-2 1.1.3 Vector Base Register ................ 1-3 1.1.4 Exception Handling ................1-3 1.1.5 Enhanced Addressing Modes ............1-4 1.1.6...
Page 6 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page 3.4.3 Special Addressing Modes ..............3-7 3.4.3.1 Program Counter Indirect With Displacement ......3-7 3.4.3.2 Program Counter Indirect with Index (8-Bit Displacement) ..3-7 3.4.3.3 Program Counter Indirect with Index (Base Displacement) ..3-8 3.4.3.4...
Page 7 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page 4.6.3 Table Example 3: 8-Bit Independent Variable ....... 4-191 4.6.4 Table Example 4: Maintaining Precision ........4-192 4.6.5 Table Example 5: Surface Interpolations ........4-194 Nested Subroutine Calls ................ 4-194 Pipeline Synchronization with the NOP Instruction .......
Page 8 Normal Four-Word Stack Frame ............. 6-22 6.4.2 Normal Six-Word Stack Frame ............6-22 6.4.3 BERR Stack Frame ................. 6-22 SECTION 7 DEVELOPMENT SUPPORT CPU32 Integrated Development Support ..........7-1 7.1.1 Background Debug Mode (BDM) Overview ........7-1 7.1.2 Deterministic Opcode Tracking Overview ......... 7-2 7.1.3 On-Chip Hardware Breakpoint Overview ..........
Page 9 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page 7.2.8 Command Set ................. 7-11 7.2.8.1 Command Format ..............7-11 7.2.8.2 Command Sequence Diagram ..........7-12 7.2.8.3 Command Set Summary ............7-14 7.2.8.4 Read A/D Register (RAREG/RDREG) ........7-15 7.2.8.5 Write A/D Register (WAREG/WDREG) ........
Page 10 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page 8.3.3 MOVE Instruction ................8-14 8.3.4 Special-Purpose MOVE Instruction ..........8-14 8.3.5 Arithmetic/Logic Instructions ............8-15 8.3.6 Immediate Arithmetic/Logic Instructions .......... 8-17 8.3.7 Binary-Coded Decimal and Extended Instructions ......8-18 8.3.8...
Page 11 LIST OF ILLUSTRATIONS Figure Title Page Loop Mode Instruction Sequence ..............1-3 CPU32 Block Diagram ................... 1-7 User Programming Model ................2-2 Supervisor Programming Model Supplement ..........2-2 Status Register ....................2-3 Data Organization in Data Registers .............. 2-4 Address Organization in Address Registers ........... 2-5 Memory Operand Addressing ................
Page 12 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Title Page 8–3 Attributed Instruction Times ................8-4 Example 1 — Instruction Stream ..............8-7 Example 2 — Branch Taken ................8-8 Example 2 — Branch Not Taken ..............8-8 Example 3 — Branch Negative Tail ............... 8-9...
Page 13 Freescale Semiconductor, Inc. LIST OF TABLES Table Title Page 1-1 Instruction Set Summary ..................1-5 3-1 Effective Addressing Mode Categories..............3-11 4-1 Condition Code Computations................4-5 4-2 Data Movement Operations................... 4-6 4-3 Integer Arithmetic Operations ................4-7 4-4 Logic Operations....................4-8 4-5 Shift and Rotate Operations ..................
Page 14 Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Table Title Page MOTOROLA CPU32 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 15: Section 1 Overview
MC68000 processor. It has many features of the MC68010 and MC68020, as well as unique features suited for high-performance con- troller applications. The CPU32 is source code and binary code compatible with the M68000 Family.
Page 16: Virtual Memory
One of these features is the DBcc looping primitive. To increase the performance of the CPU32, a loop mode has been added to the processor. The loop mode is used by any single-word instruction that does not change the program flow. Loop mode is im- plemented in conjunction with the DBcc instruction.
Page 17: Vector Base Register
Freescale Semiconductor, Inc. ONE-WORD INSTRUCTION DBcc DBcc DISPLACEMENT $FFFC = –4 Figure 1-1 Loop Mode Instruction Sequence 1.1.3 Vector Base Register The vector base register (VBR) contains the base address of the 1024-byte exception vector table. The table contains 256 exception vectors. Exception vectors are the memory addresses of routines that begin execution at the completion of exception pro- cessing.
Page 18: Enhanced Addressing Modes
APPENDIX A M68000 FAMILY SUMMARY . 1.1.6 Instruction Set The instruction set of the CPU32 is very similar to that of the MC68020 (see Table 1- 1). Two new instructions have been added to facilitate controller applications — low- power stop (LPSTOP) and table lookup and interpolate (TBL).
Page 19 Freescale Semiconductor, Inc. to store a sample of the full range and recover intermediate values quickly via linear interpolation. A round-to-nearest algorithm can be applied to the results. Table 1-1 Instruction Set Summary Mnemonic Description Mnemonic Description ABCD Add Decimal with Extend...
Page 20: Low-Power Stop Instruction
1.2 Block Diagram A block diagram of the CPU32 is shown in Figure 1-2 . The functional elements oper- ate concurrently. Essential synchronization of instruction execution and buss opera- tion is maintained by the sequencer/control unit. The bus controller prefetches instructions and operands.
Page 21: Cpu32 Block Diagram
Freescale Semiconductor, Inc. SEQUENCER CONTROL INSTRUCTION UNIT PIPELINE DECODE DATA BUS BUS CONTROL EXECUTION CONTROL UNIT ADDRESS BUS Figure 1-2 CPU32 Block Diagram CPU32 OVERVIEW MOTOROLA REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 22 Freescale Semiconductor, Inc. MOTOROLA OVERVIEW CPU32 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 23: Section 2Architecture Summary
Freescale Semiconductor, Inc. SECTION 2ARCHITECTURE SUMMARY The CPU32 is upward source and object code compatible with the MC68000 and MC68010. It is downward source and object code compatible with the MC68020. With- in the M68000 Family, architectural differences are limited to the supervisory operating state.
Page 24: Registers
Freescale Semiconductor, Inc. 16 15 DATA REGISTERS 16 15 ADDRESS REGISTERS 16 15 A7 (USP) USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER Figure 2-1 User Programming Model 16 15 A7' (SSP) SUPERVISOR STACK POINTER (CCR) STATUS REGISTER VECTOR BASE REGISTER...
Page 25: Data Types
Alternate function code registers SFC and DFC contain 3-bit function codes. The CPU32 generates a function code each time it accesses an address. Specific codes are assigned to each type of access. The codes can be used to select eight dedicated 4G-byte address spaces.
Page 26: Organization In Registers
Freescale Semiconductor, Inc. 2.3.1 Organization in Registers The eight data registers can store data operands of 1, 8, 16, 32, and 64 bits and ad- dresses of 16 or 32 bits. The seven address registers and the two stack pointers are used for address operands of 16 or 32 bits.
Page 27: Address Registers
Freescale Semiconductor, Inc. BCD data represents decimal numbers in binary form. CPU32 BCD instructions use a format in which a byte contains two digits — the four LSB contain the low digit, and the four MSB contain the high digit. The ABCD, SBCD, and NBCD instructions operate on two BCD digits packed into a single byte.
Page 28: Organization In Memory
(N + 2), and the address of the least significant byte of the long word is (N + 3). The CPU32 requires data words and long words, as well as instruction words to be aligned on word boundaries. Data misalignment is not support- ed.
Page 29: Memory Operand Addressing
Freescale Semiconductor, Inc. BIT DATA 1 BYTE = 8 BITS BYTE DATA (8 BITS) BYTE 0 BYTE 1 BYTE 2 BYTE 3 WORD DATA / INSTRUCTION (16 BITS) WORD 0 WORD 1 WORD 2 LONG WORD DATA / INSTRUCTION (32 BITS)
Page 30 Freescale Semiconductor, Inc. MOTOROLA ARCHITECTURE SUMMARY CPU32 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 31: Section 3 Data Organization And Addressing Capabilities
Freescale Semiconductor, Inc. SECTION 3 DATA ORGANIZATION AND ADDRESSING CAPABILITIES The addressing mode of an instruction can specify the value of an operand (an imme- diate operand), a register that contains the operand (register direct addressing mode), or how the effective address of an operand in memory is derived. An assembler syntax has been defined for each addressing mode.
Page 32: Notation Conventions
Freescale Semiconductor, Inc. 3.2 Notation Conventions EA — Effective address An — Address register n Example: A3 is address register 3 Dn — Data register n Example: D5 is data register 5 Rn — Any register, data or address Xn.SIZE*SCALE —...
Page 33: Effective Address
Freescale Semiconductor, Inc. Instruction Implicit Registers ORI to CCR ORI to SR PC, SP PS, SP, SR PC, SP, SR PC, SP STOP TRAP (exception) SSP, SR TRAPV (exception) SSP, SR UNLK 3.4 Effective Address Most instructions specify the location of an operand by a field in the operation word called an effective address field or an effective address (〈EA〉).
Page 34: Memory Addressing Modes
Freescale Semiconductor, Inc. 3.4.2 Memory Addressing Modes These EA modes specify the address of the memory operand. 3.4.2.1 Address Register Indirect In the address register indirect mode, the operand is in memory, and the address of the operand is in the address register specified by the register field.
Page 35: Address Register Indirect With Displacement
Freescale Semiconductor, Inc. GENERATION: An = An SIZE EA = (An) ASSEMBLER SYNTAX: (An) MODE: REGISTER: ADDRESS REGISTER: MEMORY ADDRESS OPERAND LENGTH (1, 2, OR 4): MEMORY ADDRESS: OPERAND NUMBER OF EXTENSION WORDS: 3.4.2.4 Address Register Indirect With Displacement In the address register indirect with displacement mode, the operand is in memory.
Page 36: Address Register Indirect With Index (Base Displacement)
Freescale Semiconductor, Inc. GENERATION: EA = (An) + (Xn*SCALE) + d ASSEMBLER SYNTAX: (d An. SIZE*SCALE) MODE: REGISTER: ADDRESS REGISTER: MEMORY ADDRESS DISPLACEMENT: SIGN EXTENDED INTEGER SIGN-EXTENDED VALUE INDEX REGISTER: SCALE: SCALE VALUE MEMORY ADDRESS: OPERAND NUMBER OF EXTENSION WORDS: “Ri”...
Page 37: Special Addressing Modes
Freescale Semiconductor, Inc. 3.4.3 Special Addressing Modes These special addressing modes do not use the register field to specify a register num- ber but rather to specify a submode. 3.4.3.1 Program Counter Indirect With Displacement In this mode, the operand is in memory. The address of the operand is the sum of the address in the program counter and the sign-extended 16-bit displacement integer in the extension word.
Page 38: Program Counter Indirect With Index (Base Displacement)
Freescale Semiconductor, Inc. 3.4.3.3 Program Counter Indirect with Index (Base Displacement) This mode is similar to the address register indirect with index (base displacement) mode described in 3.4.2.6 Address Register Indirect With Index (Base Displace- ment), but the program counter is used as the base register. It requires an index reg- ister indicator and an optional 16- or 32-bit sign-extended base displacement.
Page 39: Absolute Long Address
Other indexed or indirect modes consist of the instruction word and the full format of extension words. The longest instruction for the CPU32 contains six extension words. It is a MOVE instruction with full format extension words for both source and destination EA and a 32-bit base displacement for both addresses.
Page 40: Effective Address Specification Formats
Freescale Semiconductor, Inc. SINGLE EA INSTRUCTION FORMAT EFFECTIVE ADDRESS MODE REGISTER BRIEF FORMAT EXTENSION WORD REGISTER W/ L SCALE DISPLACEMENT FULL FORMAT EXTENSION WORD(S) REGISTER W/ L SCALE BD SIZE I/IS BASE DISPLACEMENT (0, 1, OR 2 WORDS) Field Definition...
Page 41: Programming View Of Addressing Modes
#(data) 3.5.1 Addressing Capabilities In the CPU32, setting the base register suppress (BS) bit in the full format extension word (see Figure 3-2) suppresses use of the base address register in calculating the EA, allowing any index register to be used in place of the base register. Because any data register can be an index register, this provides a data register indirect form (Dn).
Page 42: Using Size In The Index Selection
USED IN ADDRESS CALCULATION Figure 3-3 Using SIZE in the Index Selection For the CPU32, the register indirect modes can be extended further. Because dis- placements can be 32 bits wide, they can represent absolute addresses or the results of expressions that contain absolute addresses. This scheme allows the general reg- ister indirect form to be (bd, Rn) or (bd, An, Rn) when the base register is not sup- pressed.
Page 43: Addressing Array Items
Freescale Semiconductor, Inc. included in the address calculation (bd, An, Rn ∗ SCALE). Another variation that can be derived is (An, Rn ∗ SCALE). In the first case, the array address is the sum of the contents of a register and a displacement (see Figure 3-5). In the second example, An contains the address of an array and Rn contains a subscript.
Page 44: General Addressing Mode Summary
The user object code of earlier members of the family is upwardly compatible with later members and can be executed without change. The address extension word(s) are encoded with information that allows the CPU32 to distinguish new additions to the basic M68000 Family architecture.
Page 45: Other Data Structures
11 = Scale Factor 8 (Extension to MC68000) Figure 3-6 M68000 Family Address Extension Words The encoding for SCALE used by the CPU32 and the MC68020 is a compatible ex- tension of the M68000 architecture. A value of zero for SCALE is the same encoding for both extension words;...
Page 46: User Stacks
Freescale Semiconductor, Inc. stack fills from high memory to low memory. The address mode –(SP) creates a new item on the active system stack, and the address mode (SP)+ deletes an item from the active system stack. The program counter is saved on the active system stack on subroutine calls and is restored from the active system stack on returns.
Page 47: Queues
Freescale Semiconductor, Inc. LOW MEMORY BOTTOM OF STACK TOP OF STACK (FREE) HIGH MEMORY 3.7.3 Queues Queues can be implemented using the address register indirect with postincrement or predecrement addressing modes. Queues are pushed from one end and pulled from the other, and use two registers.
Page 48 Freescale Semiconductor, Inc. LOW MEMORY (FREE) PUT – (An) LAST PUT NEXT GET GET – (Am) LAST GET (FREE) HIGH MEMORY To implement the queue as a circular buffer, the “get” or “put” operation should be per- formed first, and then the relevant address register should be checked and (if neces- sary) adjusted.
Page 49: Section 4 Instruction Set
The CPU32 can be thought of as an intermediate member of the M68000 Family. Ob- ject code from an MC68000 or MC68010 may be executed on the CPU32, and many of the instruction and addressing mode extensions of the MC68020 are also support- 4.1.1 New Instructions...
Page 50: Unimplemented Instructions
When the TBL instruction is executed, the CPU32 looks up two table entries bounding the desired result and performs a linear interpolation between them. Byte, word, and long-word operand sizes are supported.
Page 51: Notation
Freescale Semiconductor, Inc. Besides the operation code, which specifies the function to be performed, an instruc- tion defines the location of every operand for the function. Instructions specify an op- erand location in one of three ways: • Register specification A register field of the instruction contains the number of the register.
Page 52 Freescale Semiconductor, Inc. Condition code register (lower byte of status register) X — extend bit N — negative bit Z — zero bit V — overflow bit C — carry bit Program counter Active stack pointer Status register Supervisor stack pointer...
Page 53: Instruction Summary
Freescale Semiconductor, Inc. 4.3 Instruction Summary The instructions form a set of tools to perform the following operations: Data movement Bit manipulation Integer arithmetic Binary-coded decimal arithmetic Logic Program control Shift and rotate System control The complete range of instruction capabilities combined with the addressing modes described previously provide flexibility for program development.
Page 54: Data Movement Instructions
Freescale Semiconductor, Inc. Table 4-1 Condition Code Computations (Continued) Operations Special Definition V = Dm • (Dm – 1 Dm – r) + Dm • (Dm-1 Dm – r) C = Dm – r + 1 ASL (r = 0) LSL, ROXL C = Dm –...
Page 55: Integer Arithmetic Operations
Freescale Semiconductor, Inc. Table 4-2 Data Movement Operations Instruction Syntax Operand Size Operation list, 〈ea〉 Listed registers → Destination MOVEM 16, 32 Source → Listed registers 〈ea〉, list 16, 32 → 32 Dn [31: 24] → (An + d); Dn [23 : 16] → (An + d + 2);...
Page 56: Logic Instructions
Freescale Semiconductor, Inc. Table 4-3 Integer Arithmetic Operations Instruction Syntax Operand Size Operation 〈ea〉, Rn CMP2 8, 16, 32 Lower bound Rn Upper bound, CCR shows result 〈ea〉, Dn 32/16 → 16 : 16 Destination / Source → Destination DIVS/DIVU (signed or unsigned) 〈ea〉, Dr : Dq...
Page 57: Shift And Rotate Instructions
Freescale Semiconductor, Inc. 4.3.5 Shift and Rotate Instructions The arithmetic shift instructions, ASR and ASL, and logical shift instructions, LSR and LSL, provide shift operations in both directions. The ROR, ROL, ROXR, and ROXL in- structions perform rotate (circular shift) operations, with and without the extend bit. All shift and rotate operations can be performed on either registers or memory.
Page 58: Binary-Coded Decimal (Bcd) Instructions
Freescale Semiconductor, Inc. ory. The bit number is specified as immediate data or in a data register. Register op- erands are 32 bits long, and memory operands are 8 bits long. Table 4-6 is a summary of bit manipulation instructions.
Page 59: System Control Instructions
Freescale Semiconductor, Inc. Table 4-8 Program Control Operations Instruction Syntax Operand Size Operation 〈ea〉 Destination → PC none 〈ea〉 SP – 4 → SP; PC → (SP); destination → PC none PC + 2 → PC none none Returns (SP) → PC; SP + 4 + d → SP #〈d〉...
Page 60: Condition Tests
Freescale Semiconductor, Inc. Table 4-9 System Control Operations (Continued) Instruction Syntax Size Operation RESET none none Assert RESET line (SP) → SR; SP + 2 → SP; (SP) → PC; none none SP + 4 → SP; restore stack according to format Data →...
Page 61: Instruction Details
4.4 Instruction Details The following paragraphs contain detailed information about each instruction in the CPU32 instruction set. The instruction descriptions are arranged alphabetically by in- struction mnemonic. Figure 4-2 shows the format of the instruction descriptions. 4.2.1 Notation applies, with the following additions.
Page 62: Instruction Description Format
Freescale Semiconductor, Inc. ABCD INSTRUCTION NAME Add Decim OPERATION DESCRIPTION Operation: Source + Destination + X Assembler ASSEMBLER SYNTAX FOR THIS INSTRUCTION ABCD Dy,Dx Syntax: ABCD - (Ay), - (Ax) Attributes: SIZE ATTRIBUTE Size = (Byte) Description: Adds the source operation...
Page 63 Freescale Semiconductor, Inc. ABCD ABCD Add Decimal with Extend + X → Destination Operation: Source + Destination Assembler ABCD Dy, Dx Syntax: ABCD – (Ay), – (Ax) Attributes: Size = (Byte) Description: Adds the source operand to the destination operand along with the extend bit, and stores the result in the destination location.
Page 64 Freescale Semiconductor, Inc. ABCD ABCD Add Decimal with Extend Instruction fields: Register Rx ﬁeld — Speciﬁes the destination register: If R/M = 0, speciﬁes a data register If R/M = 1, speciﬁes an address register for predecrement addressing mode R/M ﬁeld — Speciﬁes the operand addressing mode: 0 —...
Page 65 Freescale Semiconductor, Inc. Source + Destination → Destination Operation: ADD 〈 ea〉, Dn Assembler: ADD Dn, 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Adds the source operand to the destination operand using binary addition, and stores the result in the destination location. The mode of the instruction indicates which operand is the source and which is the destination as well as the operand size.
Page 66 Freescale Semiconductor, Inc. Effective Address Field — Determines addressing mode: If the location specified is a source operand, all addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W Reg. number: An (xxx).L...
Page 67 Freescale Semiconductor, Inc. ADDA ADDA Add Address Source + Destination → Destination Operation: Assembler ADDA 〈ea〉 An Syntax: Attributes: Size = (Word, Long) Description: Adds the source operand to the destination address register and stores the result in the address register. The entire destination address register is used regardless of the operation size.
Page 68 Freescale Semiconductor, Inc. ADDI ADDI Add Immediate Immediate Data + Destination → Destination Operation: Assembler ADDI #〈data〉, 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Adds the immediate data to the destination operand, and stores the result in the destination location. The size of the immediate data must match the oper- ation size.
Page 69 Freescale Semiconductor, Inc. ADDI ADDI Add Immediate Effective Address ﬁeld — Speciﬁes the destination operand. Only data alterable addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W — — (xxx).L (An) Reg.
Page 70 Freescale Semiconductor, Inc. ADDQ ADDQ Add Quick Immediate Data + Destination → Destination Operation: Assembler ADDQ #〈data〉, 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Adds an immediate value in the range (1–8) to the operand at the destination location. Word and long operations are allowed on the address registers.
Page 71 Freescale Semiconductor, Inc. ADDQ ADDQ Add Quick Instruction Fields: Data ﬁeld — Three bits of immediate data, (9–11), with 0 representing a value of 8). Size ﬁeld — Speciﬁes the size of the operation: 00 — Byte operation 01 — Word operation 10 —...
Page 72 Freescale Semiconductor, Inc. ADDX ADDX Add Extended Source + Destination + X → Destination Operation: Assembler ADDX Dy, Dx Syntax: ADDX – (Ay), – (Ax) Attributes: Size = (Byte, Word, Long) Description: Adds the source operand to the destination operand along with the extend bit and stores the result in the destination location.
Page 73 Freescale Semiconductor, Inc. ADDX ADDX Add Extended Instruction Fields: Register Rx ﬁeld — Speciﬁes the destination register: If R/M = 0, speciﬁes a data register. If R/M = 1, speciﬁes an address register for predecrement addressing mode. Size ﬁeld — Speciﬁes the size of the operation: 00 —...
Page 74 Freescale Semiconductor, Inc. Logical AND Source • Destination → Destination Operation: AND 〈ea〉,Dn Assembler AND Dn, 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Performs an AND operation of the source operand with the destina- tion operand and stores the result in the destination location. The contents of an address register may not be used as an operand.
Page 75 Freescale Semiconductor, Inc. Logical AND Effective Address ﬁeld — Determines addressing mode: If the location speciﬁed is a source operand, only data addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W —...
Page 76 Freescale Semiconductor, Inc. ANDI ANDI AND Immediate Immediate Data • Destination → Destination Operation: Assembler ANDI #〈data〉, 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Performs an AND operation of the immediate data with the destina- tion operand and stores the result in the destination location. The size of the immedi- ate data must match the operation size.
Page 77 Freescale Semiconductor, Inc. ANDI ANDI AND Immediate Effective Address ﬁeld — Speciﬁes the destination operand. Only data alterable addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W — — (xxx).L (An) Reg.
Page 78 Freescale Semiconductor, Inc. ANDI ANDI AND Immediate to Condition Code Register to CCR to CCR Source • CCR → CCR Operation: Assembler Syntax: ANDI #〈data〉, CCR Attributes: Size = (Byte) Description: Performs an AND operation of the immediate operand with the con- dition codes and stores the result in the low-order byte of the status register.
Page 79 Freescale Semiconductor, Inc. ANDI ANDI AND Immediate to the Status Register to SR to SR (Privileged Instruction) Operation: If supervisor state then Source • SR →SR else TRAP Assembler Syntax: ANDI #〈data〉, SR Attributes: Size = (Word) Description: Performs an AND operation of the immediate operand with the con- tents of the status register and stores the result in the status register.
Page 80 Freescale Semiconductor, Inc. ASL, ASR ASL, ASR Arithmetic Shift Destination Shifted by 〈count〉 → Destination Operation: Assembler ASd Dx,Dy Syntax: ASd #〈data〉, Dy ASd 〈ea〉 where d is direction, L or R Attributes: Size = (Byte, Word, Long) Description: Arithmetically shifts the bits of the operand in the direction (L or R) speciﬁed.
Page 81 Freescale Semiconductor, Inc. ASL, ASR ASL, ASR Arithmetic Shift Condition Codes: Set according to the last bit shifted out of the operand. Unaffected for a shift count of zero. Set if the most signiﬁcant bit of the result is set. Cleared otherwise.
Page 82 Freescale Semiconductor, Inc. ASL, ASR ASL, ASR Arithmetic Shift Instruction Format (Memory Shifts): EFFECTIVE ADDRESS MODE REGISTER Instruction Fields (Memory Shifts): dr ﬁeld — Speciﬁes the direction of the shift: 0 — Shift right 1 — Shift left Effective Address ﬁeld — Speciﬁes the operand to be shifted.
Page 83 Freescale Semiconductor, Inc. Branch Conditionally If (condition true) then PC+ d → PC Operation: Assembler Bcc 〈label〉Attributes: Syntax: Size = (Byte, Word, Long) Description: If the speciﬁed condition is true, program execution continues at location (PC) + displacement. The PC contains the address of the instruction word of the Bcc instruction plus two.
Page 84 Freescale Semiconductor, Inc. Branch Conditionally Instruction Fields: Condition ﬁeld — The binary code for one of the conditions listed in the table. 8-Bit Displacement ﬁeld — Twos complement integer specifying the number of bytes between the branch instruction and the next instruction to be executed if the condition is met.
Page 85 Freescale Semiconductor, Inc. BCHG BCHG Test a Bit and Change (〈number〉 of Destination) → Z; Operation: (〈number〉 of Destination) → 〈bit number〉 of Destination BCHG Dn, 〈ea〉Syntax: Assembler: BCHG #〈data〉, 〈ea〉Attributes: Size = (Byte, Long) Description: Tests a speciﬁed bit in the destination operand, sets the Z condition code appropriately, then inverts the speciﬁed bit.
Page 86 Freescale Semiconductor, Inc. BCHG BCHG Test a Bit and Change Instruction Fields (Bit Number Static): Bit Number ﬁeld — Speciﬁes the bit number. Effective Address ﬁeld — Speciﬁes the destination location. Only data alterable addressing modes are allowed as shown:...
Page 87 Freescale Semiconductor, Inc. BCLR BCLR Test a Bit and Clear (〈bit number〉 of Destination) → Z; Operation: 0 → 〈bit number〉 of Destination BCLR Dn, 〈ea〉 Assembler BCLR #〈data〉, 〈ea〉 Syntax: Attributes: Size = (Byte, Long) Description: Tests a speciﬁed bit in the destination operand, sets the Z condition code appropriately, then clears the bit.
Page 88 Freescale Semiconductor, Inc. BCLR BCLR Test a Bit and Clear Instruction Fields (Bit Number Static): Bit Number ﬁeld — Speciﬁes the bit number. Effective Address ﬁeld — Speciﬁes the destination location. Only data alterable addressing modes are allowed as shown:...
Page 89 Freescale Semiconductor, Inc. BGND BGND Enter Background Mode Operation: If (background mode enabled) then enter Background Mode else Format/Vector offset → – (SSP) PC → – (SSP) SR → – (SSP) (Vector) → PC Assembler Syntax: BGND Attributes: Size = (Unsized)
Page 90 Freescale Semiconductor, Inc. BKPT BKPT Breakpoint Operation: Run breakpoint acknowledge cycle; If acknowledged then execute returned operation word else TRAP as illegal instruction Assembler Syntax: BKPT #〈data〉 Attributes: Unsized Description: Executes a breakpoint acknowledge bus cycle. Bits [2:4] of the address bus are set to the value of the immediate data (0 to 7) and bits 0 and 1 of the address bus are set to 0.
Page 91 Freescale Semiconductor, Inc. Branch Always PC + d → PC Operation: Assembler BRA 〈label〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Program execution continues at location (PC) + displacement. The PC contains the address of the instruction word of the BRA instruction plus two. The displacement is a twos complement integer that represents the relative distance in bytes from the current PC to the destination PC.
Page 92 Freescale Semiconductor, Inc. BSET BSET Test a Bit and Set (〈bit number〉of Destination) → Z; Operation: 1 → 〈bit number〉 of Destination BSET Dn, 〈ea〉Syntax: Assembler: BSET #〈data〉, 〈ea〉 Attributes: Size = (Byte, Long) Description: Tests a bit in the destination operand, sets the Z condition code appropriately, then sets the speciﬁed bit in the destination operand.
Page 93 Freescale Semiconductor, Inc. BSET BSET Test a Bit and Set Instruction Fields (Bit Number Static): Bit Number ﬁeld — Speciﬁes the bit number. Effective Address ﬁeld — Speciﬁes the destination location. Only data alterable addressing modes are allowed as shown:...
Page 94 Freescale Semiconductor, Inc. Branch to Subroutine SP – 4 → SP; PC → (SP); PC + d → PC Operation: Assembler BSR 〈label〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Pushes the long word address of the instruction immediately follow- ing the BSR instruction onto the system stack.
Page 95 Freescale Semiconductor, Inc. BTST BTST Test a Bit – (〈bit number〉 of Destination) → Z Operation: BTST Dn, 〈ea〉 Assembler BTST #〈data〉, 〈ea〉 Syntax: Attributes: Size = (Byte, Long) Description: Tests a bit in the destination operand and sets the Z condition code appropriately.
Page 96 Freescale Semiconductor, Inc. BTST BTST Test a Bit Instruction Fields (Bit Number Static): Bit Number ﬁeld — Speciﬁes the bit number. Effective Address ﬁeld — Speciﬁes the destination location. Only data addressing modes areallowed as shown: Addressing Mode Mode Register...
Page 97 Freescale Semiconductor, Inc. Check Register Against Bounds Operation: If Dn < 0 or Dn > Source then TRAP Assembler CHK 〈ea〉, Dn Syntax: Attributes: Size = (Word, Long) Description: Compares the value in the data register speciﬁed by the instruction to zero and to the upper bound (effective address operand).
Page 98 Freescale Semiconductor, Inc. Check Register Against Bounds Effective Address ﬁeld — Speciﬁes the destination location. Only data addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W — — (xxx).L (An) Reg. number: An #〈data〉...
Page 99 Freescale Semiconductor, Inc. CHK2 CHK2 Check Register Against Bounds Operation: If Rn < lower bound or Rn > upper bound then TRAP Assembler CHK2 〈ea〉, Rn Syntax: Attributes: Size = (Byte, Word, Long) Description: Compares the value in Rn to each bound. The effective address contains the bounds pair: the lower bound followed by the upper bound.
Page 100 Freescale Semiconductor, Inc. CHK2 CHK2 Check Register Against Bounds Instruction Format: EFFECTIVE ADDRESS SIZE MODE REGISTER REGISTER Instruction Fields: Size ﬁeld — Speciﬁes the size of the operation. 00 — Byte operation 01 — Word operation 10 — Long operation Effective Address ﬁeld —...
Page 101 Freescale Semiconductor, Inc. Clear an Operand 0 → Destination Operation: Assembler CLR 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Clears the destination operand to zero. Condition Codes: — Not affected. Always cleared. Always set. Always cleared. Always cleared.
Page 102 Freescale Semiconductor, Inc. Clear an Operand Effective Address ﬁeld — Speciﬁes the destination location. Only data alterable addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. Number: Dn (xxx).W — — (xxx).L (An) Reg. number: An #〈data〉...
Page 103 Freescale Semiconductor, Inc. Compare Destination – Source → cc Operation: Assembler CMP 〈ea〉, Dn Syntax: Attributes: Size = (Byte, Word, Long) Description: Subtracts the source operand from the destination data register and sets condition codes according to the result. The data register is not changed.
Page 104 Freescale Semiconductor, Inc. Compare Effective Address ﬁeld — Speciﬁes the source operand. All addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W Reg. number: An (xxx).L (An) Reg. number: An #〈data〉...
Page 105 Freescale Semiconductor, Inc. CMPA CMPA Compare Address Destination – Source → cc Operation: Assembler CMPA 〈ea〉, An Syntax: Attributes: Size = (Word, Long) Description: Subtracts the source operand from the destination address register and sets the condition codes according to the result. The address register is not changed.
Page 106 Freescale Semiconductor, Inc. CMPA CMPA Compare Address Effective Address ﬁeld — Speciﬁes source operand. All addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W Reg. number: An (xxx).L (An) Reg. number: An #〈data〉...
Page 107 Freescale Semiconductor, Inc. CMPI CMPI Compare Immediate Destination – Immediate Data → cc Operation: Assembler CMPI #〈data〉, 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Subtracts the immediate data from the destination operand and sets condition codes according to the result. The destination location is not changed. The size of the immediate data must match the operation size.
Page 108 Freescale Semiconductor, Inc. CMPI CMPI Compare Immediate Effective Address ﬁeld — Speciﬁes the destination operand. Only data addressing modes, except immediate, are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W — — (xxx).L (An) Reg.
Page 109 Freescale Semiconductor, Inc. CMPM CMPM Compare Memory Destination – Source → cc Operation: Assembler Syntax: CMPM (Ay)+, (Ax)+ Attributes: Size = (Byte, Word, Long) Description: Subtracts the source operand from the destination operand and sets the condition codes according to the results. The destination location is not changed.
Page 110 Freescale Semiconductor, Inc. CMP2 CMP2 Compare Register Against Bounds Operation: Compare Rn < lower-bound or Rn > upper-bound and Set Condition Codes Assembler CMP2 〈ea〉, Rn Syntax: Attributes: Size = (Byte, Word, Long) Description: Compares the value in Rn to each bound. The effective address contains the bounds pair: the lower bound followed by the upper bound.
Page 111 Freescale Semiconductor, Inc. CMP2 CMP2 Compare Register Against Bounds Instruction Fields: Size ﬁeld — Speciﬁes the size of the operation. 00 — Byte operation 01 — Word operation 10 — Long operation Effective Address ﬁeld — Speciﬁes the location of the bounds pair. Only control...
Page 112 Freescale Semiconductor, Inc. DBcc DBcc Test Condition, Decrement, and Branch If condition false then Dn – 1 → Dn;If Dn ≠ –1 then PC + d → PC Operation: Assembler DBcc Dn, 〈label〉 Syntax: Attributes: Size = (Word) Description: Controls a loop of instructions. The parameters are a condition code, a data register (counter), and a displacement value.
Page 113 Freescale Semiconductor, Inc. DBcc DBcc Test Condition, Decrement, and Branch Instruction Format: CONDITION REGISTER DISPLACEMENT Instruction Fields: Condition ﬁeld — The binary code for one of the conditions listed in the table. Register ﬁeld — Speciﬁes the data register used as the counter.
Page 114 Freescale Semiconductor, Inc. DIVS DIVS Signed Divide DIVSL DIVSL Destination / Source → Destination Operation: Assembler DIVS.W 〈ea〉, Dn32/16 → 16r:16q Syntax: DIVS.L 〈ea〉, Dq32/32 → 32q DIVS.L 〈ea〉, Dr:Dq64/32 → 32r:32q DIVSL.L 〈ea〉, Dr:Dq32/32 → 32r:32q Attributes: Size = (Word, Long)
Page 115 Freescale Semiconductor, Inc. DIVS DIVS Signed Divide DIVSL DIVSL Condition Codes: — Not affected. Set if quotient is negative. Cleared otherwise. Undeﬁned if overﬂow or divide by zero occurs. Set if quotient is zero. Cleared otherwise. Undeﬁned if overﬂow or divide by zero occurs.
Page 116 Freescale Semiconductor, Inc. DIVS DIVS Signed Divide DIVSL DIVSL Instruction Format (long form): EFFECTIVE ADDRESS MODE REGISTER REGISTER Dq SIZE REGISTER Dr Instruction Fields: Effective Address ﬁeld — Speciﬁes the source operand. Only data addressing modes are allowed as shown:...
Page 117 Freescale Semiconductor, Inc. DIVU DIVU Unsigned Divide DIVUL DIVUL Destination/Source → Destination Operation: Assembler DIVS.W 〈ea〉, Dn32/16 → 16r:16q Syntax: DIVS.L 〈ea〉, Dq32/32 → 32q DIVS.L 〈ea〉, Dr:Dq64/32 → 32r:32q DIVSL.L 〈ea〉, Dr:Dq32/32 →32r:32q Attributes: Size = (Word, Long) Description: Divides the unsigned destination operand by the unsigned source operand and stores the unsigned result in the destination.
Page 118 Freescale Semiconductor, Inc. DIVU DIVU Unsigned Divide DIVUL DIVUL Instruction Format (word form): EFFECTIVE ADDRESS REGISTER MODE REGISTER Instruction Fields: Register ﬁeld — Speciﬁes any of the eight data registers. This ﬁeld always speciﬁes the destination operand. Effective Address ﬁeld — Speciﬁes the source operand. Only data addressing modes...
Page 119 Freescale Semiconductor, Inc. DIVU DIVU Unsigned Divide DIVUL DIVUL Instruction Format (long form): EFFECTIVE ADDRESS MODE REGISTER REGISTER Dq SIZE REGISTER Dr Instruction Fields: Effective Address ﬁeld — Speciﬁes the source operand. Only data addressing modes are allowed as shown:...
Page 120 Freescale Semiconductor, Inc. Exclusive OR Source ⊕ Destination → Destination Operation: Assembler EOR Dn, 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Performs an exclusive OR operation on the destination operand using the source operand and stores the result in the destination location. The source operand must be a data register.
Page 121 Freescale Semiconductor, Inc. Exclusive OR Effective Address ﬁeld — Speciﬁes the destination operand. Only data alterable addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W — — (xxx).L (An) Reg. number: An #〈data〉...
Page 122 Freescale Semiconductor, Inc. EORI EORI Exclusive OR Immediate Immediate Data ⊕ Destination → Destination Operation: Assembler EORI #〈data〉, 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Performs an exclusive OR operation on the destination operand using the immediate data and the destination operand and stores the result in the destination location.
Page 123 Freescale Semiconductor, Inc. EORI EORI Exclusive OR Immediate Effective Address ﬁeld — Speciﬁes the destination operand. Only data alterable addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W — — (xxx).L (An) Reg.
Page 124 Freescale Semiconductor, Inc. EORI EORI Exclusive OR Immediate to CCR to CCR to Condition Code Register Source ⊕ CCR → CCR Operation: Assembler Syntax: EORI #〈data〉, CCR Attributes: Size = (Byte) Description: Performs an exclusive OR operation on the condition code register using the immediate operand, and stores the result in the condition code register (low-order byte of the status register).
Page 125 Freescale Semiconductor, Inc. EORI EORI Exclusive OR Immediate to Status Register to SR to SR (Privileged Instruction) Operation: If supervisor state then Source ⊕ SR → SR else TRAP Assembler Syntax: EORI #〈data〉, SR Attributes: Size = (Word) Description: Performs an exclusive OR operation on the contents of the status register using the immediate operand, and stores the result in the status register.
Page 126 Freescale Semiconductor, Inc. Exchange Registers Rx ↔ Ry Operation: Assembler: EXG Dx, Dy Syntax: EXG Ax, Ay EXG Dx, Ay EXG Ay, Dx Attributes: Size = (Long) Description: Exchanges the contents of two 32-bit registers. The instruction per- forms three types of exchanges: 1.
Page 127 Freescale Semiconductor, Inc. Sign Extend EXTB EXTB Destination Sign-extended → Destination Operation: Assembler Syntax: EXT.W Dnextend byte to word EXT.L Dnextend word to long word EXTB.L Dnextend byte to long word Attributes: Size = (Word, Long) Description: Extends a byte in a data register to a word or a long word, or a word in a data register to a long word, by replicating the sign bit to the left.
Page 128 Freescale Semiconductor, Inc. ILLEGAL ILLEGAL Take Illegal Instruction Trap SSP – 2 → SSP; Vector Offset → (SSP); Operation: SSP – 4 → SSP; PC → (SSP); SSP – 2 → SSP; SR → (SSP); Illegal Instruction Vector Address → PC...
Page 129 Freescale Semiconductor, Inc. Jump Destination Address → PC Operation: Assembler JMP 〈ea〉 Syntax: Attributes: Unsized Description: Program execution continues at the effective address speciﬁed by the instruction. The addressing mode for the effective address must be a control addressing mode.
Page 130 Freescale Semiconductor, Inc. Jump to Subroutine SP – 4 → Sp; PC → (SP) Operation: Destination Address → PC Assembler JSR 〈ea〉 Syntax: Attributes: Unsized Description: Pushes the long word address of the instruction immediately follow- ing the JSR instruction onto the system stack. Program execution then continues at the address speciﬁed by the instruction.
Page 131 Freescale Semiconductor, Inc. Load Effective Address 〈ea〉 → An Operation: Assembler LEA 〈ea〉, An Syntax: Attributes: Size = (Long) Description: Loads the effective address into the speciﬁed address register. All 32 bits of the address register are affected by this instruction.
Page 132 Freescale Semiconductor, Inc. LINK LINK Link and Allocate Sp – 4 → Sp; An → (SP); Operation: SP → An; SP + d → SP Assembler Syntax: LINK An, #〈displacement〉 Attributes: Size = (Word, Long) Description: Pushes the contents of the speciﬁed address register onto the stack, then loads the updated stack pointer into the address register.
Page 133 Freescale Semiconductor, Inc. LPSTOP LPSTOP Low Power Stop Operation: If supervisor state then Immediate Data → SR Interrupt Mask → External Bus Interface (EBI) STOP else TRAP Assembler Syntax: LPSTOP #〈data〉 Attributes: Size = (Word) Privileged Description: The immediate operand is moved into the entire status register, the program counter is advanced to point to the next instruction, and the processor stops fetching and executing instructions.
Page 134 Freescale Semiconductor, Inc. LSL, LSR LSL, LSR Logical Shift Destination Shifted by 〈count〉 → Destination Operation: Assembler LSd Dx, Dy Syntax: LSd #〈data〉, Dy LSd 〈ea〉 where d is direction, L or R Attributes: Size = (Byte, Word, Long) Description: Shifts the bits of the operand in the direction speciﬁed (L or R).
Page 135 Freescale Semiconductor, Inc. LSL, LSR LSL, LSR Logical Shift Condition Codes: Set according to the last bit shifted out of the operand. Unaffected for a shift count of zero. Set if the result is negative. Cleared otherwise. Set if the result is zero. Cleared otherwise.
Page 136 Freescale Semiconductor, Inc. LSL, LSR LSL, LSR Logical Shift Instruction Format (Memory Shifts): EFFECTIVE ADDRESS MODE REGISTER Instruction Fields (Memory Shifts): dr ﬁeld — Speciﬁes the direction of the shift: 0 — Shift right 1 — Shift left Effective Address ﬁeld — Speciﬁes the operand to be shifted.
Page 137 Freescale Semiconductor, Inc. MOVE MOVE Move Data from Source to Destination Source → Destination Operation: Assembler MOVE 〈ea〉, 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Moves the data at the source to the destination location, and sets the condition codes according to the data.
Page 138 Freescale Semiconductor, Inc. MOVE MOVE Move Data from Source to Destination Destination Effective Address ﬁeld — Speciﬁes the destination location. Only data alterable addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W...
Page 139 Freescale Semiconductor, Inc. MOVEA MOVEA Move Address Source → Destination Operation: Assembler MOVEA 〈ea〉, An Syntax: Attributes: Size = (Word, Long) Description: Moves the contents of the source to the destination address register. The size of the operation is speciﬁed as word or long. Word size source operands are sign-extended to 32-bit quantities.
Page 140 Freescale Semiconductor, Inc. MOVE MOVE Move from the from CCR from CCR Condition Code Register CCR → Destination Operation: Assembler MOVE CCR, 〈ea〉 Syntax: Attributes: Size = (Word) Description: Moves the condition code bits (zero extended to word size) to the destination location.
Page 141 Freescale Semiconductor, Inc. MOVE MOVE Move to Condition Code Register to CCR to CCR Source → CCR Operation: Assembler MOVE 〈ea〉, CCR Syntax: Attributes: Size = (Word) Description: Moves the low-order byte of the source operand to the condition code register. The upper byte of the source operand is ignored; the upper byte of the status register is not altered.
Page 142 Freescale Semiconductor, Inc. MOVE MOVE Move to Condition Code Register to CCR to CCR Instruction Fields: Effective Address ﬁeld — Speciﬁes the destination location. Only data addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg.
Page 143 Freescale Semiconductor, Inc. MOVE MOVE Move from the Status Register from SR from SR (Privileged Instruction) Operation: If supervisor state then SR → Destination else TRAP Assembler MOVE SR, 〈ea〉 Syntax: Attributes: Size = (Word) Description: Moves the data in the status register to the destination location. The destination must be of word length.
Page 144 Freescale Semiconductor, Inc. MOVE MOVE Move to the Status Register to SR to SR (Privileged Instruction) Operation: If supervisor state then Source →SR else TRAP Assembler MOVE 〈ea〉, SR Syntax: Attributes: Size = (Word) Description: Moves the data in the source operand to the status register. The source operand is a word and all implemented bits of the status register are affected.
Page 145 Freescale Semiconductor, Inc. MOVE MOVE Move User Stack Pointer (Privileged Instruction) Operation: If supervisor state then USP → An or An → USP else TRAP Assembler MOVE USP, An Syntax: MOVE An, USP Attributes: Size = (Long) Description: Moves the contents of the user stack pointer to or from the speciﬁed address register.
Page 146 Freescale Semiconductor, Inc. MOVEC MOVEC Move Control Register (Privileged Instruction) Operation: If supervisor state then Rc → Rn or Rn → Rc else TRAP Assembler MOVEC Rc, Rn Syntax: MOVEC Rn, Rc Attributes: Size = (Long) Description: Moves the contents of the speciﬁed control register (Rc) to the spec- iﬁed general register (Rn), or copies the contents of the speciﬁed general register to...
Page 147 The order of loading is the same as that of control mode addressing. When the instruction has completed, the incremented address register contains the address of the last operand loaded plus the operand length. In the CPU32, if the addressing register is also loaded from memory, the value loaded is the value fetched plus the operand length.
Page 148 Freescale Semiconductor, Inc. MOVEM MOVEM Move Multiple Registers Condition Codes: Not affected. Instruction Format: EFFECTIVE ADDRESS SIZE MODE REGISTER REGISTER LIST MASK Instruction Field: dr ﬁeld — Speciﬁes the direction of the transfer: 0 — Register to memory 1 — Memory to register Size ﬁeld —...
Page 149 Freescale Semiconductor, Inc. MOVEM MOVEM Move Multiple Registers For memory-to-register transfers, only control addressing modes or the postincre- ment addressing mode are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register — — (xxx).W — — (xxx).L (An) Reg.
Page 150 Freescale Semiconductor, Inc. MOVEP MOVEP Move Peripheral Data Source → Destination Operation: Assembler MOVEP Dx, (d, Ay) Syntax: MOVEP (d, Ay), Dx Attributes: Size = (Word, Long) Description: Moves data between a data register and alternate bytes within the address space (typically assigned to a peripheral), starting at the location speciﬁed and incrementing by two.
Page 151 Freescale Semiconductor, Inc. MOVEP MOVEP Move Peripheral Data Example: Word transfer to/from an odd address Byte Organization in Register HIGH ORDER LOW ORDER Byte Organization in Memory (Low Address at Top) HIGH ORDER LOW ORDER Condition Codes: Not affected. Instruction Format:...
Page 152 Freescale Semiconductor, Inc. MOVEQ MOVEQ Move Quick Immediate Data → Destination Operation: Assembler Syntax: MOVEQ #〈data〉, Dn Attributes: Size = (Long) Description: Moves a byte of immediate data to a 32-bit data register. The data in an 8-bit ﬁeld within the operation word is sign-extended to a long operand in the data register as it is transferred.
Page 153 Freescale Semiconductor, Inc. MOVES MOVES Move Address Space (Privileged Instruction) Operation: If supervisor state then Rn → Destination [DFC] or Source [SFC] → Rn else TRAP MOVES Rn, 〈ea〉Syntax: Assembler: MOVES 〈ea〉, Rn Attributes: Size = (Byte, Word, Long) Description: Moves the byte, word, or long operand from the speciﬁed general...
Page 154 For either of the two following examples, which use the same ad- dress register as both source and destination, the value stored is un- defined. The current implementations of the MC68010, CPU32, and MC68020 store the incremented or decremented value of An.
Page 155 Freescale Semiconductor, Inc. MULS MULS Signed Multiply Source ∗ Destination → Destination Operation: Assembler MULS.W 〈ea〉, Dn16x16 → 32 Syntax: MULS.L 〈ea〉, Dl 32x32 → 32 MULS.L 〈ea〉, Dh:Dl32 x 32 → 64 Attributes: Size = (Word, Long) Description:: Multiplies two signed operands yielding a signed result.
Page 156 Freescale Semiconductor, Inc. MULS MULS Signed Multiply Instruction Format (word form): EFFECTIVE ADDRESS REGISTER MODE REGISTER Instruction Fields: Register ﬁeld — Speciﬁes a data register as the destination. Effective Address ﬁeld — Speciﬁes the source operand. Only data addressing modes...
Page 157 Freescale Semiconductor, Inc. MULS MULS Signed Multiply Instruction Format (long form): EFFECTIVE ADDRESS MODE REGISTER REGISTER Dl SIZE REGISTER Dh Instruction Fields: Effective Address ﬁeld — Speciﬁes the source operand. Only data addressing modes are allowed as shown: Addressing Mode...
Page 158 Freescale Semiconductor, Inc. MULU MULU Unsigned Multiply Source ∗ Destination → Destination Operation: Assembler MULU.W 〈ea〉, Dn16x16 → 32 Syntax: MULU.L 〈ea〉, Dl32x32 → 32 MULU.L 〈ea〉, Dh:Dl32x32 →64 Attributes: Size = (Word, Long) Description: Multiplies two unsigned operands yielding an unsigned result.
Page 159 Freescale Semiconductor, Inc. MULU MULU Unsigned Multiply Instruction Format (word form): EFFECTIVE ADDRESS REGISTER MODE REGISTER Instruction Fields: Register ﬁeld —Speciﬁes a data register as the destination. Effective Address ﬁeld —Speciﬁes the source operand. Only data addressing modes are allowed as shown:...
Page 160 Freescale Semiconductor, Inc. MULU MULU Unsigned Multiply Instruction Format (long form): EFFECTIVE ADDRESS MODE REGISTER REGISTER Dl SIZE REGISTER Dh Instruction Fields: Effective Address ﬁeld — Speciﬁes the source operand. Only data addressing modes are allowed as shown: Addressing Mode...
Page 161 Freescale Semiconductor, Inc. NBCD NBCD Negate Decimal with Extend ) – X → Destination Operation: 0 – (Destination Assembler NBCD 〈ea〉 Syntax: Attributes: Size = (Byte) Description: Subtracts the destination operand and the extend bit from zero. The operation is performed using binary coded decimal arithmetic. The packed BCD result is saved in the destination location.
Page 162 Freescale Semiconductor, Inc. NBCD NBCD Negate Decimal with Extend Instruction Fields: Effective Address ﬁeld — Speciﬁes the destination operand. Only data alterable addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W —...
Page 163 Freescale Semiconductor, Inc. Negate 0 – (Destination) → Destination Operation: Assembler NEG 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Subtracts the destination operand from zero and stores the result in the destination location. Condition Codes: Set the same as the carry bit.
Page 164 Freescale Semiconductor, Inc. Negate Effective Address ﬁeld — Speciﬁes the destination operand. Only data alterable addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W — — (xxx).L (An) Reg. number: An #〈data〉...
Page 165 Freescale Semiconductor, Inc. NEGX NEGX Negate with Extend 0 – (Destination) – X → Destination Operation: Assembler NEGX 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Subtracts the destination operand and the extend bit from zero. Stores the result in the destination location.
Page 166 Freescale Semiconductor, Inc. NEGX NEGX Negate with Extend Effective Address ﬁeld — Speciﬁes the destination operand. Only data alterable addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W — — (xxx).L (An) Reg.
Page 167 Freescale Semiconductor, Inc. No Operation Operation: None Assembler Syntax: Attributes: Unsized Description: Performs no operation. The program counter is incremented, but processor state is otherwise unaffected. Execution continues with the instruction fol- lowing the NOP instruction. The NOP instruction does not begin execution until all pending bus cycles are completed.
Page 168 Freescale Semiconductor, Inc. Logical Complement Destination → Destination Operation: Assembler NOT 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Calculates the ones complement of the destination operand and stores the result in the destination location. Condition Codes: — Not affected.
Page 169 Freescale Semiconductor, Inc. Logical Complement Effective Address ﬁeld — Speciﬁes the destination operand. Only data alterable addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W — — (xxx).L (An) Reg. number: An #〈data〉...
Page 170 Freescale Semiconductor, Inc. Inclusive Logical OR Source + Destination → Destination Operation: OR 〈ea〉, Dn Assembler OR Dn, 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Performs an inclusive OR operation on the source operand and the destination operand and stores the result in the destination location. The contents of an address register may not be used as an operand.
Page 171 Freescale Semiconductor, Inc. Inclusive Logical OR Effective Address ﬁeld — If the location speciﬁed is a source operand, only data addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W — —...
Page 172 Freescale Semiconductor, Inc. Inclusive OR Immediate Immediate Data; Destination → Destination Operation: Assembler ORI → #〈data〉, 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Performs an inclusive OR operation on the immediate data and the destination operand and stores the result in the destination location. The size of the immediate data must match the operation size.
Page 173 Freescale Semiconductor, Inc. Inclusive OR Immediate Effective Address ﬁeld — Speciﬁes the destination operand. Only data alterable addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W — — (xxx).L (An) Reg. number: An #〈data〉...
Page 174 Freescale Semiconductor, Inc. Inclusive OR Immediate to CCR to CCR to Condition Code Register Source; CCR → CCR Operation: Assembler Syntax: ORI #〈data〉, CCR Attributes: Size = (Byte) Description: Performs an inclusive OR operation on the immediate operand and the condition codes and stores the result in the condition code register (low-order byte of the status register).
Page 175 Freescale Semiconductor, Inc. Inclusive OR Immediate to Status Register to SR to SR (Privileged Instruction) Operation: If supervisor state then Source; SR → SR else TRAP Assembler Syntax: ORI #〈data〉, SR Attributes: Size = (Word) Description: Performs an inclusive OR operation of the immediate operand and the contents of the status register and stores the result in the status register.
Page 176 Freescale Semiconductor, Inc. Push Effective Address Sp – 4 → SP; 〈ea〉 → (SP) Operation: Assembler PEA 〈ea〉 Syntax: Attributes: Size = (Long) Description: Computes the effective address and pushes it onto the stack. The effective address must be a long word address.
Page 177 Freescale Semiconductor, Inc. RESET RESET Reset External Devices (Privileged Instruction) Operation: If supervisor state then Assert RESET Line else TRAP Assembler Syntax: RESET Attributes: Unsized Description: Asserts the RESET signal for 512 clock periods, resetting all exter- nal devices. The processor state, other than the program counter, is unaffected and execution continues with the next instruction.
Page 178 Freescale Semiconductor, Inc. ROL, ROR ROL, ROR Rotate (Without Extend) Destination Rotated by 〈count〉 → Destination Operation: Assembler ROd Dx, Dy ROd # 〈data〉, Dy Syntax: ROd 〈ea〉 where d is direction, L or R Attributes: Size = (Byte, Word, Long) Description: Rotates the bits of the operand in the direction speciﬁed (L or R).
Page 179 Freescale Semiconductor, Inc. ROL, ROR ROL, ROR Rotate (Without Extend) Condition Codes: — Not affected. Set if the most signiﬁcant bit of the result is set. Cleared otherwise. Set if the result is zero. Cleared otherwise. Always cleared. Set according to the last bit rotated out of the operand. Cleared when the rotate count is zero.
Page 180 Freescale Semiconductor, Inc. ROL, ROR ROL, ROR Rotate (Without Extend) Instruction Format (Memory Rotate): EFFECTIVE ADDRESS MODE REGISTER Instruction Fields (Memory Rotate): dr ﬁeld — Speciﬁes the direction of the rotate: 0 — Rotate right 1 — Rotate left Effective Address ﬁeld — Speciﬁes the operand to be rotated. Only memory alterable...
Page 181 Freescale Semiconductor, Inc. ROXL, ROXR ROXL, ROXR Rotate with Extend Destination Rotated with X by 〈count〉 → Destination Operation: Assembler ROXd Dx, Dy Syntax: ROXd #〈data〉, Dy ROXd 〈ea〉 where d is direction, L or R Attributes: Size = (Byte, Word, Long) Description: Rotates the bits of the operand in the direction specified (L or R).
Page 182 Freescale Semiconductor, Inc. ROXL, ROXR ROXL, ROXR Rotate with Extend Condition Codes: Set to the value of the last bit rotated out of the operand. Unaffected when count is zero. Set if the most signiﬁcant bit of the result is set. Cleared otherwise.
Page 183 Freescale Semiconductor, Inc. ROXL, ROXR ROXL, ROXR Rotate with Extend Instruction Format (Memory Rotate): EFFECTIVE ADDRESS MODE REGISTER Instruction Fields (Memory Rotate): dr ﬁeld — Speciﬁes the direction of the rotate: 0 — Rotate right 1 — Rotate left Effective Address ﬁeld — Speciﬁes the operand to be rotated. Only memory alterable...
Page 184 Freescale Semiconductor, Inc. Return and Deallocate (SP) → PC; SP + 4 + d → SP Operation: Assembler Syntax: RTD #〈displacement〉 Attributes: Unsized Description: Pulls the program counter value from the stack and adds the sign- extended 16-bit displacement value to the stack pointer. The previous program counter value is lost.
Page 185 Freescale Semiconductor, Inc. Return from Exception (Privileged Instruction) Operation: If supervisor state then (SP) → SR; SP + 2 → SP; (SP) → PC; SP + 4 → SP; restore state and de-allocate stack according to (SP) else TRAP Assembler...
Page 186 Freescale Semiconductor, Inc. Return and Restore Condition Codes (SP) → CCR; SP + 2 → SP; Operation: (SP) → PC; SP + 4 → SP Assembler Syntax: Attributes: Unsized Description: Pulls the condition code and program counter values from the stack.
Page 187 Freescale Semiconductor, Inc. Return from Subroutine (SP) → PC; SP + 4 → SP Operation: Assembler Syntax: Attributes: Unsized Description: Pulls the program counter value from the stack. The previous value is lost. Condition Codes: Not affected. Instruction Format: CPU32...
Page 188 Freescale Semiconductor, Inc. SBCD SBCD Subtract Decimal with Extend – X → Destination Operation: Destination – Source Assembler SBCD Dx, Dy Syntax: SBCD –(Ax), –(Ay) Attributes: Size = (Byte) Description: Subtracts the source operand and the extend bit from the destina- tion operand and stores the result in the destination location.
Page 189 Freescale Semiconductor, Inc. Set According to Condition Code Operation: If Condition True then set Destination else clear Destination Assembler Scc 〈ea〉 Syntax: Attributes: Size = (Byte) Description: Tests the speciﬁed condition code. If the condition is true, sets all bits in the byte speciﬁed to 1 (TRUE). Otherwise, clears all bits to 0 (FALSE). Condi- tion code cc speciﬁes one of the following conditions:...
Page 190 Freescale Semiconductor, Inc. Set According to Condition Code Instruction Fields: Condition ﬁeld — The binary code for one of the conditions listed in the table. Effective Address ﬁeld — Speciﬁes the location in which the true/false byte is to be stored.
Page 191 Freescale Semiconductor, Inc. STOP STOP Load Status Register and Stop (Privileged Instruction) Operation: If supervisor state then Immediate Data → SR; STOP else TRAP Assembler Syntax: STOP #〈data〉 Attributes: Unsized Description: Moves the immediate operand into the status register (both user and supervisor portions), advances the program counter to point to the next instruction, and stops the fetching and executing of instructions.
Page 192 Freescale Semiconductor, Inc. Subtract Destination – Source → Destination Operation: SUB 〈ea〉, Dn Assembler SUB Dn, 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Subtracts the source operand from the destination operand and stores the result in the destination. The mode of the instruction indicates which oper- and is the source, which is the destination, and which is the operand size.
Page 193 Freescale Semiconductor, Inc. Subtract Effective Address ﬁeld — Determines the addressing mode. If the location speciﬁed is a source operand, all addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W Reg. number: An (xxx).L...
Page 194 Freescale Semiconductor, Inc. SUBA SUBA Subtract Address Destination – Source → Destination Operation: Assembler SUBA 〈ea〉, An Syntax: Attributes: Size = (Word, Long) Description: Subtracts the source operand from the destination address register and stores the result in the address register. Word size source operands are sign extended to 32-bit quantities prior to the subtraction.
Page 195 Freescale Semiconductor, Inc. SUBI SUBI Subtract Immediate Destination – Immediate Data → Destination Operation: Assembler SUBI #〈data〉, 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Subtracts the immediate data from the destination operand and stores the result in the destination location. The size of the immediate data must match the operation size.
Page 196 Freescale Semiconductor, Inc. SUBI SUBI Subtract Immediate Instruction Fields: Size ﬁeld — Speciﬁes the size of the operation. 00 — Byte operation 01 — Word operation 10 — Long operation Effective Address ﬁeld — Speciﬁes the destination operand. Only data alterable...
Page 197 Freescale Semiconductor, Inc. SUBQ SUBQ Subtract Quick Destination – Immediate Data → Destination Operation: Assembler SUBQ #〈data〉, 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Subtracts the immediate data (1–8) from the destination operand. Only word and long operations are allowed with address registers, and the condition codes are not affected.
Page 198 Freescale Semiconductor, Inc. SUBQ SUBQ Subtract Quick Instruction Fields: Data ﬁeld — Three bits of immediate data; 1–7 represent immediate values of 1–7, and 0 represents 8. Size ﬁeld — Speciﬁes the size of the operation: 00 — Byte operation 01 —...
Page 199 Freescale Semiconductor, Inc. SUBX SUBX Subtract with Extend Destination – Source – X → Destination Operation: Assembler SUBX Dx, Dy Syntax: SUBX –(Ax), –(Ay) Attributes: Size = (Byte, Word, Long) Description: Subtracts the source operand and the extend bit from the destination operand and stores the result in the destination location.
Page 200 Freescale Semiconductor, Inc. SUBX SUBX Subtract with Extend Instruction Format: REGISTER Rx SIZE REGISTER Ry Instruction Fields: Register Dy/Ay ﬁeld — Speciﬁes the destination register: If R/M = 0, speciﬁes a data register. If R/M = 1, speciﬁes an address register for the predecrement addressing mode.
Page 201 Freescale Semiconductor, Inc. SWAP SWAP Swap Register Halves Register [31:16] ↔ Register [15:0] Operation: Assembler Syntax: SWAP Dn Attributes: Size = (Word) Description: Exchange the 16-bit words (halves) of a data register. Condition Codes: — Not affected. Set if the most signiﬁcant bit of the 32-bit result is set. Cleared otherwise.
Page 202 Freescale Semiconductor, Inc. TBLS TBLS Table Lookup and Interpolate (Signed) TBLSN TBLSN Operation: Rounded: ) ∗ Dx [7:0]} / 256 → Dx ENTRY + {(ENTRY – ENTRY (n + 1) Unrounded: ∗ 256 + {(ENTRY ) ∗ Dx [7:0]} → Dx ENTRY –...
Page 203 Freescale Semiconductor, Inc. TBLS TBLS Table Lookup and Interpolate (Signed) TBLSN TBLSN n–1 n–1 Signed table entries range from –2 to 2 – 1, where n is 8, 16, or 32 for byte, word, and long-word tables, respectively. Rounding of the result is optionally selected via the ’R’ instruction field. If R = 0 (TBLS), the fractional portion is rounded according to the round-to-nearest algorithm.
Page 204 Freescale Semiconductor, Inc. TBLS TBLS Table Lookup and Interpolate (Signed) TBLSN TBLSN For all sizes, the 8-bit fractional portion of the result is returned in the low byte of the data register, Dx [7:0]. User software can make use of the fractional data to reduce cumulative errors in lengthy calculations or implement rounding algorithms different from those provided by other forms of TBLS.
Page 205 Freescale Semiconductor, Inc. TBLS TBLS Table Lookup and Interpolate (Signed) TBLSN TBLSN Data Register Interpolate: REGISTER Dym REGISTER Dx SIZE REGISTER Dyn Instruction Fields: Effective address ﬁeld (table lookup and interpolate mode only: Speciﬁes the source location. Only control addressing modes are allowed as...
Page 206 Freescale Semiconductor, Inc. TBLU TBLU Table Lookup and Interpolate (Unsigned) TBLUN TBLUN Operation: Rounded: ) ∗ Dx [7:0]} / 256 → Dx ENTRY + {(ENTRY – ENTRY (n + 1) Unrounded: ∗ 256 + {(ENTRY ) ∗ Dx [7:0]} → Dx ENTRY –...
Page 207 Freescale Semiconductor, Inc. TBLU TBLU Table Lookup and Interpolate (Unsigned) TBLUN TBLUN n–1 Unsigned table entries range from 0 to 2 where n is 8, 16, or 32 for byte, word, and long-word tables, respectively. Unsigned and unrounded table results are zero extend- Rounding of the result is optionally selected via the ’R’...
Page 208 Freescale Semiconductor, Inc. TBLU TBLU Table Lookup and Interpolate (Unsigned) TBLUN TBLUN For all sizes, the 8-bit fractional portion of the result is returned in the low byte of the data register, Dx (7:0). User software can make use of the fractional data to re- duce cumulative errors in lengthy calculations or implement rounding algorithms different from those provided by other forms of TBLU.
Page 209 Freescale Semiconductor, Inc. TBLU TBLU Table Lookup and Interpolate (Unsigned) TBLUN TBLUN Data Register Interpolate: REGISTER Dym REGISTER Dx SIZE REGISTER Dyn Instruction Fields: Effective address ﬁeld (table lookup and interpolate mode only): Speciﬁes the source location. Only control addressing modes are allowed as...
Page 210 Freescale Semiconductor, Inc. Test and Set an Operand Destination Tested → Condition Codes; 1 → bit 7 of Destination Operation: Assembler TAS 〈ea〉 Syntax: Attributes: Size = (Byte) Description: Tests and sets the byte operand addressed by the effective address ﬁeld.
Page 211 Freescale Semiconductor, Inc. Test and Set an Operand Instruction Fields: Effective Address ﬁeld — Speciﬁes the location of the tested oper- and. Only data alterable addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W...
Page 212 Freescale Semiconductor, Inc. TRAP TRAP Trap SSP – 2 → SSP; Format/Offset → (SSP); Operation: SSP – 4 → SSP; PC → (SSP); SSP – 2 → SSP; SR → (SSP); Vector Address → PC Assembler Syntax: TRAP #〈vector〉 Attributes:...
Page 213 Freescale Semiconductor, Inc. TRAPcc TRAPcc Trap on Condition Operation: If cc then TRAP Assembler TRAPcc Syntax: TRAPcc.W #〈data〉TRAPcc.L #〈data〉 Attributes: Unsized or Size = (Word, Long) Description: If the speciﬁed condition is true, causes a TRAPcc exception (vector number 7). The address of the next instruction word (current PC) is pushed onto the stack.
Page 214 Freescale Semiconductor, Inc. TRAPV TRAPV Trap on Overﬂow Operation: If V then TRAP Assembler Syntax: TRAPV Attributes: Unsized Description: If the CCR overﬂow bit is set, there is a TRAPV exception (vector number 7). If the bit is not set, the processor performs no operation and execution continues with the next instruction.
Page 215 Freescale Semiconductor, Inc. Test an Operand Destination Tested → Condition Codes Operation: Assembler TST 〈ea〉 Syntax: Attributes: Size = (Byte, Word, Long) Description: Compares the operand with zero and sets condition codes accord- ing to the results of the test.
Page 216 Freescale Semiconductor, Inc. Test an Operand Effective Address ﬁeld — Speciﬁes the destination operand. All addressing modes are allowed as shown: Addressing Mode Mode Register Addressing Mode Mode Register Reg. number: Dn (xxx).W Reg. number: An (xxx).L (An) Reg. number: An #〈data〉...
Page 217 Freescale Semiconductor, Inc. UNLK UNLK Unlink An → SP; (SP) → An; SP + 4 → SP Operation: Assembler Syntax: UNLK An Attributes: Unsized Description: Loads the stack pointer from the speciﬁed address register then loads the address register with a long word pulled from the top of the stack.
Page 218: Instruction Format Summary
Freescale Semiconductor, Inc. 4.5 Instruction Format Summary A summary of the primary words in each instruction of the instruction set follows. The complete instruction definition consists of the primary words followed by the address- ing mode operands such as immediate data fields, displacements, and index oper- ands.
Page 219 Freescale Semiconductor, Inc. EFFECTIVE ADDRESS SIZE MODE REGISTER WORD DATA (16 BITS) BYTE DATA (8 BITS) LONG DATA (32 BITS) Size Field: 00 = Byte 01 = Word 10 = Long ORI to CCR BYTE DATA (8 BITS) ORI to SR...
Page 220 Freescale Semiconductor, Inc. BCHG (Dynamic) EFFECTIVE ADDRESS REGISTER MODE REGISTER BCLR (Dynamic) EFFECTIVE ADDRESS REGISTER MODE REGISTER BSET (Dynamic) EFFECTIVE ADDRESS REGISTER MODE REGISTER MOVEP DATA REGISTER OPMODE ADDR REGISTER DISPLACEMENT (16 BITS) OPMODE FIELD: 100 = Transfer Word From Memory to Register...
Page 221 Freescale Semiconductor, Inc. SUBI EFFECTIVE ADDRESS SIZE MODE REGISTER WORD DATA (16 BITS) BYTE DATA (8 BITS) LONG DATA (32 BITS) Size Field: 00 = Byte 01 = Word 10 = Long ADDI EFFECTIVE ADDRESS SIZE MODE REGISTER WORD DATA (16 BITS)
Page 222 Freescale Semiconductor, Inc. BSET (Static) EFFECTIVE ADDRESS MODE REGISTER BIT NUMBER Bit Number Field: Modulo 32-bit selection EORI EFFECTIVE ADDRESS SIZE MODE REGISTER WORD DATA (16 BITS) BYTE DATA (8 BITS) LONG DATA (32 BITS) Size Field: 00 = Byte 01 = Word 10 = Long...
Page 223 Freescale Semiconductor, Inc. MOVE DESTINATION EFFECTIVE ADDRESS SIZE REGISTER MODE MODE REGISTER Size Field: 00 = Byte 01 = Word 10 = Long Note register and mode locations. MOVEA DESTINATION EFFECTIVE ADDRESS SIZE REGISTER MODE REGISTER Size Field: 00 = Byte 01 = Word 10 = Long...
Page 224 Freescale Semiconductor, Inc. EFFECTIVE ADDRESS SIZE MODE REGISTER Size Field: 00 = Byte 01 = Word 10 = Long MOVE from CCR EFFECTIVE ADDRESS MODE REGISTER EFFECTIVE ADDRESS SIZE MODE REGISTER Size Field: 00 = Byte 01 = Word 10 = Long...
Page 225 Freescale Semiconductor, Inc. LINK Long REGISTER HIGH-ORDER DISPLACEMENT LOW-ORDER DISPLACEMENT SWAP REGISTER BKPT VECTOR EFFECTIVE ADDRESS MODE REGISTER Size Field: 00 = Byte 01 = Word 10 = Long EXT, EXTB OPMODE REGISTER Opmode Field: 010 = Extend Word 011 = Extend Long 111 = Extend Byte Long...
Page 226 Freescale Semiconductor, Inc. EFFECTIVE ADDRESS SIZE MODE REGISTER Size Field: 00 = Byte 01 = Word 10 = Long EFFECTIVE ADDRESS MODE REGISTER BGND ILLEGAL MULU (Long) EFFECTIVE ADDRESS MODE REGISTER REGISTER Dl SIZE REGISTER Dh Size Field: 0 = Long Word Product 1 = Quad Word Product...
Page 227 Freescale Semiconductor, Inc. LINK (Word) REGISTER WORD DISPLACEMENT UNLK REGISTER MOVE USP REGISTER DR Field: 0 = Move An to USP 1 = Move USP to An RESET STOP IMMEDIATE DATA Format/Offset Word (in stack frame) FORMAT VECTOR OFFSET Format Field: Four bits imply frame size; only values 000–0010 and 1000–1011 are used.
Page 228 Freescale Semiconductor, Inc. TRAPV MOVEC REGISTER CONTROL REGISTER dr Field: 0 = Control Register to General Register 1 = General Register to Control Register Control Register Field: $000 = SFC$801 = VBR $001 = DFC$802 = CAAR $002 = CACR$803 = MSP...
Page 229 Freescale Semiconductor, Inc. EFFECTIVE ADDRESS CONDITION MODE REGISTER DBcc CONDITION REGISTER DISPLACEMENT TRAPcc CONDITION OPMODE OPTIONAL WORD OR LONG WORD Opmode Field: 010 = Word Operand 011 = Long Operand 100 = No Operand SUBQ EFFECTIVE ADDRESS DATA SIZE MODE REGISTER Data Field: Three bits of immediate data;...
Page 230 Freescale Semiconductor, Inc. MOVEQ REGISTER DATA Data Field: Data is sign extended to a long operand, and all 32 bits are transferred to the data register. EFFECTIVE ADDRESS REGISTER OPMODE MODE REGISTER Opmode Field: Byte Word Long Operation 〉 〉...
Page 231 Freescale Semiconductor, Inc. SUBA EFFECTIVE ADDRESS REGISTER OPMODE MODE REGISTER Opmode Field: Word Long Operation 〉 〉 → 〉 〈Dn (〈An ) – (〈ea SUBX REGISTER Rx SIZE REGISTER Ry Size Field: 00 = Byte 01 = Word 10 = Long...
Page 232 Freescale Semiconductor, Inc. CMPM REGISTER Ax SIZE REGISTER Ay Size Field: 00 = Byte 01 = Word 10 = Long EFFECTIVE ADDRESS REGISTER OPMODE MODE REGISTER Opmode Field: Byte Word Long Operation 〉 〉 → 〉 ) • (〈Dn 〈Dn (〈ea...
Page 233 Freescale Semiconductor, Inc. EFFECTIVE ADDRESS REGISTER OPMODE MODE REGISTER Opmode Field: Byte Word Long Operation 〉 〉 → 〉 ) + (〈Dn 〈Dn (〈ea 〉 〉 → 〉 ) + (〈ea 〈ea (〈Dn ADDA EFFECTIVE ADDRESS REGISTER OPMODE MODE REGISTER...
Page 234 Freescale Semiconductor, Inc. LSL, LSR (Register) COUNT/REGISTER SIZE REGISTER Count/Register Field: If I/R Field = 0, Specifies Shift Count If I/R Field = 1, Specifies Data Register that contains Shift Count dr Field: 0 = Right 1 = Left Size Field: 00 = Byte 01 = Word 10 = Long...
Page 235 Freescale Semiconductor, Inc. ROXL, ROXR (Memory) EFFECTIVE ADDRESS MODE REGISTER dr Field: 0 = Right 1 = Left ROL, ROR (Memory) EFFECTIVE ADDRESS MODE REGISTER dr Field: 0 = Right 1 = Left LPSTOP IMMEDIATE DATA TBLU, TBLUN (Data Register Interpolate)
Page 236: Table Lookup And Interpolation Instructions
Freescale Semiconductor, Inc. 4.6 Table Lookup and Interpolation Instructions There are four table lookup and interpolate instructions. TBLS returns a signed, round- ed byte, word, or long-word result. TBLSN returns a signed, unrounded byte, word, or long-word result. TBLU returns an unsigned, rounded byte, word, or long-word result.
Page 237: Table Example 2: Compressed Table
Freescale Semiconductor, Inc. Entry Number Value Value 128* 32768 1311 41472 1659 41728 1669 41984 1679 42240 1690 192* 49152 1966 *These values are the end points of the range. All entries between these points fall on the line. The table instruction is executed with the following bit pattern in Dx: NOT USED Table Entry Offset →...
Page 238 Freescale Semiconductor, Inc. In Example 2, the data from Example 1 has been compressed by limiting the maximum value of the independent variable. Instead of the range 0 ≤ X = 65535, X is limited to 0 ≤ X ≤ 1023. The table has been compressed to only 5 entries, but up to 256 levels of interpolation are allowed between entries.
Page 239: Table Example 3: 8-Bit Independent Variable
Freescale Semiconductor, Inc. 4.6.3 Table Example 3: 8-Bit Independent Variable 3072 4096 1024 2048 INDEPENDENT VARIABLE Figure 4-5 Table Example 3 This example shows how to use a table instruction within an interpolation subroutine. Independent variable X is calculated as an 8-bit value, allowing 16 levels of interpola- tion on a 17-entry table.
Page 240: Table Example 4: Maintaining Precision
Freescale Semiconductor, Inc. The first column is the value passed to the subroutine, the second column is the value expected by the table instruction, and the third column is the result returned by the subroutine. The following value has been calculated for independent variable X:...
Page 241 Freescale Semiconductor, Inc. TLI # 1 0010 0000 . 0111 0000 TLI # 2 0011 1111 . 0111 0000 TLI # 3 0000 0001 . 0111 0000 First, the results of each TLI are rounded with the TBLS round-to-nearest-even algo- rithm.
Page 242: Table Example 5: Surface Interpolations
Freescale Semiconductor, Inc. 4.6.5 Table Example 5: Surface Interpolations The various forms of table can be used to perform surface (3D) TLIs. However, since the calculation must be split into a series of 2D TLIs, the possibility of losing precision in the intermediate results is possible.
Page 243: State Transitions
Freescale Semiconductor, Inc. SECTION 5PROCESSING STATES This section describes the processing states of the CPU32. It includes a functional de- scription of the bits in the supervisor portion of the status register and an overview of actions taken by the processor in response to exception conditions.
Page 244: Supervisor Privilege Level
Freescale Semiconductor, Inc. to all resources, performs the overhead tasks for the user level programs, and coordi- nates their activities. 5.2.1 Supervisor Privilege Level If the S bit in the status register is set, supervisor privilege level applies, and all instruc- tions are executable.
Page 245: Types Of Address Space
During each bus cycle, the processor generates function code signals that permit se- lection of eight distinct 4-Gigabyte address spaces. Not all devices that incorporate the CPU32 support a full complement of memory. (Refer to the appropriate user's manual for details.) Selection varies according to the access required. Automatic selection of supervisor and user space, and of program and data space, is provided.
Page 246: Type 0000 — Breakpoint
T bit A1 designates the type of breakpoint. T = 0 indicates a software breakpoint; T = 1 indicates a hardware breakpoint. 5.3.1.2 Type 0001 — MMU Access This type of access is not supported by the CPU32 processor. This space is reserved for future use. 5.3.1.3 Type 0010 — Coprocessor Access This type of access is not supported by the CPU32 processor.
Page 247: Type 1111 — Interrupt Acknowledge
Freescale Semiconductor, Inc. These control registers, reserved for future expansion, also reside in CPU space 3, and are only accessible through the MOVES command. The general format of this CPU space type is defined as follows: 18 17 16 15...
Page 248 Freescale Semiconductor, Inc. MOTOROLA PROCESSING STATES CPU32 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 249: Definition Of Exception Processing
Freescale Semiconductor, Inc. SECTION 6 EXCEPTION PROCESSING This section discusses system resources related to exception handling, exception pro- cessing sequence, and specific features of individual exception processing routines 6.1 Definition of Exception Processing An exception is a special condition that preempts normal processing. Exception pro- cessing is the transition from normal mode program execution to execution of a routine that deals with an exception.
Page 250: Types Of Exceptions
Freescale Semiconductor, Inc. Table 6-1 Exception Vector Assignments Vector Vector Offset Assignment Number Space Reset: Initial Stack Pointer Reset: Initial Program Counter Bus Error Address Error Illegal Instruction Zero Division CHK, CHK2 Instructions TRAPcc, TRAPV Instructions Privilege Violation Trace Line 1010 Emulator...
Page 251: Exception Processing Sequence
M68000 Family processor, format 0000 is al- ways legal and always indicates that only the first four words of a frame are present. See 6.4 CPU32 Stack Frames for a complete discussion of exception stack frames. CPU32...
Page 252: Multiple Exceptions
6.1.3 Exception Processing Sequence, but does not include execution of handler routines, which is done in normal mode. When the CPU32 completes exception processing, it is ready to begin either exception processing for a pending exception, or execution of a handler routine. Priority assign- ment governs the order in which exception processing occurs, not the order in which exception handlers are executed.
Page 253: Processing Of Specific Exceptions
Execution of the RESET instruction does not cause a reset exception nor does it affect any internal CPU register, but it does cause the CPU32 to assert the RESET signal, resetting all internal and external peripherals.
Page 254: Bus Error
Freescale Semiconductor, Inc. ENTRY T0,T1 12:IO FETCH VECTOR # 0 BUS ERROR OTHERWISE (VECTOR # 0) FETCH VECTOR # 1 BUS ERROR OTHERWISE (VECTOR # 1) PREFETCH FIRST WORD BUS ERROR/ ADDRESS OTHERWISE BEGIN ERROR INSTRUCTION (DOUBLE BUS FAULT) EXECUTION...
Page 255: Address Error
Freescale Semiconductor, Inc. When the aborted bus cycle is an instruction prefetch, the processor will not initiate exception processing unless the prefetched information is used. For example, if a branch instruction flushes an aborted prefetch, that word is not accessed, and no ex- ception occurs.
Page 256: Instruction Traps
Since the VBR on the CPU32 allows relocation of exception vectors, the exception vector ad- dress is not a reliable indication of a breakpoint. CPU32 breakpoint support is provided by extending the function of a set of illegal instructions ($4848–$484F).
Page 257: Format Error
An instruction is illegal if it contains a word bit pattern that does not correspond to the bit pattern of the first word of a legal CPU32 instruction, if it is a MOVEC instruction that contains an undefined register specification field in the first extension word, or if it contains an indexed addressing mode extension word with bits [5:4] = 00 or bits [3:0] ≠...
Page 258: Privilege Violations
Freescale Semiconductor, Inc. All unimplemented instructions are reserved for use by Motorola for enhancements and extensions to the basic M68000 architecture. Opcode pattern $4AFC is defined to be illegal on all M68000 Family members. Those customers requiring the use of an unimplemented opcode for synthesis of “custom instructions,”...
Page 259: Tracing
To aid in program development, M68000 processors include a facility to allow tracing of instruction execution. CPU32 tracing also has the ability to trap on changes in pro- gram flow. In trace mode, a trace exception is generated after each instruction exe- cutes, allowing a debugging program to monitor the execution of a program under test.
Page 260: Interrupts
Freescale Semiconductor, Inc. If an instruction is executed and an interrupt is pending on completion, the trace exception is processed before the interrupt exception. If an instruction forces an exception, the forced exception is processed before the trace exception. If an instruction is executed and a breakpoint is pending upon completion of the in- struction, the trace exception is processed before the breakpoint.
Page 261: Return From Exception
See 6.4 CPU32 Stack Frames for a description of stack frames. For a normal four-word frame, the processor updates the status register and program counter with data pulled from the stack, increments the supervisor stack pointer by eight, and resumes normal instruction execution.
Page 262: Fault Recovery
Freescale Semiconductor, Inc. ister and program counter are updated from the stack, the active supervisor stack pointer is incremented by 12, and normal instruction execution resumes. For a bus fault frame, the format value on the stack is first checked for validity. In ad- dition, the version number on the stack must match the version number of the proces- sor that is attempting to read the stack frame.
Page 263 Freescale Semiconductor, Inc. The TP field defines the class of the faulted bus operation. Two BERR exception frame types are defined. One is for faults on prefetch and operand accesses, and the other is for faults during exception frame stacking: 0 —...
Page 264: Types Of Faults
6.3.1 Types of Faults An efficient implementation of instruction restart dictates that faults on some bus cy- cles be treated differently than faults on other bus cycles. The CPU32 defines four fault types: released write faults, faults during exception processing, faults during MOVEM operand transfer, and faults on any other bus cycle.
Page 265: Type Ii: Prefetch, Operand, Rmw, And Movep Faults
Freescale Semiconductor, Inc. The remainder of the stack contains the program counter of the next unexecuted in- struction, the current status register, the address of the faulted memory location, and the contents of the data buffer which was to be written to memory. This data is written on the stack in the format depicted in Figure 6-3.
Page 266: Type Iv: Faults During Exception Processing
Freescale Semiconductor, Inc. FUNC MV is set, indicating that MOVEM should be continued from the point where the fault occurred upon return from the exception handler. TR, B1, and B0 are set if a corre- sponding exception is pending when the BERR exception is taken. IN is set if a bus fault occurs while refetching an opcode or an extension word during instruction restart.
Page 267: Type I) Completing Released Writes Via Software
Because the CPU32 has a 16-bit internal data bus, long operands require two bus ac- cesses. A fault during the second access of a long operand causes the LG bit in the SSW to be set.
Page 268: Type Iii) Correcting Faults Via Software
Freescale Semiconductor, Inc. 6.3.2.4 (Type III) Correcting Faults via Software Sufficient information is contained in the stack frame to complete MOVEM in software. After the cause of the fault is corrected, the faulted bus cycle must be rerun. Do the following to complete an instruction through software: A.
Page 269: Type Iii) Correcting Faults Via Rte
6.4 CPU32 Stack Frames The CPU32 generates three different stack frames — the normal four- and six-word frames, and the twelve-word BERR stack frame. CPU32...
Page 270: Normal Four-Word Stack Frame
The address to which RTE returns is the address of the next instruction to be executed 6.4.3 BERR Stack Frame This stack frame is created when a bus cycle fault is detected. The CPU32 BERR stack frame differs significantly from the equivalent stack frames of other M68000 Family members.
Page 271: Internal Transfer Count Register
Freescale Semiconductor, Inc. Bus operation in progress at the time of a fault is conveyed by the SSW. FUNC The BERR stack frame is 12 words in length. There are three variations of the frame, each distinguished by different values in the SSW TP and MV fields.
Page 272: Format $C — Berr Stack For Prefetches And Operands
Freescale Semiconductor, Inc. SP → STATUS REGISTER +$02 RETURN PROGRAM COUNTER HIGH RETURN PROGRAM COUNTER LOW +$06 VECTOR OFFSET +$08 FAULTED ADDRESS HIGH FAULTED ADDRESS LOW +$0C DBUF HIGH DBUF LOW +$10 CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW...
Page 273: Cpu32 Integrated Development Support
7.1.1 Background Debug Mode (BDM) Overview Microprocessor systems generally provide a debugger, implemented in software, for system analysis at the lowest level. The BDM on the CPU32 is unique because the debugger is implemented in CPU microcode. BDM incorporates a full set of debug options — registers can be viewed and/or altered, memory can be read or written, and test features can be invoked.
Page 274: Deterministic Opcode Tracking Overview
Figure 7-2 Bus State Analyzer Configuration 7.1.2 Deterministic Opcode Tracking Overview CPU32 function code outputs are augmented by two supplementary signals that mon- itor the instruction pipeline. The instruction fetch (IFETCH) output identifies bus cycles in which data is loaded into the pipeline, and signals pipeline flushes. The instruction pipe (IPIPE) output indicates when each mid-instruction pipeline advance occurs and when instruction execution begins.
Page 275: On-Chip Hardware Breakpoint Overview
BDM can be initiated in several ways — by externally generated breakpoints, by inter- nal peripheral breakpoints, by the background (BGND) instruction, or by catastrophic exception conditions. While in BDM, the CPU32 ceases to fetch instructions via the parallel bus and communicates with the development system via a dedicated, high- speed, SPI-type serial command interface.
Page 276: Enabling Bdm
7.2.1 Enabling BDM Accidentally entering BDM in a non-development environment could lock up the CPU32 since the serial command interface would probably not be available. For this reason, BDM is enabled during reset via the breakpoint (BKPT) signal. BDM operation is enabled when BKPT is asserted (low), at the rising edge of RESET.
Page 277: Double Bus Fault
Freescale Semiconductor, Inc. 7.2.2.3 Double Bus Fault The CPU32 normally treats a double bus fault, or two bus faults in succession, as a catastrophic system error, and halts. When this condition occurs during initial system debug (a fault in the reset logic), further debugging is impossible until the problem is corrected.
Page 278: Background Mode Registers
Freescale Semiconductor, Inc. 7.2.5 Background Mode Registers BDM processing uses three special purpose registers to keep track of program context during development. A description of each follows. 7.2.5.1 Fault Address Register (FAR) The FAR contains the address of the faulting bus cycle immediately following a bus or address error.
Page 279: Current Instruction Program Counter (Pcc)
DSCLK. If DSCLK is derived from the CPU32 system clock, development system serial logic is unhindered by the oper- ating frequency of the target processor. Operable frequency range of the serial clock is from DC to one-half the processor system clock frequency.
Page 280: Cpu Serial Logic
Freescale Semiconductor, Inc. Table 7-3 CPU Generated Message Encoding Bit 16 Data Message Type xxxx Valid Data Transfer FFFF Command Complete; Status OK 0000 Not Ready with Response; Come Again 0001 BERR Terminated Bus Cycle; Data Invalid FFFF Illegal Command Command and data transfers initiated by the development system should clear bit 16.
Page 281: Serial Interface Timing Diagram
CLKOUT. At the falling edge of CLKOUT, the sampled value is made available to internal logic. If there is no synchronization between CPU32 and development system hardware, the minimum hold time on DSI with respect to DSCLK is one full period of CLKOUT.
Page 282: Development System Serial Logic
Another method is to assert BKPT, then continue to assert it until the CPU32 responds by asserting FREEZE. This method is useful for forcing a transi- tion into BDM when the bus is not being monitored. Each of these methods requires a slightly different serial logic design to avoid spurious serial clocks.
Page 283: Command Set
Figure 7-9 BKPT/DSCLK Logic Diagram BKPT_TAG should be timed to the bus cycles since it is not latched. If extended past the assertion of FREEZE, the negation of BKPT_TAG appears to the CPU32 as the first DSCLK. DSCLK is the gated serial clock. Normally high, it pulses low for each bit to be trans- ferred.
Page 284: Command Sequence Diagram
Freescale Semiconductor, Inc. Operand Size: For sized operations, this field specifies the operand data size. All addresses are expressed as 32-bit absolute values. The size field is encoded as follows: Encoding Operand Size Byte Word Long Reserved Address/Data (A/D) Field: The A/D field is used by commands that operate on address and data registers.
Page 285: Command-Sequence-Diagram Example
Freescale Semiconductor, Inc. NOTE The “not ready” response can be ignored unless a memory bus cycle is in progress. Otherwise, the CPU can accept a new serial transfer with eight system clock periods. In the third cycle, the development system supplies the low-order 16 bits of a memory address.
Page 286: Command Set Summary
Freescale Semiconductor, Inc. 7.2.8.3 Command Set Summary The BDM command set is summarized in Table 7-4. Subsequent paragraphs contain detailed descriptions of each command. Table 7-4 BDM Command Summary Command Mnemonic Description Read A/D Register RAREG/RDREG Read the selected address or data register and return the results via the serial interface.
Page 287: Read A/D Register (Rareg/Rdreg)
Freescale Semiconductor, Inc. 7.2.8.4 Read A/D Register (RAREG/RDREG) Read the selected address or data register and return the results via the serial inter- face. Command Format: REGISTER Command Sequence: RDREG/RAREG NEXT CMD MS RESULT LS RESULT NEXT CMD "ILLEGAL" "NOT READY"...
Page 288: Read System Register (Rsreg)
Freescale Semiconductor, Inc. 7.2.8.6 Read System Register (RSREG) The specified system control register is read. All registers that can be read in supervi- sor mode can be read in BDM. Several internal temporary registers are also accessi- ble. Command Format:...
Page 289: Read Memory Location (Read)
Freescale Semiconductor, Inc. REGISTER Command Sequence: WSREG MS DATA LS DATA NEXT CMD "NOT READY" "NOT READY" "CMD COMPLETE" NEXT CMD "ILLEGAL" "NOT READY" Operand Data: The data to be written into the register is always supplied as a 32-bit long word. If the register is less than 32 bits, the least significant word is used.
Page 290: Write Memory Location (Write)
Freescale Semiconductor, Inc. READ READ (B/W) MS ADDR LS ADDR MEMORY "NOT READY" "NOT READY" "NOT READY" LOCATION NEXT CMD NEXT CMD RESULT "ILLEGAL" "NOT READY" NEXT CMD BERR/AERR "NOT READY" READ READ READ (LONG) MS ADDR LS ADDR MEMORY MEMORY "NOT READY"...
Page 291: Dump Memory Block (Dump)
Freescale Semiconductor, Inc. WRITE WRITE (B/W) MS ADDR LS ADDR DATA MEMORY "NOT READY" "NOT READY" "NOT READY" "NOT READY" LOCATION NEXT CMD NEXT CMD "ILLEGAL" "NOT READY" "CMD COMPLETE" BERR/AERR NEXT CMD "NOT READY" WRITE (LONG) MS ADDR LS ADDR MS DATA "NOT READY"...
Page 292 Freescale Semiconductor, Inc. NOTE The DUMP command does not check for a valid address in the tem- porary register — DUMP is a valid command only when preceded by another DUMP or by a READ command. Otherwise, the results are undefined.
Page 293: Fill Memory Block (Fill)
Freescale Semiconductor, Inc. 7.2.8.11 Fill Memory Block (FILL) FILL is used in conjunction with the WRITE command to fill large blocks of memory. An initial WRITE is executed to set up the starting address of the block and to supply the first operand.
Page 294: Resume Execution (Go)
Freescale Semiconductor, Inc. 7.2.8.12 Resume Execution (GO) The pipeline is flushed and refilled before normal instruction execution is resumed. Prefetching begins at the return PC and current privilege level. If either the PC or SR is altered during BDM, the updated value of these registers is used when prefetching commences.
Page 295 Freescale Semiconductor, Inc. If a bus error or address error occurs on the first instruction prefetch from the new PC, the processor exits BDM and the error is trapped as a normal mode exception. The stacked value of the current PC may not be valid in this case, depending on the state of the machine prior to entering BDM.
Page 296: Reset Peripherals (Rst)
Freescale Semiconductor, Inc. 7.2.8.14 Reset Peripherals (RST) RST asserts RESET for 512 clock cycles. The CPU is not reset by this command. This command is synonymous with the CPU RESET instruction. Command Format: Command Sequence: RESET ASSERT RESET "NOT READY"...
Page 297: Future Commands
NOP and return the ILLEGAL command response. 7.3 Deterministic Opcode Tracking The CPU32 utilizes deterministic opcode tracking to trace program execution. Two signals, IPIPE and IFETCH, provide all the information required to analyze the opera- tion of the instruction pipeline.
Page 298: Functional Model Of Instruction Pipeline
Freescale Semiconductor, Inc. DATA EXTENSION OPCODES WORDS RESIDUAL Figure 7-11 Functional Model of Instruction Pipeline Assertion of IPIPE for a single clock cycle indicates the use of data from IRB. Regard- less of the presence of valid data in IRA, the contents of IRB are invalidated when IPIPE is asserted.
Page 299: Opcode Tracking During Loop Mode
Freescale Semiconductor, Inc. have occurred). Loading IRC always indicates that an instruction is beginning execu- tion — the opcode is loaded into IRC by the transfer. In some cases, instructions using immediate addressing begin executing and initiate a second pipeline advance at the same time. IPIPE will not be negated between the two indications, which implies the need for a state machine to track the state of IPIPE.
Page 300 Freescale Semiconductor, Inc. MOTOROLA DEVELOPMENT SUPPORT CPU32 7-28 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 301: Resource Scheduling
8.1 Resource Scheduling The CPU32 contains several independently scheduled resources. The organization of these resources within the CPU32 is shown in Figure 8–1. Some variation in instruc- tion execution timing results from concurrent resource utilization. Because resource scheduling is not directly related to instruction boundaries, it is impossible to make an accurate prediction of the time required to complete an instruction without knowing the entire context within which the instruction is executing.
Page 302: Instruction Pipeline
Figure 8–1 Block Diagram of Independent Resources 8.1.2 Instruction Pipeline The CPU32 contains a two-word instruction pipeline where instruction opcodes are decoded. Each stage of the pipeline is initially filled under microsequencer control and subsequently refilled by the prefetch controller as it empties.
Page 303: Prefetch Controller
If instruction prefetches, rather than operand accesses, were given priority, many instruction words would be flushed unused, and necessary oper- and cycles would be delayed. To maximize available bus bandwidth, the CPU32 will schedule a prefetch only when the next instruction is not a change-of-flow instruction, and when there is room in the pipeline for the prefetch.
Page 304: Instruction Execution Overlap
Freescale Semiconductor, Inc. 8.1.4 Instruction Execution Overlap Overlap is the time, measured in clock cycles, that an instruction executes concurrent- ly with the previous instruction. As shown in Figure 8-2, portions of instructions A and B execute simultaneously, so that total execution time is reduced. Because portions of instructions B and C also overlap, overall execution time for all three instructions is also reduced.
Page 305: Effects Of Wait States
Freescale Semiconductor, Inc. 8.1.5 Effects of Wait States The CPU32 access time for on-chip memory and peripherals is two clocks. While two- clock external accesses are possible when the bus is operated in a synchronous mode, a typical external memory speed is three or more clocks.
Page 306: Effects Of Negative Tails
8.1.7 Effects of Negative Tails When the CPU32 changes instruction flow, the instruction decode pipeline must begin refilling before instruction execution can resume. Refilling forces a two-clock idle peri- od at the end of the change of flow instruction.
Page 307: Instruction Stream Timing Examples
Freescale Semiconductor, Inc. In the following equations, negative tail values are used to negate the effects of a slow- er bus. The equations are generalized, however, so that they may be used on any speed bus with any tail value.
Page 308: Timing Example 2: Branch Instructions
Freescale Semiconductor, Inc. 8.2.2 Timing Example 2: Branch Instructions Example 2 shows what happens when a branch instruction is executed, in both the taken and not-taken cases. (Refer to Figures 8-5 and 8-6). The instruction stream is for a simple limit check with the variable already in a data register.
Page 309: Timing Example 3: Negative Tails
BRA.WFARAWAY MOVE.LD1, D0 Although the CPU32 has a two-word instruction pipeline, internal delay causes mini- mum branch instruction time to be three bus cycles. The negative tail is a reminder that an extra two clocks are available for prefetching a third word on a fast bus — on a slow- er bus, there is no extra time for the third word.
Page 310: Instruction Timing Tables
Freescale Semiconductor, Inc. 8.3 Instruction Timing Tables The following assumptions apply to the times shown in the tables in this section: • A 16-bit data bus is used for all memory accesses. • Memory access times are based on two clock bus cycles with no wait states.
Page 311 Freescale Semiconductor, Inc. 10 2 1 0 TOTAL NUMBER OF CLOCKS NUMBER OF READ CYCLES NUMBER OF INSTRUCTION ACCESS CYCLES NUMBER OF WRITE CYCLES The total number of bus-activity clocks is: (2 Reads × 2 Clocks/Read) + (1 Instruction Access × 2 Clocks/Access) + (0 Writes ×...
Page 312: Fetch Effective Address
Freescale Semiconductor, Inc. 8.3.1 Fetch Effective Address The fetch effective address table indicates the number of clock periods needed for the processor to calculate and fetch the specified effective address. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number.
Page 313: Calculate Effective Address
Freescale Semiconductor, Inc. 8.3.2 Calculate Effective Address The calculate effective address table indicates the number of clock periods needed for the processor to calculate a specified effective address. The timing is equivalent to fetch effective address except there is no read cycle. The tail and cycle time are re- duced by the amount of time the read would occupy.
Page 314: Move Instruction
Freescale Semiconductor, Inc. 8.3.3 MOVE Instruction The MOVE instruction table indicates the number of clock periods needed for the pro- cessor to calculate the destination effective address and to perform a MOVE or MOVEA instruction. For entries with CEA or FEA, refer to the appropriate table to cal- culate that portion of the instruction time.
Page 315: Arithmetic/Logic Instructions
Freescale Semiconductor, Inc. Instruction Head Tail Cycles Rn, Rm 4(0/1/0) MOVEC Cr, Rn 14(0/2/0) MOVEC Rn, Cr 14-16(0/1/0) MOVE CCR, Dn 4(0/1/0) CCR, 〈CEA〉 MOVE 4(0/1/1) MOVE Dn, CCR 4(0/1/0) 〈FEA〉, CCR MOVE 4(0/1/0) MOVE SR, Dn 4(0/1/0) SR, 〈CEA〉...
Page 316 Freescale Semiconductor, Inc. Instruction Head Tail Cycles ADD(A) Rn, Rm 2(0/1/0) 〈FEA〉, Rn ADD(A) 2(0/1/0) Dn, 〈FEA〉 5(0/1/x) Dn, Dm 2(0/1/0) 〈FEA〉, Dn 2(0/1/0) Dn, 〈FEA〉 5(0/1/x) Dn, Dm 2(0/1/0) Dn, 〈FEA〉 5(0/1/x) Dn, Dm 2(0/1/0) 〈FEA〉, Dn 2(0/1/0) Dn, 〈FEA〉...
Page 317: Immediate Arithmetic/Logic Instructions
Freescale Semiconductor, Inc. 8.3.6 Immediate Arithmetic/Logic Instructions The immediate arithmetic/logic instruction table indicates the number of clock periods needed for the processor to fetch the source immediate data value and to perform the specified arithmetical/logical instruction using the specified addressing mode. Foot- notes indicate when to account for the appropriate fetch effective or fetch immediate effective address times.
Page 318: Binary-Coded Decimal And Extended Instructions
Freescale Semiconductor, Inc. 8.3.7 Binary-Coded Decimal and Extended Instructions The binary-coded decimal and extended instruction table indicates the number of clock periods needed for the processor to perform the specified operation using the specified addressing mode. No additional tables are needed to calculate total effective execution time for these instructions.
Page 319: Shift/Rotate Instructions
Freescale Semiconductor, Inc. 8.3.9 Shift/Rotate Instructions The shift/rotate instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. Footnotes indicate when to account for the appropriate effective address times. The number of bits shifted does not affect the execution time, unless noted.
Page 320: Bit Manipulation Instructions
Freescale Semiconductor, Inc. 8.3.10 Bit Manipulation Instructions The bit manipulation instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. The total number of clock cycles is outside the parentheses. The numbers inside parenthe- ses (r/p/w) are included in the total clock cycle number.
Page 321: Control Instructions
Freescale Semiconductor, Inc. 8.3.12 Control Instructions The control instruction table indicates the number of clock periods needed for the pro- cessor to perform the specified operation on the given addressing mode. Footnotes indicate when to account for the appropriate effective address times. The total number of clock cycles is outside the parentheses.
Page 322: Save And Restore Operations
Freescale Semiconductor, Inc. Instruction Head Tail Cycles BKPT (Acknowledged) 14(1/0/0) −2 BKPT (Bus Error) 35(3/2/4) Breakpoint (Acknowledged) 10(1/0/0) −2 Breakpoint (Bus Error) 42(3/2/6) −2 Interrupt 30(3/2/4)∗ RESET 518(0/1/0) STOP 12(0/1/0) −2 LPSTOP 25(0/3/1) −2 Divide-by-Zero 36(2/2/6) −2 Trace 36(2/2/6) −2...
Page 323 Freescale Semiconductor, Inc. APPENDIX AM68000 FAMILY SUMMARY Appendix A summarizes the characteristics of the microprocessors in the M68000 Family. The M68000 user’s manual includes more detailed information about the MC68000 and MC68010 differences. MC68000 MC68010 CPU32 MC68020 Data Bus Size (Bits)
Page 324 Freescale Semiconductor, Inc. MC68000 USP, SSP MC68010 USP, SSP CPU32 USP, SSP MC68020 USP, SSP (MSP, ISP) Status Register Bits MC68000 T, S, I0/I1/I2, X/N/Z/V/C MC68010 T, S, I0/I1/I2, X/N/Z/V/C CPU32 T1/T0, S, I0/I1/I2, X/N/Z/V/C MC68020 T1/T0, S, M, I0/I1/I2, X/N/Z/V/C...
Page 325 Freescale Semiconductor, Inc. Table A-1 M68000 instruction Set Extensions Mnemonic Description CPU32 M68020 ◊ ◊ Supports 32-Bit Displacement ◊ BFxxxx Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFO, BFINS, BFSET, BFTST) ◊ BGND Background Operation ◊ ◊ BKPT New Instruction Function ◊...
Page 326 Freescale Semiconductor, Inc. Table A-2 M68000 Addressing Modes Mode Mnemonic MC68010/ CPU32 MC68020 MC68000 ◊ ◊ ◊ Register Direct ◊ ◊ ◊ Address Register Indirect (An) ◊ ◊ ◊ Address Register Indirect with (An)+ Postincrement ◊ ◊ ◊ Address Register Indirect with-(An)
Page 327 Freescale Semiconductor, Inc. INDEX –A– Sources 7-4 Registers 7-6 Serial Interface 7-7 Absolute Long Address Mode 3-9 BGND Instruction 7-4 Absolute Short Address Mode 3-8 Binary-Coded Decimal Operations 4-10 AC Electrical Specifications, Bit Manipulation Operations 4-10 See appropriate user’s manual...
Page 328 Freescale Semiconductor, Inc. –G– Double Bus Faults 6-5, 7-5 Dynamic Bus Sizing 6-16, 6-23 General Description 1-1 –E– –H– Effective Address 3-3 Calculation Timing Table (CEA) 8-13 Halt Operation 5-1 Encoding Summary 3-9 Fetch Timing Table (FEA) 8-12 –I– Enhanced Addressing Modes 1-4...
Page 329 Freescale Semiconductor, Inc. Addressing Modes 3-4 Implicit 3-2 Indirect Addressing 3-4 Program 3-1 Organization 2-6 Register Direct Mode 3-3 Virtual 1-2 Registers Microbus Controller 8-3 Address 2-5 Microsequencer 8-1 Condition Code 2-3, 4-5 Model, Programming 2-1 Control 2-5 Move Instruction Timing 8-14...
Page 330 Freescale Semiconductor, Inc. Standard Usage 4-188 Surface Interpolations 4-194 Instruction, Using the 4-188 Tests, Condition 4-12 Timing Examples Branch Instructions 8-8 Execution Overlap 8-7 Negative Tails 8-9 Timing Tables 8-10 Arihmetic/Logic Instructions 8-15 Binary-Coded Decimal/Extended Instructions 8-18 Bit Manipulation Instructions 8-20...

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