Core System's Routines And Macros - Freescale Semiconductor DSP56800E User Manual

2.4

Core System's Routines and Macros

This section describes routines, macros and intrinsic function redefinition provided by the Core
System Infrastructure.
2.4.1 Architecture dependent routines
This section describes architecture dependent routines and macros which provide interface to the
56800E core architecture. It encapsulates the unique features of the 56800E architecture into the
abstract APIs. All routines are defined in the arch.h header file.
2.4.1.1 archEnableInt - enable interrupts
Call(s):
void archEnableInt(void);
Arguments: None.
Description: The archEnableInt macro enables all interrupts by clearing bits I1 (Bit 9) and I0
(Bit 8) in the Status Register (SR).
Example 2-3. archEnableInt macro usage
archEnableInt();
2.4.1.2 archEnableIntLvl123 - enable interrupt levels 1, 2 and 3
Call(s):
void archEnableIntLvl123(void);
Arguments: None.
Description: The archEnableIntLvl123 macro enables interrupts at levels 1, 2 and 3 while
masking the interrupts at level 0. It is accomplished by clearing bit I1 (Bit 9) and setting bit I0 (Bit
8) in the Status Register (SR).
Example 2-4. archEnableIntLvl123 macro usage
archEnableIntLvl123();
FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform
Boot Sequence
2-7