80A01 Trigger Prescale Preamplifier Module; 80A02 Eos/Esd Protection Module; 80A05 Electrical Clock Recovery Module - Tektronix DSA8200 Service Manual

80A01 Trigger Prescale Preamplifier Module

80A02 EOS/ESD Protection Module

80A05 Electrical Clock Recovery Module

DSA8200 Digital Serial Analyzer and Modules Service Manual
The 80A01 module is designed to increase the sensitivity of the prescale trigger
input of the DSA8200 to ≤200 mV
The major function block of the module is a high sensitivity, high gain RF
amplifier. The input and output to this amplifier are routed to two identical
SMA, female connectors, labelled Input and Output at the module front panel.
The module receives power from the main instrument through a single connector
at the rear of the module. The power LED indicates the module is receiving
power through the interface connector.
For major functional circuit blocks refer to Figure 5- -3 on page 5- -4.
The 80A02 EOS/ESD (Electrical Over Stress/Electro-Static Discharge)
protection module works with any DSA8200 instrument and provides static
electricity damage protection to vulnerable sampling head input stages and/or
other sensitive elements.
The 80A02 EOS/ESD module has a 26 GHz bandwidth, making it possible to
provide static protection to a sensitive single input channel of a sampling
oscilloscope with very minimal speed degradation.
The 80A02 EOS/ESD module is designed to work with either the Tektronix
P8018 probe for manual test station static protection as well as automated test
stations.
For major functional circuit blocks refer to Figure 5- -4 on page 5- -5.
The electrical clock recovery module is capable of performing clock recovery on
the input signal (signal input must meet data rate and format requirements), and
provides this signal as a trigger source to the DSA8200.
Front panel connectors provide a replica of the recovered clock signal.
The module uses one of two separate clock recovery circuits dependant on the
specified data rate. The single-ended or complementary input signals are split
with a 1:2 divider and routed to the two circuits.
The low bandwidth circuit recovers clock and data from input data in the
50 Mb/s to 2.7 Gb/s range. The recovered clock from this circuit is routed
directly to the front panel and internal trigger.
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pk-pk
Theory of Operation
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