Ist Flag And Parallel Poll Enable (Ppe) Register - R&S EB200 Manual

EB200 Manual
Bit no. Meaning
6 MSS bit (master status summary bit)
The bit is set if the device triggers a service request. This is the case if one of the other bits of this registers is set
together with its mask bit in the service request enable register SRE.
7 OPERation status register summary bit
The bit is set if an EVENt bit is set in the OPERation status register and the corresponding ENABle bit is set to 1.
A set bit indicates that the device is just performing an action. The type of action can be determined by polling the
QUEStionable status register.

4.7.3.2 IST flag and Parallel Poll Enable (PPE) register

Analogous to the SRQ, the IST flag combines the entire status information in a single bit. It can be
queried by using command "*IST?".
The parallel poll enable register (PPE) determines which bits of the STB contribute to the IST flag. The
bits of the STB are ANDed with the corresponding bits of the PPE. In contrast to SRE bit 6 is also used
here. The IST flag results from the ORing of all results. The PPE can be set using the "*PRE"
commands and read using the "*PRE?" command.
4052.2000.02 4.132
Remote control
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