Samsung S5PC110 Manual page 600

S5PC110_UM
SROM_BW
AddrMode0
DataWidth0
Bit
1 = Enables WAIT
[1] Select SROM ADDR Base for Memory Bank0
0 = SROM_ADDR is Half-word base address.
(SROM_ADDR[22:0] <= HADDR[23:1])
1 = SROM_ADDR is byte base address
(SROM_ADDR[22:0] <= HADDR[22:0])
Note: When DataWidth0 is "0", SROM_ADDR is byte base
address. (Ignored this bit.)
[0] Data bus width control for Memory Bank0
1 = 16-bit
Note: Only 16bit for bank0, can't change
Description
2 SROM CONTROLLER
Initial State
0
1
2-8