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Although it is similar to the normal handshaking, the debugger polling of RR is bypassed with the
assumption that the debug handler can read the previous data from RX before the debugger can
scan in the new data.
Table 10-10. High-Speed Download Handshaking States
Debugger Actions
Debugger wants to transfer code into the Intel® XScale™ core system memory.
Prior to starting download, the debugger must poll the RR bit until it is clear. Once the RR bit is clear, indicating
the debug handler is ready, the debugger starts the download.
The debugger scans data into JTAG to write to the RX register with the download bit and the valid bit set.
Following the write to RX, the RR bit and D bit are automatically set in TXRXCTRL.
Without polling of RR to see whether the debug handler has read the data just scanned in, the debugger
continues scanning in new data into JTAG for RX, with the download bit and the valid bit set.
An overflow condition occurs if the debug handler does not read the previous data before the debugger
completes scanning in the new data, (see
condition).
After completing the download, the debugger clears the D bit allowing the debug handler to exit the download
loop.
Debug Handler Actions
Debug handler is in a routine waiting to write data out to memory. The routine loops based on the D bit in
TXRXCTRL.
The debug handler polls the RR bit until it is set. It then reads the Rx register, and writes it out to memory. The
handler loops, repeating these operations until the debugger clears the D bit.
10.7.2
Overflow Flag (OV)
The Overflow flag is a sticky flag that is set when the debugger writes to the RX register while the
RR bit is set.
The flag is used during high-speed download to indicate that some data was lost. The assumption
during high-speed download is that the time it takes for the debugger to shift in the next data word
is greater than the time necessary for the debug handler to process the previous data word. So,
before the debugger shifts in the next data word, the handler will be polling for that data.
However, if the handler incurs stalls that are long enough such that the handler is still processing
the previous data when the debugger completes shifting in the next data word, an overflow
condition occurs and the OV bit is set.
Once set, the overflow flag will remain set, until cleared by a write to TXRXCTRL with an MCR.
After the debugger completes the download, it can examine the OV bit to determine if an overflow
occurred. The debug handler software is responsible for saving the address of the last valid store
before the overflow occurred.
10.7.3
Download Flag (D)
The value of the download flag is set by the debugger through JTAG. This flag is asserted during
high-speed download to replace a loop counter.
Using the download flag, the debug handler loops until the debugger clears the flag. Therefore,
when doing a high-speed download, for each data word downloaded, the debugger should set the D
bit. On completing the download the debugger clears the D bit releasing the debug handler to take
the data.
Intel® XScale™ Microarchitecture User's Manual
Section 10, "Overflow Flag (OV)"
Software Debug
for more details on the overflow
10-13
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