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Intel BX80623I52500K Specification

Specification update
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Intel
Pentium
4 Processor
Specification Update
August 2008
Revision 071
Document Number: 249199-071

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  • Page 1 ® ® Intel Pentium 4 Processor Specification Update August 2008 Revision 071 Document Number: 249199-071...
  • Page 2 Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Intel Pentium 4 processor, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

  • Page 3: Table Of Contents

    Contents Preface..........................9 Summary Tables of Changes....................11 General Information ......................21 Identification Information ....................24 Errata ..........................31 Specification Changes....................... 69 Specification Clarifications ....................70 Documentation Changes ....................74 § Specification Update...

  • Page 4: Revision History

    May 2001 • Updated the Intel Pentium 4 Processor Identification Information table. Added erratum N49. ® • Updated Specification Update product key to include the Intel -009 June 2001 ™ Xeon processor. Updated erratum N45, added erratum N50 and Specification Change N1.
  • Page 5 Revision Description Date • Added Documentation Change N4. -018 January 2002 • Added errata N60 and N61. -019 February 2002 • Added Documentation Change N5 -020 March 2002 • Added errata N62 and N63. Removed Documentation Changes, -021 April 2002 Specification Clarifications, and Specification Changes that have been incorporated into documentation.
  • Page 6 4 processor on 90 nm process documentation • Added Erratum N89 thru N91 -050 • Added Figure Numbers to each Figure “Out of Cycle” June 21 2004 • Added content for Intel Pentium 4 Extreme Edition on 0.13 Specification Update...
  • Page 7 Revision Description Date micron process in 775-LGA package Added Figure 5 Added Datasheet information and its link Added S-spec number SL7GD -051 • Added S-Spec number under identification information table Aug 2004 • Updated Summary Tables of Changes (Errata N16, N51, N56, N69, N79, N84, N85 and N92) •...
  • Page 8 Revision Description Date • Updated Summary Table of Changes. -069 May 2007 • Updated Summary Table of Changes. -070 April 2008 • Updated Summary Table of Changes -071 August 2008 § Specification Update...

  • Page 9: Preface

    See <<http:// www.intel.com/info/hyperthreading/>> for more information including details on which processors support HT Technology. Related Documents Document Title and Link ® Intel 64 and IA-32 Intel Architectures Software Developer's Manual Volume 1: Basic Specification Update...
  • Page 10 64 and IA-32 Intel Architectures Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z ® Intel 64 and IA-32 Intel Architectures Software Developer's Manual Volume 3A: System Programming Guide ® Intel 64 and IA-32 Intel Architectures Software Developer's Manual Volume 3B: System...

  • Page 11: Summary Tables Of Changes

    The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
  • Page 12 Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel®...
  • Page 13 Quad-Core Intel® Xeon® processor 5400 series Dual-Core Intel® Xeon® processor 5200 series AZ = Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45- nm Process AAA = Quad-Core Intel® Xeon® processor 3300 series AAB = Dual-Core Intel® Xeon® E3110 Processor AAC = Intel®...
  • Page 14 Summary Tables of Changes Plan ERRATA Uncacheable (UC) code in same line as Fixed write back (WB) data may lead to data corruption No Fix Transaction is not retried after BINIT# Invalid opcode 0FFFh requires a ModRM No Fix byte RFO-ECC-snoop-MCA combination can Fixed result in two lines being corrupted in...
  • Page 15 Summary Tables of Changes Plan ERRATA register Processor may hang on a correctable Fixed error and snoop combination The IA32_MC1_STATUS register may No Fix contain incorrect information for correctable errors MCA error incorrectly logged as Fixed prefetches Speculative loads which hit the L2 Fixed cache and get an uncorrectable error will log erroneous information...
  • Page 16 Summary Tables of Changes Plan ERRATA as expected Processor may Timeout Waiting for a Fixed Device to Respond after ~0.67 Seconds Cascading of Performance Counters No Fix does not work Correctly when Forced Overflow is Enabled Possible Machine Check Due to Line- Fixed Split Loads with Page-Tables in Uncacheable (UC) Space...
  • Page 17 Summary Tables of Changes Plan ERRATA Associated counting logic must be Fixed configured when using Event Selection Control (ESCR) MSR IA32_MC0_ADDR and IA32_MC0_MISC registers will contain invalid or stale No Fix data following a Data, Address, or Response Parity Error CR2 may be incorrect or an incorrect page fault error code may be pushed Fixed...
  • Page 18 Summary Tables of Changes Plan ERRATA The TCK Input in the Test Access Port (TAP) is Sensitive to Low Clock Edge Fixed Rates and Prone to Noise Coupling Onto TCK's Rising or Falling Edges Disabling a Local APIC Disables Both Logical Processor APICs on a Hyper- No Fix Threading Technology Enabled...
  • Page 19 Event Based Sampling) May Update Memory outside the BTS/PEBS Buffer Brand String Field Reports Incorrect Maximum ® ® Operating Frequency on Intel Pentium No Fix Extreme Edition Processor with 1066 MHz Memory Ordering Failure May Occur with Snoop Filtering Third Party Agents after...
  • Page 20 Summary Tables of Changes Plan ERRATA when an Interrupt is Pending May Cause an Unexpected Interrupt Using 2M/4M Pages When A20M# Is N102 No Fix Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper N103 No Fix Semaphores or Barriers May Expose a...

  • Page 21: General Information

    General Information General Information ® ® Figure 1 Intel Pentium 4 Processor in the 423-Pin Package and Boxed Pentium 4 Processor in the 423-Pin Package Markings Frequency/Cache/Bus/Voltage ® ® ®bbb ®bbb pentium pentium 2-D Matrix Mark 1.5GHz/256/400/1.7V 1.5GHz/256/400/1.7V SL4SH MALAY...
  • Page 22 General Information ® ® Figure 4 Intel Pentium 4 Processor with 512-KB L2 Cache on 0.13 Micron Process, ® ® Intel Pentium 4 Processor Extreme Edition Supporting Hyper-Threading Technology, and Boxed Pentium 4 Processor with 512-KB L2 Cache on 0.13...
  • Page 23 General Information ® ® Figure 7 Intel Pentium 4 Extreme Edition on 0.13 micron in the 775-Land LGA Package Marking Frequency/ L2 Cache/ S-Spec/ INTEL Country of Assy ® PENTIUM 3.40 GHZ/512/800 SYYYY XXXXXX FFFFFFFF Unique Unit 2-D Matrix Mark...

  • Page 24: Identification Information

    Device ID registers accessible through Boundary Scan. The Brand ID corresponds to bits [7:0] of the EBX register after the CPUID instruction is executed with a 1 in the EAX register. ® ® Table 1. Intel Pentium 4 Processor Identification Information Core L2 Cache...
  • Page 25 Identification Information Core L2 Cache S-Spec CPUID Speed Core/Bus Package and Revision Notes Stepping Size (bytes) SL4X4 256K 0F0Ah 1.60GHz/400MHz 31.0 mm OOI rev 1.0 1, 3 SL57V 256K 0F0Ah 1.70GHz/400MHz 31.0 mm OOI rev 1.0 1, 3 SL4X5 256K 0F0Ah 1.80GHz/400MHz 31.0 mm OOI rev 1.0...
  • Page 26 Identification Information Core L2 Cache S-Spec CPUID Speed Core/Bus Package and Revision Notes Stepping Size (bytes) SL5UJ 256K 0F12h 1.60GHz/400MHz 31.0 mm FC rev 1.0 1, 4 SL5UG 256K 0F12h 1.70GHz/400MHz 31.0 mm FC rev 1.0 1, 4 SL62Z 256K 0F12h 1.70GHz/400MHz 31.0 mm FC rev 1.0...
  • Page 27 Identification Information Core L2 Cache S-Spec CPUID Speed Core/Bus Package and Revision Notes Stepping Size (bytes) SL6S7 512K 0F27h 2.00GHz/400MHz 31.0 mm FC rev 1.0 5, 16 SL6S8 512K 0F27h 2.20GHz/400MHz 31.0 mm FC rev 1.0 5, 16 SL6RY 512K 0F27h 2.26GHz/533MHz 31.0 mm FC rev 1.0...
  • Page 28 Identification Information Core L2 Cache S-Spec CPUID Speed Core/Bus Package and Revision Notes Stepping Size (bytes) SL6QN 512K 0F29h 2.2GHz/400MHz 31.0 mm FC rev 1.0 1, 5, 16 SL6QP 512K 0F29h 2.4GHz/400MHz 31.0 mm FC rev 1.0 1, 5, 16 SL6QQ 512K 0F29h...
  • Page 29 ® ® These parts have some specifications that differ from those in the Intel Pentium Processor in the 478-pin Package datasheet. The specifications that are different from the datasheet are: Vmax = 1.665 V, Vmin = 1.570 V, Icc_max = 46.1 A, TDP = 62.9 W, Tcase = 71 °C, Isgnt = 15.8 A.
  • Page 30 These parts will only operate at the specified core to bus frequency ratio and lower. ® ® These parts have some specifications that differ from those in the Intel Pentium Processor with 512-KB L2 Cache on 0.13 Micron Process Datasheet. The specifications that are different from the datasheet are: Vmax = 1.425 V, Vmin = 1.350 V, Icc_max...

  • Page 31: Errata

    Errata Errata I/O Restart in SMM May Fail after Simultaneous Machine Check Exception (MCE). Problem: If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data for this instruction becomes corrupted, the processor will signal a Machine Check Exception (MCE).
  • Page 32 The invalid opcode 0FFFh did not require a ModRM byte in previous generation Intel architecture processors, but does in the Pentium 4 processor. Implication: The use of an invalid opcode 0FFFh without the ModRM byte may result in a page or limit fault on the Pentium 4 processor.
  • Page 33 Workaround: Intel does not support the overlapping of any two or more MTRRs unless one of them is of UC memory type. Ensure that the system BIOS does not create overlapping memory ranges.
  • Page 34 Errata Workaround: Remove the software’s dependency on #AC having precedence over #PF. Alternately, correct the page fault in the page fault handler and then restart the faulting instruction. Status: For the steppings affected, see the Summary Tables of Changes. IERR# May Not go Active When an Internal Error Occurs Problem: If the processor hangs because a store to the system bus does not complete, the processor may not assert the IERR# signal.

  • Page 35: System Memory

    Errata Processor May Hang Due to Speculative Page Walks to Non-Existent System Memory Problem: A load operation that misses the Data Translation Lookaside Buffer (DTLB) will result in a page-walk. If the page-walk loads the Page Directory Entry (PDE) from cacheable memory and that PDE load returns data that points to a valid Page Table Entry (PTE) in uncacheable memory the processor will access the address referenced by the PTE.
  • Page 36 Errata Status: For the steppings affected, see the Summary Tables of Changes. IA32_MC0_STATUS Register Overflow Bit Not Set Correctly Problem: The Overflow Error bit (bit 62) in the IA32_MC0_STATUS register indicates, when set, that a machine check error occurred while the results of a previous error were still in the error reporting bank (i.e.
  • Page 37 Errata internal boundary conditions exist that may prevent the data breakpoint from being captured. Implication: When this erratum occurs, a data breakpoint will not be captured. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. MCA Error Code Field in IA32_MC0_STATUS Register May become out of Sync with the Rest of the Register Problem:...
  • Page 38 Errata MCA Error Incorrectly Logged As Prefetches Problem: An MCA error is being incorrectly logged as PREFETCH type errors in the Request sub-field of the Compound error code in the IA32_MC0_STATUS register. A store, which hits a double bit data error in the L2 cache, is incorrectly logged as a prefetch data error.
  • Page 39 RFO has completed. The processor does not see that the RFO has completed and will hang. Implication: When this erratum occurs, the processor will hang. Intel has not been able to reproduce this erratum with commercial software.
  • Page 40 Problem: The I/O buffers for the FERR#, PROCHOT# and THERMTRIP# signals are specified in ® ® the Intel Pentium 4 Processor in the 423-pin Package Datasheet as AGTL+ buffers. The buffers for these signals were instead designed with CMOS buffers.
  • Page 41 Errata Problem: The processor may incorrectly go to the Machine Check handler in the following scenario: • Error reporting is enabled in the IA32_MC1_CTL register, • The processor issues a Read for Ownership (RFO) that hits an L2 cache line in the Shared state, and •...
  • Page 42 Errata Problem: Bit 1 of the IA32_THERM_STATUS register (Thermal Status Log) is a sticky bit designed to be set to '1' if the thermal control circuit (TCC) has been active since either the previous processor reset or software cleared this bit. If TCC is active and the Thermal Status Log bit is cleared by a processor reset or by software, it will remain clear (set to ‘0’) as long as the TCC remains active.
  • Page 43 Errata Problem: When the processor detects errors it should attempt to report and/or recover from the error. In the situations described below, the processor does not report and/or recover from the error(s) as intended. • When a transaction is deferred during the snoop phase and subsequently receives a Hard Failure response, the transaction should be removed from the bus queue so that the processor may proceed.
  • Page 44 Errata • If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data for this instruction becomes corrupted, the processor will signal a Machine Check Exception (MCE). If the instruction is directed at a device that is powered down, the processor may also receive an assertion of SMI#.
  • Page 45 Errata issued to the bus before the processor vectors to the machine check handler. Once the chipset receives its last Stop Grant special cycle it is allowed to ignore any bus activity from the processors. As a result, processor accesses to the machine check handler may not be acknowledged, resulting in a processor hang.
  • Page 46 Errata Possible Machine Check Due to Line-Split Loads with Page-Tables in Uncacheable (UC) Space Problem: The processor issues a speculative load which splits a 64-byte cache line. At the same time the page miss handling logic completes a page-walk for a different load. The resulting translation fills the DTLB and evicts the TLB entry to be used by the line-split load.
  • Page 47 Errata instruction pointer (LIP) is pointing to a floating-point instruction whose instruction bytes are in UC space and which takes an exception 16 (floating point error exception). The processor stalls trying to fetch the bytes of the faulting floating-point instruction and those following it. This processor hang is caused by interactions between thermal control circuit and floating-point event handler.
  • Page 48 Intel has not been able to reproduce this erratum with commercial software. Implication: Should this erratum be encountered the processor will livelock resulting in a system hang or operating system failure.
  • Page 49 UnCacheable (UC) address translation with the Data Translation Look-Aside Buffer, an unintended UnCacheable load operation may be sent out on the system bus. Implication: When this erratum occurs, an unintended load may be sent on system bus. Intel has only encountered this erratum during pre-silicon simulation.
  • Page 50 . System designers should evaluate whether a particular system is affected by this ® ® erratum. Designs that follow the recommendations in the Intel Pentium ® Processor and Intel 850 Chipset Platform Design Guide are not expected to be affected.
  • Page 51 Errata Processor May Hang When Resuming from Deep Sleep State Problem: When resuming from the Deep Sleep state the address strobe signals (ADSTB [1:0]#) may become out of phase with respect to the system bus clock (BCLK). Implication: When this erratum occurs, the processor will hang. Workaround: The system BIOS should prevent the processor from going to the Deep Sleep state.
  • Page 52 The incorrect data is corrected before the completion of the LSS instruction but the value of CR2 and the error code pushed on the stack are reflective of the speculative state. Intel has not observed this erratum with commercially available software.
  • Page 53 4. The writeback from the WC Buffers completes leaving stale data, for cacheline A, in the Exclusive (E) state in the L2 cache. Implication: Stale data may be consumed leading to unpredictable program execution. Intel has not been able to reproduce this erratum with commercial software.
  • Page 54 Errata Workaround: It is possible for BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. Re-Mapping the APIC Base Address to a Value Less Than or Equal to 0xDC001000 May Cause IO and Special Cycle Failure Problem: Remapping the APIC base address from its default can cause conflicts with either I/O or special cycle bus transactions.
  • Page 55 Errata Implication: Processor may fetch incorrect data, resulting in BIOS failure. Workaround: De-asserting and re-asserting A20M# prior to the data access will workaround this erratum. Status: For the steppings affected, see the Summary Tables of Changes. CPUID Instruction Returns Incorrect Number of ITLB Entries Problem: When CPUID instruction is executed with EAX = 2 on a processor without Hyper- Threading Technology or with Hyper-Threading Technology disabled via power on...
  • Page 56 If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the processor may hang while trying to evict the line. Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any commercially available software.
  • Page 57 Errata Disabling a Local APIC Disables Both Logical Processor APICs on a Hyper-Threading Technology Enabled Processor Problem: Disabling a local APIC on one logical processor of a Hyper-Threading Technology enabled processor by clearing bit 11 of the IA32_APIC_BASE MSR will effectively disable the local APIC on the other logical processor.
  • Page 58 Errata Changes to CR3 Register Do Not Fence Pending Instruction Page Walks Problem: When software writes to the CR3 register, it is expected that all previous/outstanding code, data accesses and page walks are completed using the previous value in CR3 register.
  • Page 59 Errata Simultaneous Page Faults at Similar Page Offsets on Both Logical Processors of a Hyper-Threading Technology Enabled Processor May Cause Application Failure Problem: An incorrect value of CR2 may be presented to one of the logical processors of an HT Technology enabled processor if a page access fault is encountered on one logical processor in the same clock cycle that the other logical processor also encounters a page fault.
  • Page 60 Errata necessary to avoid a multi-agent livelock scenario in which the processor cannot gain ownership of a line and modify it before that data is snooped out by another agent. In the case of this erratum, split load lock instructions incorrectly trigger the use- once protocol.
  • Page 61 (SMC) logic, then the processor may be locked in the synchronization loop until the arrival of an interrupt or other event. Implication: If this erratum occurs in an HT Technology enabled system, the application may temporarily stop making forward progress. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 62 Errata Modified Cache Line Eviction from L2 Cache May Result in Writeback of Stale Data Problem: It is possible for a modified cache line to be evicted from the L2 cache just prior to another update to the same line by software. In rare circumstances, the processor may accrue two bus queue entries that have the same address but have different data.
  • Page 63 Implication: This erratum has not been observed in any commercially available operating system or application. The aliasing of memory regions, a condition necessary for this erratum ® to occur, is documented as being unsupported in the IA-32 Intel Architecture Software Developer's Manual, Volume 3, section 10.12.4, Programming the PAT.
  • Page 64 Translation Lookaside Buffer (TLB) and used for memory operations. This erratum has not been observed with any commercially available software. ® Workaround: The guidelines in the IA-32 Intel Architecture Software Developer's Manual should be followed. Status: For the steppings affected, see the Summary Tables of Changes.
  • Page 65 Define BTS/PEBS buffer such that BTS/PEBS absolute maximum minus BTS/PEBS buffer base is integer multiple of the corresponding record sizes as recommended in ® the IA-32 Intel Architecture Software Developer’s Manual, Volume 3. Status: For the steppings affected, see the Summary Tables of Changes.
  • Page 66 CR2. Implication: The value in CR2 is correct at the time that an architectural page fault is signaled. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 67 Exposure to this problem requires the use of a data write which spans a cache line boundary. Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with any commercially available software or system.
  • Page 68 Errata Status: For the steppings affected, see the Summary Tables of Changes. 104. Debug Status Register (DR6) Breakpoint Condition Detected Flags May be set Incorrectly Problem: The Debug Status Register (DR6) may report detection of a spurious breakpoint condition under certain boundary conditions when either: •...

  • Page 69: Specification Changes

    Specification Changes The Specification Changes listed in this section apply to the following documents: ® ® ® ® • Intel Pentium 4 Processor in the 423-pin Package, Intel Pentium 4 Processor in the 478-pin Package Datasheet ® ® • Intel Pentium 4 Processor in the 478-pin Package Datasheet ®...

  • Page 70: Specification Clarifications

    The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M, Pentium 4, and Intel Xeon processors) is a 64-bit counter that is set to 0 following a RESET of the processor. Following a RESET, the counter will increment even when the...
  • Page 71 The RDMSR and WRMSR instructions read and write the time-stamp counter, treating the time-stamp counter as an ordinary MSR (address 10H). In the Pentium 4, Intel Xeon, and P6 family processors, all 64-bits of the time-stamp counter are read using RDMSR (just as with RDTSC).
  • Page 72 Specification Clarifications 15.10.9 COUNTING CLOCKS The count of cycles, also known as clockticks, forms a basis for measuring how long a program takes to execute. Clockticks are also used as part of efficiency ratios like cycles per instruction (CPI). Processor clocks may stop ticking under circumstances like the following: •...
  • Page 73 Specification Clarifications § Specification Update...

  • Page 74: Documentation Changes

    Documentation Changes The Documentation Changes listed in this section apply to the following documents: ® ® ® ® • Intel Pentium 4 Processor in the 423-pin Package, Intel Pentium 4 Processor in the 478-pin Package Datasheet ® ® • Intel Pentium 4 Processor in the 478-pin Package Datasheet ®...

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