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Summary Tables of Changes
The following tables indicate the errata, specification changes, specification
clarifications, or documentation changes which apply to the processor. Intel may fix
some of the errata in a future stepping of the component, and account for the other
outstanding issues through documentation or specification changes as noted. These
tables uses the following notations:
Codes Used in Summary Tables
Stepping
X:
(No mark)
or (Blank box):
Page
(Page):
Status
Doc:
Plan Fix:
Fixed:
No Fix:
Row
Change bar to left of a table row indicates this erratum is either new or modified from
the previous version of the document.
Errata (Sheet 1 of 5)
Steppings
Number
E-1
L-1
N-0
BV1
X
X
X
BV2
X
X
X
BV3
X
X
X
BV4
X
X
X
BV5
X
X
X
BV6
X
X
X
8
Errata exists in the stepping indicated. Specification Change or
Clarification that applies to this stepping.
This erratum is fixed in listed stepping or specification change
does not apply to listed stepping.
Page location of item in this document.
Document change or update will be implemented.
This erratum may be fixed in a future stepping of the product.
This erratum has been previously fixed.
There are no plans to fix this erratum.
Status
No Fix
The Processor May Report a #TS Instead of a #GP Fault
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
No Fix
Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or
Lead to Memory-Ordering Violations.
No Fix
IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly
No Fix
Performance Monitor SSE Retired Instructions May Return Incorrect Values
IRET under Certain Conditions May Cause an Unexpected Alignment Check
No Fix
Exception
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some
No Fix
Transitions
ERRATA
Specification Update
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