Interrupt Control Register (Icr) - Fujitsu FR60 Hardware Manual

CHAPTER 11 INTERRUPT CONTROLLER

11.2.1 Interrupt Control Register (ICR)

An interrupt control register is provided for each of the interrupt input and sets the
interrupt level of the corresponding interrupt request.
■ Bit Configuration of Interrupt Control Register (ICR)
Figure 11.2-2 shows the bit configuration of the interrupt control register (ICR: Interrupt Control
Register).
Figure 11.2-2 Bit Configuration of the Interrupt Control Register (ICR)
Address 000440
■ Detailed Bit of Interrupt Control Register (ICR)
The following describes the bit functions of the interrupt control register (ICR).
[bit4 to bit0] ICR4 to ICR0 interrupt level setting
These bits, which are the interrupt level setting bits, specify the interrupt level of the
corresponding interrupt request.
If an interrupt request has an interrupt level specified in this register that exceeds the level
mask value specified in the interrupt level mask register (ILM) of the CPU, it is masked by
the CPU.
These bits are initialized to 11111
Table 11.2-1 shows the correspondence between possible interrupt level setting bits and
interrupt levels.
334
bit 7 6
- -
H
to
00046F
H
5 4 3 2
-
ICR4 ICR3 ICR2
R R/W R/W
by a reset.
B
1 0 Initial value
---11111
ICR1 ICR0
B
R/W R/W