Word Alignment - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS
3.7

Word Alignment

Since instructions and data are accessed in byte units, the addresses at which they
are placed depend on the instruction length or the data width.
■ Program Access
A program for the FR family must be placed at an address that is a multiple of "2".
Bit0 of the program counter (PC) is set to "0" if the PC is updated when an instruction is
executed.
Bit0 can be set to "1" only if an odd-number address is specified as the branch address.
If bit0 is set to "1", however, bit0 is invalid and an instruction must be placed at the address that
is a multiple of "2".
No odd-number address exception exists.
■ Data Access
If data in the FR family is accessed, forced alignment is applied to the address based on the
width.
• Word access:
• Halfword access: An address must be a multiple of "2". (The lowest-order bit is forcibly set to
• Byte access:
During word or halfword data access, some of the bits in the result of calculating an effective
address are forcibly set to "0". For example, in @(R13, Ri) addressing mode, the register before
addition is used without change in the calculation (even if the lowest-order bit is "1") and the
low-order bits are masked. A register before calculation is not masked.
[Example] LD @(R13, R2), R0
72
An address must be a multiple of "4". (The lowest-order 2 bits are forcibly
set to "00".)
"0".)
-
R13 00002222
R2 00000003
+)
Addition result 00002225
Address pin 00002224
H
H
H
Lower 2 bits forcibly masked
H