Address/Data Multiplex Interface - Fujitsu FR60 Hardware Manual

32-bit microcontroller mb91301 series

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CHAPTER 4 EXTERNAL BUS INTERFACE

Address/data Multiplex Interface

This section explains the following three cases of operation of the address/data

multiplex interface:

• Without external wait

• With external wait

• CSn -> RD/WRn setup

■ Without External Wait

Figure 4.7-1 shows the operation timing chart for (TYP3 to TYP0=0100

Figure 4.7-1 Timing Chart for the Address/Data Multiplex Interface (without External Wait)

Making a setting such as TYP3 to TYP0=01xx

data multiplex interface to be set.

If the address/data multiplex interface is set, set 8 bits or 16 bits for the data bus width

(DBW1, DBW0 bits). The 32 bit width is not supported.

In the address/data multiplex interface, the total of 3 cycles of 2 address output cycles + 1

data cycle becomes the basic number of access cycles.

In the address output cycles, AS is asserted as the output address latch signal.

However, when CSn -> RD/WRn setup delay (AWR1) is set to "0", the multiplex address

output cycle becomes only 1 cycle as shown in Figure 4.7-1, and address cannot be directly

latched at the rising edge of AS. Therefore, the address is fetched at the rising edge of

MCLK for the cycle which "L" is asserted to AS.

address[15:0]

address[15:0]

address [31:0]

in the ACR register enables the address/