Instruction Cache Statuses And Settings - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS
3.3.3

Instruction Cache Statuses and Settings

This section describes the state of the instruction cache in each operating modes and
how to set up the instruction cache.
■ Instruction Cache Status in Each Operating Mode
Table 3.3-2 shows the state of the instruction cache in each operating mode.
The disable and flush states are encountered if a bit manipulation or similar instruction has
changed only the related bit.
Table 3.3-2 Status of Instruction Cache in Each Operating Mode
Cache memory
Address tag
Subblock
valid bit
Tag LRU
Entry lock
bit
TAG
valid bit
RAM
Global lock
Autolock fail
Entry autolock
Control
register
Entry lock
clear
Enable
Flash
58
Just after reset
Previous state maintained
Contents undefined
Not rewritable while disabled
Previous state maintained
Contents undefined
Not rewritable while disabled
Previous state maintained
Contents undefined
Not rewritable while disabled
Previous state maintained
Contents undefined
Not rewritable while disabled
Previous state maintained
Contents undefined
Not rewritable while disabled
Previous state maintained
Contents undefined
Flashable while disabled
Previous state maintained
Normal mode
Flashable while disabled
Previous state maintained
Unlocked
Rewritable while disabled
Previous state maintained
No fail
Rewritable while disabled
Previous state maintained
Unlocked
Rewritable while disabled
Previous state maintained
No clearing
Rewritable while disabled
Disabled Disabled
Previous state maintained
Not flushed
Rewritable while disabled
Disable
Previous state maintained
Previous state maintained
Previous state maintained
Previous state maintained
Entry lock cleared
All entries invalid
Previous state maintained
Previous state maintained
Previous state maintained
Previous state maintained
Previous state maintained
Previous state maintained
Flashed in the cycle
following memory access
Returned to "0" thereafter
Flash