Clock Distribution - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS

3.12.3 Clock Distribution

An operating clock for each function is generated based on the base clock generated
from the source clock. A total of four internal operating clocks are provided. A divide-
by rate can be set independently for each of them.
This section describes these internal operating clocks.
■ CPU Clock (CLKB)
This clock is used for the CPU, internal memory, and internal buses.
It is used by the following circuits:
• CPU
• Built-in RAM
• Bit search module
• I-bus, D-bus, X-bus, and F-bus
• DMA controller
• DSU (development tool interface circuit)
Since 68 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by
rate and divide-by rate that results in a frequency exceeding this limit.
■ Peripheral Clock (CLKP)
This clock is used for peripheral circuits and peripheral buses.
It is used by the following circuits:
• Peripheral bus
• Clock controller (only for the bus interface)
• Interrupt controller
• Peripheral I/O ports
• I/O port bus
• External interrupt input
• UART
• 16-bit timer
• A/D converter
2
• I C interface
Since 34 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by
rate and divide-by rate that results in a frequency exceeding this limit.
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