14.6.2 FR30 Compatible Mode of DACK
FR30 compatible mode of DACK makes the DACK timing identical to the timing of DMA
used in FR30 devices. This section provides the timing charts for the DACK pin in
FR30 compatible mode for the following examples of transfer mode setting:
• 2-cycle transfer mode
• Fly-by transfer mode
■ Transfer Mode Settings
Set the transfer mode using the PFR register corresponding to the DACK pin.
When setting PFR, match the transfer mode (2-cycle transfer/fly-by transfer) of the corresponding
DMA channel.
Note:
If 2-cycle transfer is set in FR30 compatible mode, the transfer is synchronized with RD or WR/
WRn. To use WR, enable WR by setting "0X1X
❍ 2-cycle transfer mode
Figure 14.6-3 shows the timing chart in 2-cycle transfer mode.
RD
DQMUU/DQMUL
WR/WRn
DACK (AKxx=111
B
DACK (AKxx=001
B
DACK (AKxx=010
B
DACK (AKxx=011
B
DACK (AKxx=100
B
DACK (AKxx=101
B
DACK (AKxx=110
B
* : AKxx is the setting value in the PFR register that corresponds to the DMA channel.
Figure 14.6-3 Timing Chart in 2-Cycle Transfer Mode
*
)
*
)
2-cycle transfer setting disabled
*
)
*
)
*
)
*
)
*
)
CHAPTER 14 DMA CONTROLLER (DMAC)
" for TYPE3 to TYPE0 of the ACR register.
B
Same timing as the chip select
441