I 2 C Interface Operation - Fujitsu FR60 Hardware Manual

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CHAPTER 16 I C INTERFACE
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16.5 I C Interface Operation
This section explains the operation of the I
■ Operational Explanation
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The I C bus consists of two bidirectional bus lines used for transfer: one serial data line (SDA)
and one serial clock line (SCL). The I
(SDA and SCL), enabling wired logic.
❍ START Condition
Write "1" to the MSS bit while the bus is open (BB=0, MSS=0) to place the I
master mode and to generate a START condition.
The interface sends the value of the IDAR register as a slave address.
To generate a repeated START condition, write "1" to the SCC bit while the interrupt flag is set
in bus master mode (MSS = 1 and INT = 1: IBCR).
Write "1" to the MSS bit while the bus is being used (BB=1 and TRX=0: IBSR, MSS=0 and
INT=0: IBCR) to cause the interface to start transmission after waiting for the bus to be open. If,
during this time, the interface in slave mode is receiving a write access, it starts transmission
after the transfer is completed. Then the interface is open the bus.
If the interface is sending data, it does not start transmission even though the bus has been
released.
To use this feature, it is important to check the followings:
• Whether the interface is specified as a slave (MSS=0: IBCR, AAS=1: IBSR).
• Whether data byte transmission is normal (AL=1: IBSR) when the next interrupt is received.
❍ STOP Condition
Write "0" to the MSS bit in master mode (MSS=1, INT=1: IBCR) to generate a STOP condition
and to place the interface in slave mode. Writing "0" to the MSS bit in any other state is
irrelevant.
After the MSS bit is cleared, the interface tries to generate a STOP condition. However, a STOP
condition will not be generated if the SCL line is driven to L. An interrupt is generated after the
next byte is transferred.
Notes:
• It takes time from writing "0" to the MSS bit until the STOP condition is generated.
• Disabling the I
stops the operation immediately and generates an invalid clock on the SCL line.
• Before disabling the I
condition has occurred (BB=0: IBSR).
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C interface (DBL=1: IDBL or EN=0: ICCR) before the "STOP" condition occurs
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C interface (DBL=1: IDBL or EN=0: ICCR), check that the "STOP"
C interface.
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C interface has two corresponding open-drain I/O pins
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C interface in