Csn Delay Setting - Fujitsu FR60 Hardware Manual

CHAPTER 4 EXTERNAL BUS INTERFACE
4.5.8

CSn Delay Setting

This section shows the operation timing for the CSn delay setting.
■ Operation Timing for the CSn Delay Setting
Figure 4.5-8 shows the operation timing for (TYP3 to TYP0=0000
Figure 4.5-8 Operation Timing Chart for the CSn Delay Setting
MCLK
A31 to A00
AS
CSn
RD
READ
D31 to D00
WRn
WRITE
D31 to D00
If the W02 bit is "1", assertion starts in the cycle following the cycle in which AS is asserted. For
successive accesses, a negation period is inserted.
212
, AWR=000C ).
B H