Operating States Of The Counter - Fujitsu FR60 Hardware Manual

6.4

Operating States of the Counter

The counter state is determined by the CNTE bit of the control status register (TMCSR)
and the WAIT signal, which is an internal signal. The states that can be set including
the stop state, when CNTE=0 and WAIT=1 (STOP state); the startup trigger wait state,
when CNTE=1 and WAIT=1 (WAIT status); and the operation state, when CNTE=1 and
WAIT=0 (RUN state).
■ Operating States of the Counter
Figure 6.4-1 shows the state transitions.
Reset
CNTE=1, WAIT=1
WAIT
Counter: Holds the value
when it stops;
undefined just
after reset and
until data is
loaded
Figure 6.4-1 Status Transitions of Counter
STOP
CNTE=0, WAIT=1
Counter: Holds the value
when it stops;
undefined just
after reset
CNTE=1
CNTE=1
TRG=1
TRG=0
RELD UF
TRG=1
LOAD CNTE=1, WAIT=0
Loads contents of reload
register into counter.
CHAPTER 6 16-BIT RELOAD TIMER
State transition due to hardware
State transition due to register access
CNTE=1, WAIT=0
RUN
Counter: Running
TRG=1
RELD UF
Load completed
279