Clk Synchronous Mode - Fujitsu FR60 Hardware Manual

13.3.2 CLK Synchronous Mode

If the UART is used in operating mode 2, the clock synchronous transfer method is
used.
■ Transfer Data Format
The UART handles only data in the NRZ (Non Return to Zero) format.
Figure 13.3-2 shows the relationship between send and receive clocks and data.
Writing to SODR
RXE, TXE
When the internal clock (U-TIMER) has been selected, a data receive synchronous clock is
automatically generated as soon as data is sent. While an external clock has been selected, you
must check that data exists in the send data buffer SODR register of the send side UART
(TDRE flag is "0") and then supply an accurate clock for one byte. Before sending starts and
after it ends, be sure to set the mark level.
The data length is 8 bits only, and no parity can be added. Only overrun errors are detected
because there is no start or stop bit.
Figure 13.3-2 Transfer Data Format (Mode 2)
SCK
SI, SO
1
LSB
Data that has been transferred is 01001101
0 1 1 0 0 1 0
MSB
CHAPTER 13 UART
Mark
(Mode 2)
.
B
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