Configuration Of The Instruction Cache - Fujitsu FR60 Hardware Manual

3.3.1

Configuration of the Instruction Cache

This section describes the configuration of the instruction cache.
■ Overview of Specifications
The following is an overview of the instruction cache specifications:
• FR family basic instruction length: 2 bytes
• Block layout method: 2-way set associative
• Block: One way consists of 128 blocks.
One block consists of 16 bytes (= 4 sub blocks).
One sub block consists of 4 bytes (= 1 bus access unit)
■ Configuration of Instruction Cache
Figure 3.3-1 shows the configuration of the instruction cache.
4 bytes
Way 1
Cache tag
128 blocks
Cache tag
Way 2
Cache tag
128 blocks
Cache tag
Figure 3.3-1 Configuration of Instruction Cache
4 bytes
I3
Subblock 3 Subblock 2
Subblock 3 Subblock 2
Subblock 3 Subblock 2
Subblock 3 Subblock 2
CHAPTER 3 CPU AND CONTROL UNITS
4 bytes 4 bytes
I2 I1
Subblock 1
Subblock 1
Subblock 1
Subblock 1
4 bytes
I0
Subblock 0 Block 0
Subblock 0 Block 127
Subblock 0 Block 0
Subblock 0 Block 127
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