Transfer Count Control - Fujitsu FR60 Hardware Manual

CHAPTER 14 DMA CONTROLLER (DMAC)

14.3.6 Transfer Count Control

Specify the transfer count within the range of the maximum 16-bit length (1 to 65536).
■ Transfer Count Control
Set the transfer count value in the transfer count register (DTC of DMACA).
The register value is stored in the temporary storage buffer when the transfer starts and is
decremented by the transfer counter. When the counter value becomes "0", end of transfer for
the specified count is detected, and the transfer on the channel is stopped or waiting for a
restart request starts (when reload is specified).
The following are some features of the group of transfer count registers:
• Each register has 16-bit length.
• All registers have a dedicated reload register.
• If transfer is activated when the register value is "0", transfer is performed 65536 times.
■ Reload Operation
• The reload operation can be used only if reloading is enabled in a register that allows
reloading.
• When transfer is activated, the initial value of the count register is saved in the reload
register.
• If the transfer counter counts down to "0", end of transfer is reported and the initial value is
read from the reload register and written to the count register.
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