Cache Enable Register (Cher) - Fujitsu FR60 Hardware Manual

CHAPTER 4 EXTERNAL BUS INTERFACE
4.2.8

Cache Enable Register (CHER)

This section explains the configuration and functions of the cache enable register
(CHER).
■ Configuration of the Cache Enable Register (CHER)
The cache enable register (CHER: CacHe Enable Register) controls the transfer of data read
from each chip select area.
Figure 4.2-8 shows the configuration of the cache enable register (CHER).
Figure 4.2-8 Configuration of the Cache Enable Register (CHER)
Address
000681
■ Functions of Bits in the Cache Enable Register (CHER)
The following explains the functions of the bits in the cache enable register (CHER).
[bit23 to bit17] CHE7 to CHE0 (Cache Enable 7 to Cache Enable 0)
These bits enable and disable each chip select area for transfers to the built-in cache.
Table 4.2-37 Cache area setting
CHEn
0
1
174
bit 23 22 21
CHE7 CHE6 CHE5 CHE4 CHE3 CHE2 CHE1 CHE0 11111111
H
Not a cache area (data read from the applicable area is not saved in the cache)
Cache area (data read from the applicable area is saved in the cache)
20 19 18 17
Cache area setting
16 Initial value
(INIT)
B
11111111 (RST)
B
Access
R/W