Dma Fly-By Transfer (Memory -> I/O) - Fujitsu FR60 Hardware Manual

4.5.11 DMA Fly-By Transfer (Memory -> I/O)
This section shows the operation timing for DMA fly-by transfer (memory -> I/O).
■ Operation Timing for DMA Fly-By Transfer (Memory -> I/O)
Figure 4.5-11 shows the operation timing chart for (TYP3 to TYP0=0000
IOWR=51
Figure 4.5-11 Timing Chart for DMA Fly-By Transfer (Memory -> I/O)
Basic cycle
MCLK
A31 to A00
AS
CSn
RD
D31 to D00
IOWR
• Setting "1" for the HLD bit of the IOWR0, IOWR1 registers enables the I/O read cycle to be
extended by one cycle.
• Setting the WR1, WR0 bits of the IOWR0, IOWR1 registers enables 0 to 3 write recovery
cycles to be inserted.
• If the write recovery cycle is set to "1" or more, a write recovery cycle is always inserted after
write access.
• Setting bits IW3 to IW0 of the IOWR0,IOWR1 registers enables 0 to 15 wait cycles to be
inserted.
• If wait is also set on the memory side (AWR15 to AWR12 is not "0"), the larger value is used
as the wait cycle after comparison with the I/O wait (IW3 to IW0 bits).
). This timing chart shows a case in which a wait is not set on the memory side.
H
I/O wait I/O hold
cycle wait
CHAPTER 4 EXTERNAL BUS INTERFACE
I/O idle
cycle
Basic cycle
, AWR=0008
B
I/O wait I/O hold
cycle wait
,
H
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