Auto-Wait Cycle - Fujitsu FR60 Hardware Manual

CHAPTER 4 EXTERNAL BUS INTERFACE
4.5.5

Auto-Wait Cycle

This section shows the operation timing for the auto-wait cycle.
■ Auto-Wait Cycle Timing
Figure 4.5-5 shows the operation timing for (TYP3 to TYP0=0000
READ
WRITE
• Setting of the W15 to W12 bits (first wait cycles) of the AWR register enables 0 to 15 auto-
wait cycles to be set.
• In Figure 4.5-5, two auto-wait cycles are inserted, making a total of four cycles for access. If
auto-wait is set, the minimum number of bus cycles is 2 cycles + (first wait cycles). For a
write operation, the minimum number of bus cycles may be still longer depending on the
internal state.
208
Figure 4.5-5 Timing Chart for the Auto-Wait Cycle
Basic cycle
MCLK
A31 to A00
AS
CSn
RD
D31 to D00
WRn
D31 to D00
, AWR=2008
B
Wait cycle
).
H