Reset Sources - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS

3.11.2 Reset Sources

This section describes the reset sources and the reset levels in the FR family device.
To determine reset sources that have occurred in the past, read the RSRR (reset
source register). For more information about registers and flags described in this
section, see Section "3.12.5 Block Diagram of Clock Generation Controller" and
"3.12.6 Register of Clock Generation Controller".
■ INIT Pin Input (Settings Initialization Reset Pin)
The INIT pin, which is an external pin, is used as the settings initialization reset pin.
A settings initialization reset (INIT) request is generated while the "L" level is being input to this
pin.
Input the "H" level to this pin to clear a settings initialization reset (INIT) request.
If a settings initialization reset (INIT) is generated in response to a request from this pin, bit15
(INIT bit) of the RSRR (reset source register) is set.
Because a settings initialization reset (INIT) in response to a request from this pin has the
highest interrupt level among all reset sources, it has precedence over any other input,
operation, or state.
Immediately after power-on, be sure to apply a settings initialization reset (INIT) at the INIT pin.
To assure the oscillation stabilization wait time for the oscillation circuit immediately after power-
on, input the "L" level to the INIT pin for the stabilization wait time required by the oscillation
circuit. INIT at the INIT pin initializes the oscillation stabilization wait time to the minimum value.
• Reset source:
• Source of clearing: "H" level input to the external INIT pin
• Reset level:
• Corresponding flag: bit15 (INIT)
■ Software Reset (STCR: SRST Bit Writing)
If "0" is written to bit4 (SRST bit) of the standby control register (STCR), a software reset
request occurs. A software reset request is an operation initialization reset (RST) request.
When the request is accepted and an operation initialization reset (RST) is generated, the
software reset request is cleared.
If an operation initialization reset (RST) is generated due to a software reset request, a bit11
(SRST bit) in the RSRR (reset source register) is set.
An operation initialization reset (RST) is generated due to a software reset request only after all
bus access has stopped and if bit7 (SYNCR bit) of the time base counter control register
(TBCR) has been set (synchronization reset mode). Thus, depending on the bus usage status,
a long time is required before an operation initialization reset (RST) occurs.
• Reset source:
• Source of clearing:Generation of an operation initialization reset (RST)
• Reset level:
• Corresponding flag:bit11(SRST)
96
"L" level input to the external INIT pin
Settings initialization reset (INIT)
Writing "0" to bit4 (SRST) of the standby control register (STCR)
Request of operation initialization reset (RST)