Power-On Sequence - Fujitsu FR60 Hardware Manual

4.9.2

Power-on Sequence

This section describes the power-on sequence.
■ Power-on Sequence
Setting the PON bit in the refresh control register (RCR) to "1" initiates the power-on sequence.
Take the following steps to set the PON bit to "1" for transition to the power-on sequence.
1) Reserve the clock stabilization wait time specified in the SDRAM/FCRAM manual.
2) Set ACR, AWR, MCRA(B).
3) Set the CSER to enable the area to which SDRAM/FCRAM has been connected.
4) Set the PON bit to "1" while setting the RCR value.
Taking the above steps causes the SDRAM/FCRAM interface to execute the following power-on
sequence.
5) Execute the PALL command.
6) Execute the REF command eight times.
7) The mode register is set according to the BST bit in the ACR, CL (CAS Latency) bit in the
AWR, and the WBST bit in the MCRA.
8) Transition to the normal access state
CHAPTER 4 EXTERNAL BUS INTERFACE
229