Serial Control Register (Scr) - Fujitsu FR60 Hardware Manual

13.2.2 Serial Control Register (SCR)

The serial control register (SCR) controls the transfer protocol that is used for serial
communication.
This section describes the configuration and functions of the serial control register
(SCR).
■ Bit Configuration of Serial Control Register (SCR)
Figure 13.2-4 shows the bit configuration of the serial control register (SCR).
Figure 13.2-4 Bit Configuration of the Serial Control Register (SCR)
Address: 000062
H
00006A
H
000072
H
■ Detailed Bit of Serial Control Register (SCR)
The following describes each bit function of the serial control register (SCR).
[bit7] PEN (Parity Enable): Setting of parity
This bit specifies whether data communication is performed to add parity in serial communication.
Table 13.2-4 shows the setting of the parity.
Table 13.2-4 Function for Setting of Parity
PEN
Note:
Parity can be added only in normal mode (Mode 0) of asynchronous (start-stop synchronization)
communication mode. No parity can be added in multiprocessor mode (Mode 1) or CLK
synchronous communication mode (Mode 2).
[bit6] P (Parity): Specifying of even/odd parity
This bit specifies that even or odd parity be added to perform data communication.
Table 13.2-5 shows specifying of even/odd parity.
Table 13.2-5 Function for Specifying of Even/Odd Parity
bit 7 6
(ch.0)
PEN P SBL
(ch.1)
R/W R/W R/W
(ch.2)
0 No parity
1 Parity
P
0 Even parity
1 Odd parity
5 4 3 2
CL A/D REC
R/W R/W W
Function
[initial value]
Function
[initial value]
CHAPTER 13 UART
1 0 Initial value
00000100
RXE TXE
B
R/W R/W
365